DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6, 8-12, 14-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al (U.S. Pub #2021/0343616), in view of Hwang et al (U.S. Pub #2013/0221519).
With respect to claim 1, Choi teaches a semiconductor package comprising:
a first semiconductor chip (Fig. 1, bottom chip 200) including a first substrate having a first surface and a second surface (Fig. 1, upper surface of bottom chip 200) opposite to the first surface, first through electrodes (Fig. 1, 230), first signal bonding pads (Fig. 1, 270S and Paragraph 43), and first dummy bonding pads (Fig. 1, 270T and Paragraph 45), wherein the first through electrodes (Fig. 1, 230) penetrate the first substrate, wherein the first signal bonding pads are provided on the second surface and are electrically connected to the first through electrodes, and wherein the first dummy bonding pads are provided on the second surface and are electrically insulated from the first through electrodes (Paragraph 45);
a second semiconductor chip (Fig. 1, second to bottom chip 200) stacked on the second surface of the first semiconductor chip, wherein the second semiconductor chip includes a second substrate having a third surface (Fig. 1, lower surface of second to bottom chip 200) and a fourth surface (Fig. 1, upper surface) opposite to the third surface and a plurality of second chip pads that are provided on the third surface and that are respectively corresponding to the first signal bonding pads (Fig. 1, 270S) and the first dummy bonding pads (Fig. 1, 270T);
first conductive bumps (Fig. 1, 260S and Paragraph 39) interposed between the first signal bonding pads and the corresponding second chip pads; and
second conductive bumps (Fig. 1, 260T and Paragraph 39) interposed between the first dummy bonding pads and the corresponding second chip pads,
Choi does not teach
wherein each of the first conductive bumps includes a signal bump pad and a first solder bump, wherein the signal bump pad is provided on a second chip pad of the plurality of second chip pads and has a dimple in an upper portion thereof, and wherein the first solder bump is provided on the signal bump pad, and
each of the second conductive bumps includes a thermal bump pad and a second solder bump, wherein the thermal bump is provided on a second chip pad of the plurality of second chip pads and has a flat upper surface, and wherein the solder bump is provided on the thermal bump pad.
Hwang teaches
wherein each of the first conductive bumps includes a signal bump pad (Fig. 3, 155a) and a first solder bump (Fig. 3, 175a’), wherein the signal bump pad is provided on a chip pad (Fig. 3, 132) and has a dimple in an upper portion thereof, and wherein the first solder bump is provided on the signal bump pad, and
each of the second conductive bumps (Fig. 3, dummy bumps 180b) includes a thermal bump pad (Fig. 3, 155b) and a second solder bump (Fig. 3, 175b’), wherein the thermal bump is provided on a second chip pad of the plurality of second chip pads and has a flat upper surface (Fig. 3, 155b), and wherein the solder bump is provided on the thermal bump pad.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a signal bump pad having a dimple and a thermal bump pad that is flat on the first and second chip pads of Choi as taught by Hwang in order to distribute stress on the pads and improve reliability (Paragraph 59-60).
With respect to claim 4, Choi does not the signal bump pad includes nickel, and the thermal bump pad includes copper.
Hwang teaches that the signal bump pad includes nickel (Paragraph 54), and the thermal bump pad includes copper (Fig. 3, 170b and Paragraph 56).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide nickel and copper in the respective bump pads as taught by Hwang in order to prevent diffusion (Paragraph 55).
With respect to claim 5, Choi does not teach that the thermal bump pad includes a first plating pad and a second plating pad provided on the first plating pad.
Hwang teaches that the thermal bump pad includes a first plating pad and a second plating pad provided on the first plating pad (Fig. 3, 150a, 155a, and 170a).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a first plating pad and a second plating pad as taught by Hwang in order to prevent diffusion (Paragraph 55).
With respect to claim 6, Hwang teaches that the first plating pad includes copper (Fig. 3, 170a and Paragraph 114), and the second plating pad includes nickel (Fig. 3, 155a/150a).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a first plating pad and a second plating pad as taught by Hwang in order to prevent diffusion (Paragraph 55).
With respect to claim 8, Choi teaches that each of the signal bump pad and the thermal bump pad have a diameter within a range of about 10 pm to about 20 pm (Paragraph 76).
With respect to claim 9, Choi teaches an adhesive layer (Fig. 1, 350 and Paragraph 53) filling spaces between the first conductive bumps and the second conductive bumps and between the first semiconductor chip and the second semiconductor chip, and attaching the first and second semiconductor chips to each other.
With respect to claim 10, Choi teaches that the second semiconductor chip includes a second wiring layer (Fig. 3A, BEOL layers) provided on the third surface of the second substrate, and the second chip pads (Fig. 3A, PIL) are provided on the second wiring layer.
With respect to claim 11, Choi teaches semiconductor package comprising: first, second, third and fourth semiconductor chips (Fig. 1, chips 200) sequentially stacked on one another via conductive connection members (Fig. 1, 230),
wherein each of the first, second, third and fourth semiconductor chips includes a substrate having a first surface and a second surface opposite to each other, and signal chip pads (Fig. 1, 270S and Paragraph 43) and dummy chip pads (Fig. 1, 270T and Paragraph 45) provided on the first surface of the substrate,
wherein each of the conductive connection members include first conductive bumps (Fig. 1, 260S) and second conductive bumps (Fig. 1, 260T), wherein the first conductive bumps are disposed on the signal chip pads, and wherein second conductive bumps are disposed on the dummy chip pads,
Choi does not teach
wherein each of the first conductive bumps includes a signal bump pad and a first solder bump, wherein the signal bump pad is provided on the signal chip pad and has a dimple in an upper portion thereof, and wherein the first solder bump is provided on the signal bump pad, and wherein each of the second conductive bumps includes a thermal bump pad and a second solder bump, wherein the thermal bump pad is provided on the dummy chip pad and has a flat upper surface, and wherein the second solder bump is provided on the thermal bump pad.
Hwang teaches
wherein each of the first conductive bumps includes a signal bump pad (Fig. 3, 155a) and a first solder bump (Fig. 3, 175a’), wherein the signal bump pad is provided on a chip pad (Fig. 3, 132) and has a dimple in an upper portion thereof, and wherein the first solder bump is provided on the signal bump pad, and
each of the second conductive bumps (Fig. 3, dummy bumps 180b) includes a thermal bump pad (Fig. 3, 155b) and a second solder bump (Fig. 3, 175b’), wherein the thermal bump is provided on a second chip pad of the plurality of second chip pads and has a flat upper surface (Fig. 3, 155b), and wherein the solder bump is provided on the thermal bump pad.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a signal bump pad having a dimple and a thermal bump pad that is flat on the first and second chip pads of Choi as taught by Hwang in order to distribute stress on the pads and improve reliability (Paragraph 59-60)
With respect to claim 12, Choi teaches that each of the first, second and third semiconductor chips includes through electrodes (Fig. 1, 230) penetrating the substrate, and the first conductive bumps are electrically connected to the through electrodes, and the second conductive bumps are electrically insulated from the through electrodes (Paragraph 45).
With respect to claim 14, Choi does not the signal bump pad includes nickel, and the thermal bump pad includes copper.
Hwang teaches that the signal bump pad includes nickel (Paragraph 54), and the thermal bump pad includes copper (Fig. 3, 170b and Paragraph 56).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide nickel and copper in the respective bump pads as taught by Hwang in order to prevent diffusion (Paragraph 55).
With respect to claim 15, Choi does not teach that the thermal bump pad includes a first plating pad and a second plating pad provided on the first plating pad.
Hwang teaches that the thermal bump pad includes a first plating pad and a second plating pad provided on the first plating pad (Fig. 3, 150a, 155a, and 170a).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a first plating pad and a second plating pad as taught by Hwang in order to prevent diffusion (Paragraph 55).
With respect to claim 16, Hwang teaches that the first plating pad includes copper (Fig. 3, 170a and Paragraph 114), and the second plating pad includes nickel (Fig. 3, 155a/150a).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a first plating pad and a second plating pad as taught by Hwang in order to prevent diffusion (Paragraph 55).
With respect to claim 18, Choi teaches adhesive layers (Fig. 1, 350 and Paragraph 53) filling spaces between the first conductive bumps and the second conductive bumps and between the first, second, third and fourth semiconductor chips, wherein the adhesive layers attach the first, second, third and fourth semiconductor chips to each other.
With respect to claim 19, Choi teaches that each of the first, second, third and fourth semiconductor chips includes a wiring layer (Fig. 3A, BEOL layers) provided on the first surface of the substrate, and the signal chip pads and the dummy chip pads are provided on the wiring layer (Fig. 3A, PIL).
With respect to claim 20, Choi teaches a semiconductor package comprising:
a buffer die (Fig. 1, 100);
first, second, third and fourth memory dies (Fig. 1, chips 200; Paragraph 24-25) sequentially stacked on the buffer die via conductive connection members (Fig. 1, 230); and
adhesive layers (Fig. 1 350 and Paragraph 53) disposed between the first to fourth memory dies and attaching the first, second, third and fourth memory dies to each other,
wherein each of the first, second, third and fourth memory dies includes a substrate having a first surface and a second surface opposite to the first surface and signal chip pads (Fig. 1, 270S and Paragraph 43) and dummy chip pads (Fig. 1, 270T and Paragraph 45) provided on the substrate,
wherein the conductive connection members include first conductive bumps (Fig. 1, 260S) and second conductive bumps (Fig. 1, 260T), wherein the first conductive bumps are disposed on the signal chip pads, and the second conductive bumps are disposed on the dummy chip pads,
Choi does not teach
wherein each of the first conductive bumps includes a signal bump pad and a first solder bump, wherein the signal bump pad is provided on the signal chip pad and has a dimple in an upper portion thereof, and the first solder bump is provided on the signal bump pad, and
wherein each of the second conductive bumps includes a thermal bump pad and a second solder bump, wherein the thermal bump pad is provided on the dummy chip pad and has a flat upper surface, and the second solder bump is provided on the thermal bump pad.
Hwang teaches
wherein each of the first conductive bumps includes a signal bump pad (Fig. 3, 155a) and a first solder bump (Fig. 3, 175a’), wherein the signal bump pad is provided on a chip pad (Fig. 3, 132) and has a dimple in an upper portion thereof, and wherein the first solder bump is provided on the signal bump pad, and
each of the second conductive bumps (Fig. 3, dummy bumps 180b) includes a thermal bump pad (Fig. 3, 155b) and a second solder bump (Fig. 3, 175b’), wherein the thermal bump is provided on a second chip pad of the plurality of second chip pads and has a flat upper surface (Fig. 3, 155b), and wherein the solder bump is provided on the thermal bump pad.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a signal bump pad having a dimple and a thermal bump pad that is flat on the first and second chip pads of Choi as taught by Hwang in order to distribute stress on the pads and improve reliability (Paragraph 59-60).
Claims 2, 3, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Choi and Hwang, in view of Gandhi et al (U.S. Pub #2016/0233139).
With respect to claim 2, Choi does not teach that the signal bump pad has a first thickness, and the thermal bump pad has a second thickness greater than the first thickness.
Gandhi teaches the thermal bump pad (Fig. 2, 206 and extended thickness 208) has a second thickness greater than the first thickness.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to form the thermal bump pad of Choi and Hwang to have a greater thickness than the signal bump pad as taught by Gandhi in order to provide a more thermally conductive path (Paragraph 19).
With respect to claim 3, Choi and Hwang teach that the first thickness of the signal bump pad is within a range of about 1 um to about 5 um, and the second thickness of the thermal bump pad is within a range of about 3 um to about 7 um (Paragraph 52-53, 107-108 of Hwang).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a signal bump pad and a thermal bump pad having thicknesses as taught by Hwang in order to distribute stress on the pads and improve reliability (Paragraph 59-60).
With respect to claim 13, Choi does not teach that the signal bump pad has a first thickness, and the thermal bump pad has a second thickness greater than the first thickness.
Gandhi teaches the thermal bump pad (Fig. 2, 206 and extended thickness 208) has a second thickness greater than the first thickness.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to form the thermal bump pad of Choi and Hwang to have a greater thickness than the signal bump pad as taught by Gandhi in order to provide a more thermally conductive path (Paragraph 19).
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Choi and Hwang, in view of Gandhi et al (U.S. Pub #2015/0221612).
With respect to claim 7, Choi does not teach that the signal bump pad has a first thermal conductivity, and the thermal bump pad has a second thermal conductivity greater than the first thermal conductivity.
Gandhi teaches a signal bump pad having a first thermal conductivity, and a thermal bump pad having a second thermal conductivity greater than the first thermal conductivity (Paragraph 18).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to form the thermal bump pad of Choi and Hwang to have a greater thermal conductivity than the signal bump pad as taught by Gandhi in order to improve heat transfer through the structure (Paragraph 18).
With respect to claim 17, Choi does not teach that the signal bump pad has a first thermal conductivity, and the thermal bump pad has a second thermal conductivity greater than the first thermal conductivity.
Gandhi teaches a signal bump pad having a first thermal conductivity, and a thermal bump pad having a second thermal conductivity greater than the first thermal conductivity (Paragraph 18).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to form the thermal bump pad of Choi and Hwang to have a greater thermal conductivity than the signal bump pad as taught by Gandhi in order to improve heat transfer through the structure (Paragraph 18).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN P SANDVIK whose telephone number is (571)272-8446. The examiner can normally be reached M-F: 10-6.
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/BENJAMIN P SANDVIK/ Primary Examiner, Art Unit 2812
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