Attorney Docket Number: 138789-5870-US
Filing Date: 11/30/2023
Claimed Foreign Priority Date: 12/19/2022 (KR10-2022-0177942)
Inventors: Baik et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the application filed 11/30/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the
first inventor to file provisions of the AIA . In the event the determination of the status of the
application as to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis
(i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of
rejection if the prior art relied upon, and the rationale supporting the rejection, would be the
same under either status.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made
Claims 1-3 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Boo (US 20240072024) in view of Clara (US 20160351739 A1).
Regarding claim 1, Boo (see, e.g., fig. 4), shows most aspects of the instant invention including a semiconductor package comprising:
A substrate (e.g., substrate 424) extending in first (e.g., horizontal direction) and second directions (e.g., vertical direction) that intersect each other;
A first semiconductor chip stack (e.g., first 3D stack 421a) disposed on the substrate (e.g., substrate 424) and including a plurality of first semiconductor chips (e.g., left-side electronic devices 422 + paragraph 43 “…electronic devices…can include chips, semiconductor dies, memory dies…”) stacked on each other;
A second semiconductor chip stack (e.g., second 3D stack 421b) disposed on the substrate (e.g., substrate 424), and spaced apart from the first conductive chip stack (e.g., first 3D stack 421a) in the first direction (e.g., horizontal direction), wherein the second semiconductor chip stack (e.g., second 3D stack 421b) includes a plurality of second semiconductor chips (e.g., right-side electronic devices 422 + paragraph 43 “…electronic devices…can include chips, semiconductor dies, memory dies…”) stacked on each other;
A mold layer (e.g., mold compound 429) covering the first (e.g., first 3D stack 421a) and second semiconductor chip stacks (e.g., second 3D stack 421b);
Boo, (see, e.g., fig. 4), however, fails to show a first spacer disposed on the first semiconductor chip stack and including a coupling layer, wherein the mold layer is in contact with the first spacer.
Clara (see, e.g., fig. 1C), in a similar device to Boo, teaches a spacer (e.g., intrinsic silicon spacer layer 106) disposed on a semiconductor structure (e.g., second semiconductor layer structure 107) and including a coupling layer (see, e.g., paragraph 118).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the spacer and coupling layer of Clara on the first semiconductor chip stack of Boo, in order to provide necessary protection and stability to the semiconductor chip stack. Note that if the spacer is added directly onto the first semiconductor chip stack, the molding compound (which covers the top surface of the chip stack) would contact said spacer.
Regarding claim 3, Boo (see, e.g., fig. 4) in view of Clara teaches wherein the first spacer (e.g., intrinsic silicon spacer layer 106) is not disposed on the second semiconductor chip stack (e.g., second 3D stack 421b).
Regarding claim 10, Clara (see, e.g., fig. 1C) teaches the coupling layer (see, e.g., paragraph 118) includes a silane coupling agent (see, e.g., paragraph 118 “…may be covered with silicon (e.g. the first intrinsic silicon spacer layer of the second semiconductor layer structure). To form the first intrinsic silicon spacer layer of the second semiconductor layer structure, a silicon precursor such as silane…may be applied or provided”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the silane of Clara within the spacer of Boo in view of Clara, as silane was a well-known material at the time of filing the invention to be included within a spacer, as taught by Clara.
Regarding claim 11, Boo (see, e.g., fig. 4), shows most aspects of the instant invention including a semiconductor package comprising:
A substrate (e.g., substrate 424) including a first area (e.g., substrate area under left-stack) and a second area (e.g., substrate area under right-stack) spaced apart from the first area (e.g., substrate area under left-stack);
A first semiconductor chip stack (e.g., first 3D stack 421a) disposed on the on the first area (e.g., substrate area under left-stack) and including a plurality of first semiconductor chips (e.g., left-side electronic devices 422 + paragraph 43 “…electronic devices…can include chips, semiconductor dies…”) stacked on each other;
A second semiconductor chip stack (e.g., second 3D stack 421b) disposed on the second area (e.g., substrate area under right-stack), and including a plurality of second semiconductor chips (e.g., right-side electronic devices 422 + paragraph 43 “…electronic devices…can include chips, semiconductor dies…”) stacked on each other;
A mold layer (e.g., mold compound 429) in contact with a first surface (e.g., top surface of second 3D stack 421b) of the second semiconductor chip stack (e.g., second 3D stack 421b);
Boo, (see, e.g., fig. 4), however, fails to show a first spacer disposed on the first semiconductor chip stack and including a coupling layer, wherein the mold layer is in contact with the first spacer.
Clara (see, e.g., fig. 1C), in a similar device to Boo, teaches a spacer (e.g., intrinsic silicon spacer layer 106) disposed on a semiconductor structure (e.g., second semiconductor layer structure 107) and including a coupling layer (see, e.g., paragraph 118).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the spacer and coupling layer of Clara on the first semiconductor chip stack of Boo, in order to provide necessary protection and stability to the semiconductor chip stack.
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Boo in view of Clara further in view of Niwa (US 20210249373 A1).
Regarding claim 2, Boo in view of Clara fails to teach wherein an upper surface of the first spacer and an upper surface of the second semiconductor chip stack are disposed substantially on a same plane.
Niwa (see, e.g., fig. 15), in a similar device to Boo in view of Clara, teaches an upper surface of a first spacer (e.g., spacer chip 50) and an upper surface of a semiconductor chip (e.g., semiconductor chip 20) are disposed substantially on a same plane (see, e.g., paragraph 50 “It is preferable that a height of an upper surface of each spacer chip 50 is generally equal to a height of an upper surface of the semiconductor chip 20”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the same plane/height configuration of Niwa within the spacer-to-chip stack relationship of Boo in view of Clara, in order to improve flatness of the chip and spacer for any additional chip stacking as necessary, as taught by Niwa (see, e.g., paragraph 50).
Regarding claim 12, Boo in view of Clara fails to teach wherein an upper surface of the first spacer and an upper surface of the second semiconductor chip stack are disposed substantially on a same plane.
Niwa (see, e.g., fig. 15), in a similar device to Boo in view of Clara, teaches an upper surface of a first spacer (e.g., spacer chip 50) and an upper surface of a semiconductor chip (e.g., semiconductor chip 20) are disposed substantially on a same plane (see, e.g., paragraph 50 “It is preferable that a height of an upper surface of each spacer chip 50 is generally equal to a height of an upper surface of the semiconductor chip 20”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the same plane/height configuration of Niwa within the spacer-to-chip stack relationship of Boo in view of Clara, in order to improve flatness of the chip and spacer for any additional chip stacking as necessary, as taught by Niwa (see, e.g., paragraph 50).
Claims 5-6, 13-16, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Boo in view of Clara further in view of Kosaka (US 20200075543 A1).
Regarding claim 5, Boo in view of Clara fails to teach a controller disposed between the substrate and the second semiconductor chip stack.
Kosaka (see, e.g., fig. 9), in a similar device to Boo in view of Clara, teaches a controller (e.g., controller chip 16) disposed between a substrate (e.g., substrate 11) and a semiconductor chip stack (e.g., second memory chips 43).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the controller of Kosaka between the semiconductor chip stack and substrate of Boo in view of Clara, in order to achieve the expected result of providing management for data flow within the device.
Regarding claim 6, Kosaka (see, e.g., fig. 9) teaches a spacer (e.g., spacer 42) disposed between the controller (e.g., controller chip 16) and a semiconductor chip stack (e.g., second memory chips 43).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to dispose the spacer of Kosaka between the controller and second semiconductor chip stack of Boo in view of Clara further in view of Kosaka, in order to provide a barrier, preventing interference between the controller chip and semiconductor chip, resulting in improved reliability of the device.
Regarding claim 13, Boo in view of Clara fails to teach a controller disposed between the substrate and the second semiconductor chip stack.
Kosaka (see, e.g., fig. 9), in a similar device to Boo in view of Clara, teaches a controller (e.g., controller chip 16) disposed between a substrate (e.g., substrate 11) and a semiconductor chip stack (e.g., second memory chips 43).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the controller of Kosaka between the semiconductor chip stack and substrate of Boo in view of Clara, in order to achieve the expected result of providing management for data flow within the device.
Regarding claim 14, Kosaka (see, e.g., fig. 9) teaches wherein the controller (e.g., controller chip 16) is mounted on the substrate (e.g., substrate 11) by a wire bonding method (see, e.g., paragraph 67 “…the controller chip 16 is electrically connected to the wires(circuit) of the substrate 11 by wire bonding”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the wire bonding of Kosaka within the device of Boo in view of Clara further in view of Kosaka, as wire bonding was a well-known method at the time of filing the invention to mount a controller to a substrate and its circuits, as taught by Kosaka (see paragraph 67).
Regarding claim 15, Kosaka (see, e.g., fig. 9) teaches wherein the controller (e.g., controller chip 16) is mounted on the substrate (e.g., substrate 11) by a flip chip method (see, e.g., paragraph 67 “…the controller chip may be mounted on the first surface 11a by not limited to this example but another method such as flip chip mounting”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the timfiling the invention to include the flip chip mounting of Kosaka within the device of Boo in view of Clara further in view of Kosaka, as flip chip mounting was a well-known method at the time of filing the invention to mount a controller to a substrate, as taught by Kosaka (see paragraph 67).
Regarding claim 16, Boo in view of Clara fails to teach a second spacer disposed in the second area and including a silicon layer.
Kosaka (see, e.g., fig. 9), in a similar device to Boo in view of Clara, teaches a spacer (e.g., spacer 42) disposed in a second area (e.g., right-side of substrate 11) and including a silicon layer (see, e.g., paragraph 124 “The spacer 42 is produced from silicon…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the silicon spacer of Kosaka within the second area of Boo in view of Clara, in order to provide electrical protection between the second semiconductor chip stack and the controller chip, with electrical conductivity properties to connect the chip stack and controller chip when desired due to its silicon material.
Regarding claim 18, Boo (see, e.g., fig. 4), shows most aspects of the instant invention including a semiconductor package comprising:
A substrate (e.g., substrate 424) extending in first (e.g., horizontal direction) and second directions (e.g., vertical direction) that intersect each other;
A first semiconductor chip stack (e.g., first 3D stack 421a) disposed on the substrate (e.g., substrate 424) and including a plurality of first semiconductor chips (e.g., left-side electronic devices 422 + paragraph 43 “…electronic devices…can include chips, semiconductor dies, memory dies…”) stacked on each other;
A second semiconductor chip stack (e.g., second 3D stack 421b) disposed on the substrate (e.g., substrate 424), and spaced apart from the first conductive chip stack (e.g., first 3D stack 421a) in the first direction (e.g., horizontal direction), wherein the second semiconductor chip stack (e.g., second 3D stack 421b) includes a plurality of second semiconductor chips (e.g., right-side electronic devices 422 + paragraph 43 “…electronic devices…can include chips, semiconductor dies, memory dies…”) stacked on each other;
A mold layer (e.g., mold compound 429) covering the first (e.g., first 3D stack 421a) and second semiconductor chip stacks (e.g., second 3D stack 421b);
Boo, (see, e.g., fig. 4), however, fails to show a first spacer disposed on the first semiconductor chip stack and including a silane coupling layer, wherein the mold layer is in contact with the first spacer, while it also fails to teach a controller disposed between the substrate and the second semiconductor chip stack, and a second spacer disposed between the controller and the second semiconductor chip stack.
Clara (see, e.g., fig. 1C), in a similar device to Boo, teaches a spacer (e.g., intrinsic silicon spacer layer 106) disposed on a semiconductor structure (e.g., second semiconductor layer structure 107) and including a silane coupling layer (see, e.g., paragraph 118 “…may be covered with silicon (e.g. the first intrinsic silicon spacer layer of the second semiconductor layer structure). To form the first intrinsic silicon spacer layer of the second semiconductor layer structure, a silicon precursor such as silane…may be applied or provided”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the spacer and silane coupling layer of Clara on the semiconductor chip stacks of Boo, in order to provide necessary protection and stability to the semiconductor chip stack. Note that if the spacer is added directly onto the semiconductor chip stack, the molding compound (which covers the top surface of the chip stack) would contact said spacers.
Boo in view of Clara, however, fails to teach a controller disposed between the substrate and the second semiconductor chip stack and a second spacer disposed between the controller and the second semiconductor chip stack.
Kosaka (see, e.g., fig. 9), in a similar device to Boo in view of Clara, teaches a controller (e.g., controller chip 16) disposed between a substrate (e.g., substrate 11) and a semiconductor chip stack (e.g., second memory chips 43), and a spacer (e.g., spacer 42) disposed between the controller (e.g., controller chip 16) and a semiconductor chip stack (e.g., second memory chips 43).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the controller of Kosaka between the semiconductor chip stack and substrate of Boo in view of Clara, in order to achieve the expected result of providing management for data flow within the device. In addition, it also would have been obvious to one of ordinary skill in the art at the time of filing the invention to dispose the spacer of Kosaka between the controller and second semiconductor chip stack of Boo in view of Clara further in view of Kosaka, in order to provide a barrier, preventing interference between the controller chip and semiconductor chip, resulting in improved reliability of the device.
Regarding claim 19, Boo in view of Clara teaches wherein an upper surface of the first spacer (e.g., intrinsic silicon spacer 106 – note that spacer 106 was added directly on top of the first semiconductor chip stack, which was previously making contact with the mold layer) and an upper surface of the second semiconductor chip stack (e.g., second 3D stack 421b) are in contact with the mold layer (e.g., mold compound 29).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Boo in view of Clara further in view of Kosaka and Cho (US 20210013136 A1).
Regarding claim 7, Kosaka (see, e.g., fig. 9) teaches wherein the substrate (e.g., substrate 11) includes a wiring layer (see, e.g., paragraphs 21 – 22 “The substrate 11 is, for example, a printed a wiring hoard (PWB).“) first upper pad (e.g., left-side pad 21) electrically connected to a first semiconductor chip stack (e.g., first memory chips 33) through a first bonding wire (e.g., first wire 13), a second upper pad (e.g., right-side pad 21) electrically connected to the second semiconductor chip stack (e.g., second memory chips 43) through a second bonding wire (e.g., second wire 15) and a third upper pad (e.g., central pad 21) electrically connected to the controller (e.g., controller chip 16).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the pad and wire configuration of Kosaka within the substrate of Boo in view of Clara, in order to achieve the expected result of providing electrical connections between the chip stack/controller and substrate as necessary.
Boo in view of Clara further in view of Kosaka, however, fails to teach the substrate includes an insulating structure including an insulating layer and first and second passivation layers disposed on the insulating layer, and a wiring structure including a wiring structure including a first wiring layer disposed in the first passivation layer and a second wiring layer disposed in the second passivation layer.
Cho (see, e.g., fig. 1), in a similar device to Boo in view of Clara further in view of Kosaka, teaches a substrate (e.g., substrate 110) includes an insulating structure (e.g., dielectric structure 111) including an insulating layer (see, e.g., dielectric structure 111 + paragraph 20 “…dielectric structure 111 comprising one or more dielectric layers…”), and first (e.g., passivation layer 116) and second passivation layers (e.g., passivation layer 117) disposed on the insulating layer (e.g., dielectric structure 111), a wiring structure (e.g., wiring patterns 112a, 112b, 112c, and 113) including a first wiring layer (e.g., wiring pattern 112a) disposed in the first passivation layer (e.g., passivation layer 116) and a second wiring layer (e.g., wiring pattern 113) disposed in the second passivation layer (e.g., passivation layer 117).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the insulating structure, wiring pattern setup, and passivation structure configuration of Cho within the substrate of Boo in view of Clara further in view of Kosaka, in order to achieve the expected result of providing insulative/passivation protection around the substrate adjacent to the wiring structures, assisting in electrical and environmental protection and additional electrical connections as necessary within the device.
Regarding claim 8, Kosaka (see, e.g., fig. 9) teaches wherein the controller (e.g., controller chip 16) is electrically connected to the substrate (e.g., substrate 11) through a third bonding wire (e.g., third wire 17) that is connected to the third upper pad (e.g., central pad 21).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the third bonding wire of Kosaka to electrically connect the substrate and controller of Boo in view of Clara further in view of Kosaka and Cho, in order to achieve the expected result of electrically connecting the controller chip to the substrate.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Boo in view of Clara further in view of Kosaka, Cho, and Ye (US 20240072022 A1).
Regarding claim 9, Boo in view of Clara further in view of Kosaka further in view of Cho fails to teach wherein the controller is electrically connected to the substrate through a solder ball that is connected to the third upper pad.
Ye (see, e.g., fig. 1), in a similar device to Boo in view of Clara further in view of Kosaka and Cho, teaches a controller (e.g., controller die 122) is electrically connected to a substrate (e.g., package substrate 110) through a solder ball (e.g., solder structure 123 + paragraph 25 “…solder structures 123 (e.g., solder balls…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the solder balls of Ye on the third upper pad of Boo in view of Clara further in view of Kosaka and Cho, in order to achieve the expected result of providing additional electrical connection between the controller and the substrate as necessary.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Boo in view of Clara further in view of Kosaka and Niwa.
Regarding claim 20, Boo in view of Clara fails to teach wherein an upper surface of the first spacer and an upper surface of the second semiconductor chip stack are disposed substantially on a same plane.
Niwa (see, e.g., fig. 15), in a similar device to Boo in view of Clara, teaches an upper surface of a first spacer (e.g., spacer chip 50) and an upper surface of a semiconductor chip (e.g., semiconductor chip 20) are disposed substantially on a same plane (see, e.g., paragraph 50 “It is preferable that a height of an upper surface of each spacer chip 50 is generally equal to a height of an upper surface of the semiconductor chip 20”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the same plane/height configuration of Niwa within the spacer-to-chip stack relationship of Boo in view of Clara, in order to improve flatness of the chip and spacer for any additional chip stacking as necessary, as taught by Niwa (see, e.g., paragraph 50).
Allowable Subject Matter
Claims 4 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner
should be directed to Thomas McCoy at (571) 272-0282 and between the hours of 9:30 AM to 6:30 PM
(Eastern Standard Time) Monday through Friday or by e-mail via Thomas.McCoy@uspto.gov. If attempts
to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814