Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The changes made to the title in the response filed on May 11, 2026 are accepted by the examiner.
Claim Objections
The applicant’s amendments to claims 1-4 and 8 in the response filed on May 11, 2026 have overcome the objections to these claims in the Office action dated February 10, 2026. Therefore, the examiner has withdrawn the objections to claims 1-4 and 8 and claims that depend therefrom.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation “the gate insulating film disposed in the at least one of the trenches,” on page 6 lines 21-22. This limitation renders the claim indefinite because it is unclear whether gate insulating films are disposed in the pair of end trenches because claim 13 contains no prior recitation of gate insulating films disposed in the pair of end trenches. The examiner also notes that only a gate insulating film in the inner trench is previously recited, see claim 1 page 3 lines 22-24. For examination purposes, this limitation will be interpreted as reciting the gate insulating film disposed in the inner trench.
Claim 14 recites the limitation “the gate insulating film disposed in the at least one of the trenches,” on page 6 lines 25-26. This limitation renders the claim indefinite because it is unclear whether gate insulating films are disposed in the pair of end trenches because claim 14 contains no prior recitation of gate insulating films disposed in the pair of end trenches. The examiner also notes that only a gate insulating film in the inner trench is previously recited, see claim 6 page 5 lines 1-4. For examination purposes, this limitation will be interpreted as reciting the gate insulating film disposed in the inner trench.
Claim 15 recites the limitation “each of the inner trenches,” on page 7 lines 10, 12, 13, 14, , 15, and 16. This limitation lacks antecedent basis because claim 15 recites “an inner trench,” on page 7 line 8, which is a singular term, while the inner trenches is a plural term that requires at least two inner trenches. For examination purposes, this limitation will be interpreted as reciting the inner trench.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 6, 8, and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yamaoka et al. (JP 2009088186 A) in view Potera et al. (US 2024/0145537). The examiner notes that the citations to paragraphs in Yamaoka refer to paragraphs in the attached English language translation of Yamaoka.
Regarding Claim 1:
Yamaoka discloses a semiconductor device comprising:
a semiconductor layer (N+ type semiconductor layer and N- type semiconductor layer, See figs. 2a and 16, ref. nos. 11, 12, and paragraphs 12-13) formed with a plurality of trenches (trenches having a perimeter around the gate oxide film and the trench oxide film, See fig. 16, ref. nos. 13B, 16, paragraphs 12-13 and 32) in a surface layer portion (the trenches having a perimeter around the gate oxide film and the trench oxide film are formed in the N- type semiconductor layer, See figs. 3A, 8A, paragraphs 17-18 and 21-23); and
a plurality of trench gates (gate electrodes, See fig. 16, ref. no. 18 and paragraph 13) correspondingly provided in the plurality of trenches of the semiconductor layer, wherein
each of the plurality of trenches extends at least in a first direction (the trenches having a perimeter around the gate oxide film and the trench oxide film are shown in figure 16 extending in the horizontal direction, See fig. 16) in a plan view of the semiconductor layer,
the plurality of trenches are arranged apart from each other in a second direction (the trenches having a perimeter around the gate oxide film and the trench oxide film are shown in figure 16 arranged apart from each other in a vertical direction, See fig. 16) orthogonal to the first direction in the plan view of the semiconductor layer,
each of the plurality of trenches has a pair of end side walls (left sidewall and right sidewall, See fig. 16, ref. nos. 13B and 16) at ends in the first direction and a pair of longitudinal side walls (top sidewall and bottom sidewall, See fig. 16, ref. no. 13B and 16) extending between the pair of end side walls,
the plurality of trenches include a pair of end trenches located at opposite ends in the second direction (top trench and bottom trench, See fig. 16) and an inner trench (middle trench, See fig. 16) located between the pair of end trenches in the second direction,
and a gate insulating film (the gate oxide film and the trench oxide film, See fig. 16, ref. nos. 13B and 16) disposed in the inner trench has a larger thickness on the at least one of the end side walls than on the at least one of the intermediate portions of the longitudinal side walls (the trench oxide film on the right sidewall has a thickness greater than the gate oxide film in the center portion of the top sidewall, See fig. 16, ref. no. 13B, 16, and paragraph 13).
Yamaoka does not disclose at least one of the end side walls of the inner trench has a surface roughness larger than a surface roughness of at least one of intermediate portions of the longitudinal side walls of the inner trench, the intermediate portions being at an intermediate position of the inner trench in the first direction.
Potera discloses at least one of the end side walls of the inner trench (end surfaces of middle mesa stripe, See figs. 2A-2B, ref. no. 12 and paragraph 53) has a surface roughness larger than a surface roughness of at least one of intermediate portions of the longitudinal side walls of the inner trench, the intermediate portions being at an intermediate position of the inner trench in the first direction (the middle mesa stripe has end surfaces that are rougher than longitudinal sidewall surfaces, See figs. 2A-2B, ref. no. 12 and paragraph 53. The examiner also notes that the middle mesa strip is visually shown in figure 2B having an end surface rougher than a longitudinal sidewall surface with more lines indicating a rougher surface on the end surface. The examiner additionally notes Potera disclose a plurality of mesa stripes that includes the middle mesa stripe are formed using a plasma etch. See paragraph 53.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Yamaoka to include the trenches having a perimeter around the gate oxide film and the trench oxide film formed by a plasma etch such as that taught by Potera so that the top and bottom sidewalls of interior trenches have less under cutting because the top and bottom sidewalls are etched with a more anisotropic etch. (See Potera paragraph 53.)
Regarding Claim 3:
The above stated combination of Yamaoka and Potera disclose the above stated semiconductor device. Yamaoka further discloses middle trench has a larger width at the right end than at an intermediate position between the right end and the left end (See fig. 16).
The above stated combination of Yamaoka and Potera does not disclose wherein at least one of the trenches has a larger width at opposite ends in the first direction than at the intermediate portions of the longitudinal side walls between the opposite ends of the at least one of the trenches, the width being defined in the second direction.
Potera discloses electrically insulating both ends of a plurality of mesa stripes so that etch damage on the end surfaces of the plurality of mesa stripe does not substantially impact a JFET having the plurality of mesa stripes (See fig. 11, ref. nos. 12, 12E, 320, paragraph 52-53 and 76).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Yamaoka and Potera to include the left end of the middle trench having the same width and the trench oxide film as the right end of the middle trench as that taught by Potera so that etch damage on the left end of the middle trench does not substantially impact the semiconductor device. (See Potera paragraph 76.)
Regarding Claim 6:
Yamaoka discloses a manufacturing method of a semiconductor device, the method comprising:
forming a plurality of trenches (forming trenches having a perimeter around the gate oxide film and the trench oxide film in an N-type semiconductor layer, See fig. 3A, ref. no. 15, figs. 8A-8B, ref. no. 17, fig. 16, ref. nos. 13B, 16, paragraphs 12-13, 21-22, and 31-32) in an upper layer portion (N- type semiconductor layer, See figs. 2a and 16, ref. nos. 11, 12 and paragraphs 12-13) of a semiconductor layer (N+ type semiconductor layer and N- type semiconductor layer, See figs. 2a and 16, ref. nos. 11, 12 and paragraphs 12-13); and
forming a plurality of trench gates (forming gate electrodes, See figs. 10A-11B, ref. nos. 18, 18P, fig. 16, ref. no. 18, paragraphs 13 and 24-25) correspondingly in the plurality of trenches of the semiconductor layer, wherein
in the forming of the plurality of trenches,
each of the plurality of trenches is formed to extend at least in a first direction (the trenches having a perimeter around the gate oxide film and the trench oxide film are shown in figure 16 extending in the horizontal direction, See fig. 16) in a plan view of the semiconductor layer, and to have a pair of end side walls (left sidewall and right sidewall, See fig. 16, ref. nos. 13B and 16) at opposite ends in the first direction walls and a pair of longitudinal side walls (top sidewall and bottom sidewall, See fig. 16, ref. no. 13B and 16) extending between the end side walls,
the plurality of trenches are formed to be arranged spaced apart from each other in a second direction (the trenches having a perimeter around the gate oxide film and the trench oxide film are shown in figure 16 arranged apart from each other in a vertical direction in figure, See fig. 16) orthogonal to the first direction in the plan view of the semiconductor layer, and to include a pair of end trenches located at opposite ends (top trench and bottom trench, See fig. 16) in the second direction and an inner trench (middle trench, See fig. 16) located between the pair of end trenches in the second direction, and
the forming of the plurality of trench gates includes forming a gate insulating film (forming the trench oxide film and the gate oxide film, See figs. 4A-4B, ref. no. 16A, fig. 5A, ref. no. 16, figs. 9A-9B, ref. no 13B, fig. 16, ref. nos. 13B, 16, paragraph 18 and 23) in the inner trench so that a thickness of the gate insulating film on at least one of the end side walls of the inner trench is larger than a thickness of the gate insulating film on at least one of intermediate portions of the longitudinal side walls of the inner trench, the intermediate portions being at an intermediate position of the inner trench in the first direction (the trench oxide film on the right sidewall has a thickness greater than the gate oxide film in the center portion of the top sidewall, See fig. 16, ref. no. 13B, 16, and paragraph 13).
Yamaoka does not disclose a state where the at least one of the end side walls of the inner trench has a surface roughness larger than a surface roughness of the at least one of the intermediate portions of the longitudinal side walls of the inner trench.
Potera discloses a state (a state of the plurality of mesa stripes after plasma etching, See figs. 2A-2B, ref. no. 12 and paragraph 53) where the at least one of the end side walls of the inner trench (end surfaces of middle mesa stripe, See figs. 2A-2B, ref. no. 12 and paragraph 53) has a surface roughness larger than a surface roughness of the at least one of the intermediate portions of the longitudinal side walls of the inner trench (the middle mesa stripe has end surfaces that are rougher than longitudinal sidewall surfaces, See figs. 2A-2B, ref. no. 12 and paragraph 53. The examiner also notes that the middle mesa strip is visually shown in figure 2B having an end surface rougher than a longitudinal sidewall surface with more lines indicating a rougher surface on the end surface.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing a semiconductor device of Yamaoka to include plasma etching the trenches having a perimeter around the gate oxide film and the trench oxide film such as that taught by Potera so that the top and bottom sidewalls of interior trenches have less under cutting because the top and bottom sidewalls are etched with a more anisotropic etch. (See Potera paragraph 53.)
Regarding Claim 8:
The above stated combination of Yamaoka and Potera discloses the above stated method of manufacturing a semiconductor device. Yamaoka further discloses forming the middle trench with a larger width at the right end than at an intermediate position between the right end and the left end (See figs. 3A, ref. no. 15, fig. 16, and paragraph 17).
The above stated combination of Yamaoka and Potera does not disclose wherein the forming of the plurality of trenches includes forming at least one of the plurality of trenches so that a width at opposite ends in the first direction is larger than a width at the intermediate position between the opposite ends, the width being defined in the second direction.
Potera discloses electrically insulating both ends of a plurality of mesa stripes so that etch damage on the end surfaces of the plurality of mesa stripe does not substantially impact a JFET having the plurality of mesa stripes (See fig. 11, ref. nos. 12, 12E, 320, paragraph 52-53 and 76).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing a semiconductor device of Yamaoka and Potera to include forming the left end of the middle trench having the same width and the trench oxide film as the right end of the middle trench as that taught by Potera so that etch damage on the left end of the middle trench does not substantially impact the semiconductor device. (See Potera paragraph 76.)
Regarding Claim 13:
The above stated combination of Yamaoka and Potera discloses the gate insulating film disposed in the at least one of the trenches has a larger thickness at both the opposite ends having larger width than at the intermediate portions of the longitudinal walls (Yamaoka discloses insulating an end of the middle trench, which has a width larger than at the intermediate portions of the longitudinal side walls with the trench oxide having a larger thickness than the gate oxide at the intermediate portions, See fig. 16, ref no. 16, and Potera discloses electrically insulating both ends of a plurality of mesa stripes, See fig. 11, ref. nos. 12, 12E, 320, paragraph 52-53 and 76).
Regarding Claim 14:
The above stated combination of Yamaoka and Potera discloses the gate insulating film disposed in the at least one of the trenches has a larger thickness at both the opposite ends having larger width than at the intermediate portions of the longitudinal walls (Yamaoka discloses insulating an end of the middle trench, which has a width larger than at the intermediate portions of the longitudinal side walls with the trench oxide having a larger thickness than the gate oxide at the intermediate portions, See fig. 16, ref no. 16, and Potera discloses electrically insulating both ends of a plurality of mesa stripes, See fig. 11, ref. nos. 12, 12E, 320, paragraph 52-53 and 76).
Regarding Claim 15:
Yamaoka discloses a semiconductor device comprising:
a semiconductor layer (N+ type semiconductor layer and N- type semiconductor layer, See figs. 2a and 16, ref. nos. 11, 12, and paragraphs 12-13) formed with a plurality of trenches (trenches having a perimeter around the gate oxide film and the trench oxide film, See fig. 16, ref. nos. 13B, 16, paragraphs 12-13 and 32) in a surface layer portion (the trenches having a perimeter around the gate oxide film and the trench oxide film are formed in the N- type semiconductor layer, See figs. 3A, 8A, paragraphs 17-18 and 21-23); and
a plurality of trench gates (gate electrodes, See fig. 16, ref. no. 18 and paragraph 13) correspondingly provided in the plurality of trenches of the semiconductor layer, wherein
each of the plurality of trenches extends at least in a first direction (the trenches having a perimeter around the gate oxide film and the trench oxide film are shown in figure 16 extending in the horizontal direction, See fig. 16) in a plan view of the semiconductor layer,
the plurality of trenches are arranged apart from each other in a second direction (the trenches having a perimeter around the gate oxide film and the trench oxide film are shown in figure 16 arranged apart from each other in a vertical direction, See fig. 16) orthogonal to the first direction in the plan view of the semiconductor layer,
each of the plurality of trenches has a pair of end side walls (left sidewall and right sidewall, See fig. 16, ref. nos. 13B and 16) at ends in the first direction and a pair of longitudinal side walls (top sidewall and bottom sidewall, See fig. 16, ref. no. 13B and 16) extending between the pair of end side walls,
the plurality of trenches include a pair of end trenches located at opposite ends in the second direction (top trench and bottom trench, See fig. 16) and an inner trench (middle trench, See fig. 16) located between the pair of end trenches in the second direction,
and a single gate insulating film (the gate oxide film and the trench oxide film, See fig. 16, ref. nos. 13B and 16. The examiner notes that the gate oxide film and the trench oxide film form a single film disposed in the inner trench because the gate oxide film and the trench oxide film do not overlap such that they form two films covering an end side wall or a longitudinal side wall of the inner trench.) disposed in the inner trench and covering the pair of end side walls (the gate oxide film covers the left side wall and the trench oxide covers the right side wall, See fig. 16, ref. nos. 13B and 16) and the pair of longitudinal walls (the gate oxide film and the trench oxide film together cover the longitudinal side walls, See fig. 16, ref. nos. 13B and 16), wherein the single gate insulating film in the inner trench has a larger thickness on the at least one of the end side walls than on the at least one of the intermediate portions of the longitudinal side walls (the trench oxide film on the right sidewall has a thickness greater than the gate oxide film in the center portion of the top sidewall, See fig. 16, ref. no. 13B, 16, and paragraph 13).
Yamaoka does not disclose at least one of the end side walls of the inner trench has a surface roughness larger than a surface roughness of at least one of intermediate portions of the longitudinal side walls of the inner trench, the intermediate portions being at an intermediate position of the inner trench in the first direction.
Potera discloses at least one of the end side walls of the inner trench (end surfaces of middle mesa stripe, See figs. 2A-2B, ref. no. 12 and paragraph 53) has a surface roughness larger than a surface roughness of at least one of intermediate portions of the longitudinal side walls of the inner trench, the intermediate portions being at an intermediate position of the inner trench in the first direction (the middle mesa stripe has end surfaces that are rougher than longitudinal sidewall surfaces, See figs. 2A-2B, ref. no. 12 and paragraph 53. The examiner also notes that the middle mesa strip is visually shown in figure 2B having an end surface rougher than a longitudinal sidewall surface with more lines indicating a rougher surface on the end surface. The examiner additionally notes Potera disclose a plurality of mesa stripes that includes the middle mesa stripe are formed using a plasma etch. See paragraph 53.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Yamaoka to include the trenches having a perimeter around the gate oxide film and the trench oxide film formed by a plasma etch such as that taught by Potera so that the top and bottom sidewalls of interior trenches have less under cutting because the top and bottom sidewalls are etched with a more anisotropic etch. (See Potera paragraph 53.)
Claims 1, 6, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Shimada et al. (US 2010/0102382) in view Potera et al. (US 2024/0145537).
Regarding Claim 1:
Shimada discloses a semiconductor device comprising:
a semiconductor layer (N+ type semiconductor layer and N- type semiconductor layer, See figs. 1-3B, ref. nos. 11, 12, and paragraphs 27-28) formed with a plurality of trenches (trenches, See fig. 1, ref. no. 14, figs. 3A-3B, ref. no. 14, and paragraph 32) in a surface layer portion (the trenches are formed in the N- type semiconductor layer, See figs. 3A-3B, ref. no. 14 and paragraph 32); and
a plurality of trench gates (gate electrodes, See fig. 1, ref. no. 16, fig. 9, ref. no. 16, paragraph 28 and 41) correspondingly provided in the plurality of trenches of the semiconductor layer, wherein
each of the plurality of trenches extends at least in a first direction (the trenches are shown in figure 1 extending in the vertical direction, See fig. 1) in a plan view of the semiconductor layer,
the plurality of trenches are arranged apart from each other in a second direction (the trenches are shown in figure 1 arranged apart from each other in a horizontal direction, See fig. 1) orthogonal to the first direction in the plan view of the semiconductor layer,
each of the plurality of trenches has a pair of end side walls (short sides, See fig. 1, ref. no. 14 and paragraph 28) at ends in the first direction and a pair of longitudinal side walls (long sides, See fig. 1, ref. no. 14 and paragraph 28) extending between the pair of end side walls,
the plurality of trenches include a pair of end trenches located at opposite ends in the second direction (left most trench and right most trench, See fig. 1) and an inner trench (the trench in the middle of the five trenches shown, See fig. 1) located between the pair of end trenches in the second direction,
and a gate insulating film (thicker silicon oxide film and thin silicon oxide film, See fig. 7A-7B, ref. nos. 15A, 15B, and paragraphs 37-38) disposed in the inner trench has a larger thickness on the at least one of the end side walls than on the at least one of the intermediate portions of the longitudinal side walls (the thicker silicon oxide film is on the short sides and the thin silicon oxide film is on the long sides, See fig. 5A-7B and paragraphs 35-39).
Shimada does not disclose at least one of the end side walls of the inner trench has a surface roughness larger than a surface roughness of at least one of intermediate portions of the longitudinal side walls of the inner trench, the intermediate portions being at an intermediate position of the inner trench in the first direction.
Potera discloses at least one of the end side walls of the inner trench (end surfaces of middle mesa stripe, See figs. 2A-2B, ref. no. 12 and paragraph 53) has a surface roughness larger than a surface roughness of at least one of intermediate portions of the longitudinal side walls of the inner trench, the intermediate portions being at an intermediate position of the inner trench in the first direction (the middle mesa stripe has end surfaces that are rougher than longitudinal sidewall surfaces, See figs. 2A-2B, ref. no. 12 and paragraph 53. The examiner also notes that the middle mesa strip is visually shown in figure 2B having an end surface rougher than a longitudinal sidewall surface with more lines indicating a rougher surface on the end surface. The examiner additionally notes Potera disclose a plurality of mesa stripes that includes the middle mesa stripe are formed using a plasma etch. See paragraph 53.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Shimada to include the trenches formed by a plasma etch such as that taught by Potera so that the long sides of interior trenches have less under cutting because the long sides are etched with a more anisotropic etch. (See Potera paragraph 53.)
Regarding Claim 6:
Shimada a manufacturing method of a semiconductor device, the method comprising:
forming a plurality of trenches (forming trenches in an N-type semiconductor layer, See figs. 3A-3B, ref. nos. 12, 14, and paragraph 32) in an upper layer portion (N- type semiconductor layer, See figs. 1-3B, ref. no. 11, paragraphs 28 and 32) of a semiconductor layer (N+ type semiconductor layer and N- type semiconductor layer, See figs. figs. 1-3B, ref. no. 11 and paragraphs 28); and
forming a plurality of trench gates (forming gate electrodes, See figs. 8A-8B, ref. nos. 16P, fig. 9A-9B, ref. nos. 16, 16P, and paragraphs 40-41) correspondingly in the plurality of trenches of the semiconductor layer, wherein
in the forming of the plurality of trenches,
each of the plurality of trenches is formed to extend at least in a first direction (the trenches are shown in figure 1 extending in the vertical direction, See fig. 1) in a plan view of the semiconductor layer, and to have a pair of end side walls (short sides, See fig. 1, ref. no. 14 and paragraph 28) at opposite ends in the first direction walls and a pair of longitudinal side walls (long sides, See fig. 1, ref. no. 14 and paragraph 28) extending between the end side walls,
the plurality of trenches are formed to be arranged spaced apart from each other in a second direction (the trenches are shown in figure 1 arranged apart from each other in a horizontal direction, See fig. 1) orthogonal to the first direction in the plan view of the semiconductor layer, and to include a pair of end trenches located at opposite ends (left most trench and right most trench, See fig. 1) in the second direction and an inner trench (the trench in the middle of the five trenches shown, See fig. 1) located between the pair of end trenches in the second direction, and
the forming of the plurality of trench gates includes forming a gate insulating film (forming thicker silicon oxide film and thin silicon oxide film, See fig. 5A-5B, ref. no. 15A, fig. 6A, ref. no. 15A, fig. 6B, figs. 7A-7B, ref. nos. 15A,15B and paragraphs 35-38) in the inner trench so that a thickness of the gate insulating film on at least one of the end side walls of the inner trench is larger than a thickness of the gate insulating film on at least one of intermediate portions of the longitudinal side walls of the inner trench, the intermediate portions being at an intermediate position of the inner trench in the first direction walls (the thicker silicon oxide film is on the short sides and the thin silicon oxide film is on the long sides, See fig. 5A-7B and paragraphs 35-39).
Shimada does not disclose a state where the at least one of the end side walls of the inner trench has a surface roughness larger than a surface roughness of the at least one of the intermediate portions of the longitudinal side walls of the inner trench.
Potera discloses a state (a state of the plurality of mesa stripes after plasma etching, See figs. 2A-2B, ref. no. 12 and paragraph 53) where the at least one of the end side walls of the inner trench (end surfaces of middle mesa stripe, See figs. 2A-2B, ref. no. 12 and paragraph 53) has a surface roughness larger than a surface roughness of the at least one of the intermediate portions of the longitudinal side walls of the inner trench (the middle mesa stripe has end surfaces that are rougher than longitudinal sidewall surfaces, See figs. 2A-2B, ref. no. 12 and paragraph 53. The examiner also notes that the middle mesa strip is visually shown in figure 2B having an end surface rougher than a longitudinal sidewall surface with more lines indicating a rougher surface on the end surface.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing a semiconductor device of Shimada to include plasma etching the trenches such as that taught by Potera so that the long sides of interior trenches have less under cutting because the long sides are etched with a more anisotropic etch. (See Potera paragraph 53.)
Regarding Claim 15:
Shimada discloses a semiconductor device comprising:
a semiconductor layer (N+ type semiconductor layer and N- type semiconductor layer, See figs. 1-3B, ref. nos. 11, 12, and paragraphs 27-28) formed with a plurality of trenches (trenches, See fig. 1, ref. no. 14, figs. 3A-3B, ref. no. 14, and paragraph 32) in a surface layer portion (the trenches are formed in the N- type semiconductor layer, See figs. 3A-3B, ref. no. 14 and paragraph 32); and
a plurality of trench gates (gate electrodes, See fig. 1, ref. no. 16, fig. 9, ref. no. 16, paragraph 28 and 41) correspondingly provided in the plurality of trenches of the semiconductor layer, wherein
each of the plurality of trenches extends at least in a first direction (the trenches are shown in figure 1 extending in the vertical direction, See fig. 1) in a plan view of the semiconductor layer,
the plurality of trenches are arranged apart from each other in a second direction (the trenches are shown in figure 1 arranged apart from each other in a horizontal direction, See fig. 1) orthogonal to the first direction in the plan view of the semiconductor layer,
each of the plurality of trenches has a pair of end side walls (short sides, See fig. 1, ref. no. 14 and paragraph 28) at ends in the first direction and a pair of longitudinal side walls (long sides, See fig. 1, ref. no. 14 and paragraph 28) extending between the pair of end side walls,
the plurality of trenches include a pair of end trenches located at opposite ends in the second direction (left most trench and right most trench, See fig. 1) and an inner trench (the trench in the middle of the five trenches shown, See fig. 1) located between the pair of end trenches in the second direction,
and a single gate insulating film (thicker silicon oxide film and thin silicon oxide film, See fig. 7A-7B, ref. nos. 15A, 15B, and paragraphs 37-38. The examiner notes that the thicker silicon oxide film and the thin oxide film form a single film disposed in the inner trench because the thicker oxide film and the thin oxide film do not overlap such that they form two films covering an end side wall or a longitudinal side wall of the inner trench.) disposed in the inner trench and covering the pair of end side walls (the thicker silicon oxide film is on the short sides, See fig. 5A-7B and paragraphs 35-39) and the pair of longitudinal walls (the thin silicon oxide film is on the long sides, See fig. 5A-7B and paragraphs 35-39), wherein the single gate insulating film in the inner trench has a larger thickness on the at least one of the end side walls than on the at least one of the intermediate portions of the longitudinal side walls (the thicker silicon oxide film is on the short sides and the thin silicon oxide film is on the long sides, See fig. 5A-7B and paragraphs 35-39).
Shimada does not disclose at least one of the end side walls of the inner trench has a surface roughness larger than a surface roughness of at least one of intermediate portions of the longitudinal side walls of the inner trench, the intermediate portions being at an intermediate position of the inner trench in the first direction.
Potera discloses at least one of the end side walls of the inner trench (end surfaces of middle mesa stripe, See figs. 2A-2B, ref. no. 12 and paragraph 53) has a surface roughness larger than a surface roughness of at least one of intermediate portions of the longitudinal side walls of the inner trench, the intermediate portions being at an intermediate position of the inner trench in the first direction (the middle mesa stripe has end surfaces that are rougher than longitudinal sidewall surfaces, See figs. 2A-2B, ref. no. 12 and paragraph 53. The examiner also notes that the middle mesa strip is visually shown in figure 2B having an end surface rougher than a longitudinal sidewall surface with more lines indicating a rougher surface on the end surface. The examiner additionally notes Potera disclose a plurality of mesa stripes that includes the middle mesa stripe are formed using a plasma etch. See paragraph 53.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Shimada to include the trenches formed by a plasma etch such as that taught by Potera so that the long sides of interior trenches have less under cutting because the long sides are etched with a more anisotropic etch. (See Potera paragraph 53.)
Claims 2, 5, 7, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yamaoka et al. (JP 2009088186 A) in view Potera et al. (US 2024/0145537) further in view Kyogoku et al. (US 2018/0158938).
Regarding Claim 2:
The above stated combination of Yamaoka and Potera discloses the above stated semiconductor device.
The above stated combination of Yamaoka and Potera does not disclose wherein the at least one of the end side walls of the inner trench has a smaller inclination angle than that of the at least one of the intermediate portions of the longitudinal side walls, the inclination angle being defined relative to the surface of the semiconductor layer.
Kyogoku discloses wherein the at least one of the end side walls of the inner trench has a smaller inclination angle than that of the at least one of the intermediate portions of the longitudinal side walls, the inclination angle being defined relative to the surface of the semiconductor layer (a fourth partial region of a semiconductor layer located at the end of a trench for an electrode has an inclination angle less than an inclination angle of a side region of the electrode that is on the fourth partial region of the semiconductor layer and the side region of the electrode has an inclination angle which is less than 80 degrees, See fig. 1A, ref. nos. 10s, 21, fig. 2, ref. nos. θ, 10d, 10s, 21, 21bx, paragraphs 29-30 and 61-62. The examiner also notes the Kyogoku discloses the longitudinal sidewall of the trenches for the electrode are generally 90 degrees, See figs. 1A, 1B, ref. no. 21 and paragraph 27).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Yamaoka and Potera to include wherein the at least one of the end side walls of the inner trench has a smaller inclination angle than that of the at least one of the intermediate portions of the longitudinal side walls, the inclination angle being defined relative to the surface of the semiconductor layer as taught by Kyogoku in order to improve insulative characteristics at the end of the trench by reducing the electric field strength at the vicinity of the end of the trench. (See Kyogoku paragraph 64.)
Regarding Claim 5:
The above stated combination of Yamaoka and Potera discloses the above stated semiconductor device.
The above stated combination of Yamaoka and Potera does not disclose the semiconductor layer is made of silicon carbide.
Kyogoku discloses the semiconductor layer is made of silicon carbide (the semiconductor layer includes silicon carbide, See fig. 1A-1D ref. no. 10s and paragraph 47).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Yamaoka and Potera to include the semiconductor layer is made of silicon carbide as that taught by Kyogoku because field effect transistors manufactured using silicon carbide are capable of high blocking voltages and high current carrying capacity. (See Potera paragraph 2).
Regarding Claim 7:
The above stated combination of Yamaoka and Potera discloses the above stated method of manufacturing a semiconductor device.
The above stated combination of Yamaoka and Potera does not disclose wherein the forming of the plurality of trenches includes forming the inner trench so that the at least one of the end side walls has an inclination angle smaller than that of the at least one of the intermediate portions of the longitudinal side walls, the inclination angle being defined relative to a surface of the semiconductor layer.
Kyogoku discloses wherein the forming of the plurality of trenches includes forming the inner trench so that the at least one of the end side walls has an inclination angle smaller than that of the at least one of the intermediate portions of the longitudinal side walls, the inclination angle being defined relative to a surface of the semiconductor layer (forming a trench with a titled region having an inclination angle less than an inclination angle of longitudinal sidewalls of the trench, See figs. 7A-7E, ref. nos. T1, Tb1 and paragraphs 78-83.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing a semiconductor device of Yamaoka and Potera to include wherein the forming of the plurality of trenches includes forming the inner trench so that the at least one of the end side walls has an inclination angle smaller than that of the at least one of the intermediate portions of the longitudinal side walls, the inclination angle being defined relative to a surface of the semiconductor layer as taught by Kyogoku in order to improve insulative characteristics at the end of the trench by reducing the electric field strength at the vicinity of the end of the trench. (See Kyogoku paragraph 64.)
Regarding Claim 10:
The above stated combination of Yamaoka and Potera discloses the above stated method of manufacturing a semiconductor device.
The above stated combination of Yamaoka and Potera does not disclose the semiconductor layer is made of silicon carbide.
Kyogoku discloses the semiconductor layer is made of silicon carbide (the semiconductor layer includes silicon carbide, See fig. 1A-1D ref. no. 10s and paragraph 47).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing a semiconductor device of Yamaoka and Potera to include the semiconductor layer is made of silicon carbide as that taught by Kyogoku because field effect transistors manufactured using silicon carbide are capable of high blocking voltages and high current carrying capacity. (See Potera paragraph 2).
Claims 2, 5, 7, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Shimada et al. (US 2010/0102382) in view Potera et al. (US 2024/0145537) further in view Kyogoku et al. (US 2018/0158938).
Regarding Claim 2:
The above stated combination of Shimada and Potera discloses the above stated semiconductor device.
The above stated combination of Shimada and Potera does not disclose wherein the at least one of the end side walls of the inner trench has a smaller inclination angle than that of the at least one of the intermediate portions of the longitudinal side walls, the inclination angle being defined relative to the surface of the semiconductor layer.
Kyogoku discloses wherein the at least one of the end side walls of the inner trench has a smaller inclination angle than that of the at least one of the intermediate portions of the longitudinal side walls, the inclination angle being defined relative to the surface of the semiconductor layer (a fourth partial region of a semiconductor layer located at the end of a trench for an electrode has an inclination angle less than an inclination angle of a side region of the electrode that is on the fourth partial region of the semiconductor layer and the side region of the electrode has an inclination angle which is less than 80 degrees, See fig. 1A, ref. nos. 10s, 21, fig. 2, ref. nos. θ, 10d, 10s, 21, 21bx, paragraphs 29-30 and 61-62. The examiner also notes the Kyogoku discloses the longitudinal sidewall of the trenches for the electrode are generally 90 degrees, See figs. 1A, 1B, ref. no. 21 and paragraph 27).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Shimada and Potera to include wherein the at least one of the end side walls of the inner trench has a smaller inclination angle than that of the at least one of the intermediate portions of the longitudinal side walls, the inclination angle being defined relative to the surface of the semiconductor layer as taught by Kyogoku in order to improve insulative characteristics at the end of the trench by reducing the electric field strength at the vicinity of the end of the trench. (See Kyogoku paragraph 64.)
Regarding Claim 5:
The above stated combination of Shimada and Potera discloses the above stated semiconductor device.
The above stated combination of Shimada and Potera does not disclose the semiconductor layer is made of silicon carbide.
Kyogoku discloses the semiconductor layer is made of silicon carbide (the semiconductor layer includes silicon carbide, See fig. 1A-1D ref. no. 10s and paragraph 47).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Shimada and Potera to include the semiconductor layer is made of silicon carbide as that taught by Kyogoku because field effect transistors manufactured using silicon carbide are capable of high blocking voltages and high current carrying capacity. (See Potera paragraph 2).
Regarding Claim 7:
The above stated combination of Shimada and Potera discloses the above stated method of manufacturing a semiconductor device.
The above stated combination of Shimada and Potera does not disclose wherein the forming of the plurality of trenches includes forming the inner trench so that the at least one of the end side walls has an inclination angle smaller than that of the at least one of the intermediate portions of the longitudinal side walls, the inclination angle being defined relative to a surface of the semiconductor layer.
Kyogoku discloses wherein the forming of the plurality of trenches includes forming the inner trench so that the at least one of the end side walls has an inclination angle smaller than that of the at least one of the intermediate portions of the longitudinal side walls, the inclination angle being defined relative to a surface of the semiconductor layer (forming a trench with a titled region having an inclination angle less than an inclination angle of longitudinal sidewalls of the trench, See figs. 7A-7E, ref. nos. T1, Tb1 and paragraphs 78-83.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing a semiconductor device of Shimada and Potera to include wherein the forming of the plurality of trenches includes forming the inner trench so that the at least one of the end side walls has an inclination angle smaller than that of the at least one of the intermediate portions of the longitudinal side walls, the inclination angle being defined relative to a surface of the semiconductor layer as taught by Kyogoku in order to improve insulative characteristics at the end of the trench by reducing the electric field strength at the vicinity of the end of the trench. (See Kyogoku paragraph 64.)
Regarding Claim 10:
The above stated combination of Shimada and Potera discloses the above stated method of manufacturing a semiconductor device.
The above stated combination of Shimada and Potera does not disclose the semiconductor layer is made of silicon carbide.
Kyogoku discloses the semiconductor layer is made of silicon carbide (the semiconductor layer includes silicon carbide, See fig. 1A-1D ref. no. 10s and paragraph 47).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing a semiconductor device of Shimada and Potera to include the semiconductor layer is made of silicon carbide as that taught by Kyogoku because field effect transistors manufactured using silicon carbide are capable of high blocking voltages and high current carrying capacity. (See Potera paragraph 2).
Claims 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yamaoka et al. (JP 2009088186 A) in view Potera et al. (US 2024/0145537) further in view of Nakamura (JP 2012231187 A). The examiner notes that the citations to paragraphs in Yamaoka refer to paragraphs in the attached English language translation of Yamaoka and the citations to paragraphs in Nakamura refer to paragraphs in the attached English language translation of Nakamura.
Regarding Claim 4:
The above stated combination of Yamaoka and Potera discloses the above stated semiconductor device. The above stated combination of Yamaoka and Potera further discloses wherein at least one of the end trenches (top trench, See Yamaoka fig. 16) has an outer longitudinal side wall (the top sidewall of the top trench, See Yamaoka fig. 16) as one of the pair of longitudinal side walls on an outer side in the second direction, the outer longitudinal side wall has a surface roughness larger than the surface roughness of the at least one of the intermediate portions of the longitudinal side walls of the inner trench (outer sidewalls of the outermost mesa stripes have a rougher surface than the sidewalls of the inner mesa strips, See figs. 2A-2B, ref. nos. 12, 12S and paragraph 53. The examiner also notes that the outer mesa stripe having an outer sidewall with a surface rougher than a sidewall of an inner mesa stripe is visually shown in figure 2B with more lines indicating a rougher surface on the outer sidewall of the outer mesa stripe.).
The above stated combination of Yamaoka and Potera does not disclose the gate insulating film disposed in the at least one of the end trenches and covering the outer longitudinal side wall has a thickness larger than that of the gate insulating film on the at least one of the intermediate portions of the longitudinal side walls of the inner trench.
Nakamura disclose depositing a CVD oxide over a thermal oxide on a sidewall of a trench with a highly uneven surface (See fig. 3a, 3c, ref. nos. 9, 10, and paragraph 12 and 15)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Yamaoka and Potera to include depositing a CVD oxide over the gate oxide film of the top trench as that taught by Nakamura to improve the gate insulating film characteristics such as leakage characteristics, breakdown voltage distribution, and reliability. (See Nakamura paragraph 76.) (The examiner notes that top trench has a thicker gate insulating film than the middle trench because both the gate oxide film and the CVD oxide film are deposited in the top trench.)
Regarding Claim 9:
The above stated combination of Yamaoka and Potera discloses the above stated method of manufacturing a semiconductor device. The above stated combination of Yamaoka and Potera further discloses wherein the forming of the plurality of trench gates includes forming a gate insulating film on an outer longitudinal side wall of the at least one of the end trenches (forming the gate oxide film on the top sidewall of the top trench, See Yamaoka figs. 9A-9B, ref. no. 13B, fig. 16, and paragraph 23), the outer longitudinal side wall being one of the pair of longitudinal side walls of the at least one of the end trenches and on an outer side in the second direction, in a state where the outer longitudinal side wall of the at least one of the end trenches has a surface roughness larger than that of the at least one of the intermediate portions of the longitudinal side walls of the inner trench (The gate oxide film is formed on the top sidewall of the top trench after etching the N- type semiconductor layer to form the top trench, See Yamaoka figs. 8A-9B and paragraphs 21-23.
The above stated combination of Yamaoka and Potera does not disclose forming a gate insulating film in at least one of the end trenches so that a thickness of the gate insulating film on an outer longitudinal side wall of the at least one of the end trenches is larger than the thickness of the gate insulating film on the at least one of the intermediate portions of the longitudinal side walls of the inner trench.
Nakamura disclose depositing a CVD oxide over a thermal oxide on a sidewall of a trench with a highly uneven surface (See fig. 3a, 3c, ref. nos. 9, 10, and paragraph 12 and 15)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing a semiconductor device of Yamaoka and Potera to include depositing a CVD oxide over the gate oxide film of the top trench as that taught by Nakamura to improve the gate insulating film characteristics such as leakage characteristics, breakdown voltage distribution, and reliability. (See Nakamura paragraph 76.) (The examiner notes that top trench has a thicker gate insulating film than the middle trench because both the gate oxide film and the CVD oxide film are deposited in the top trench.)
Claims 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yamaoka et al. (JP 2009088186 A) in view Potera et al. (US 2024/0145537) further in view Takeuchi et al. (US 2019/00334030).
Regarding Claim 5:
The above stated combination of Yamaoka and Potera discloses the above stated semiconductor device.
The above stated combination of Yamaoka and Potera does not disclose the semiconductor layer is made of silicon carbide.
Takeuchi discloses the semiconductor layer is made of silicon carbide (SiC semiconductor device formed using an N+ type substrate made of SiC and N- type epitaxial film made of SiC, See fig. 2 ref. nos. 1, 2, and paragraph 42).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Yamaoka and Potera to include the semiconductor layer is made of silicon carbide as that taught by Takeuchi because field effect transistors manufactured using silicon carbide are capable of high blocking voltages and high current carrying capacity. (See Potera paragraph 2).
Regarding Claim 10:
The above stated combination of Yamaoka and Potera discloses the above stated method of manufacturing a semiconductor device.
The above stated combination of Yamaoka and Potera does not disclose the semiconductor layer is made of silicon carbide.
Takeuchi discloses the semiconductor layer is made of silicon carbide (SiC semiconductor device formed using an N+ type substrate made of SiC and N- type epitaxial film made of SiC, See fig. 2 ref. nos. 1, 2, and paragraph 42).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing a semiconductor device of Yamaoka and Potera to include the semiconductor layer is made of silicon carbide as that taught by Takeuchi because field effect transistors manufactured using silicon carbide are capable of high blocking voltages and high current carrying capacity. (See Potera paragraph 2).
Claims 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Shimada et al. (US 2010/01022382) in view Potera et al. (US 2024/0145537) further in view Takeuchi et al. (US 2019/00334030).
Regarding Claim 5:
The above stated combination of Shimada and Potera discloses the above stated semiconductor device.
The above stated combination of Shimada and Potera does not disclose the semiconductor layer is made of silicon carbide.
Takeuchi discloses the semiconductor layer is made of silicon carbide (SiC semiconductor device formed using an N+ type substrate made of SiC and N- type epitaxial film made of SiC, See fig. 2 ref. nos. 1, 2, and paragraph 42).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Shimada and Potera to include the semiconductor layer is made of silicon carbide as that taught by Takeuchi because field effect transistors manufactured using silicon carbide are capable of high blocking voltages and high current carrying capacity. (See Potera paragraph 2).
Regarding Claim 10:
The above stated combination of Shimada and Potera discloses the above stated method of manufacturing a semiconductor device.
The above stated combination of Shimada and Potera does not disclose the semiconductor layer is made of silicon carbide.
Takeuchi discloses the semiconductor layer is made of silicon carbide (SiC semiconductor device formed using an N+ type substrate made of SiC and N- type epitaxial film made of SiC, See fig. 2 ref. nos. 1, 2, and paragraph 42).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing a semiconductor device of Shimada and Potera to include the semiconductor layer is made of silicon carbide as that taught by Takeuchi because field effect transistors manufactured using silicon carbide are capable of high blocking voltages and high current carrying capacity. (See Potera paragraph 2).
Allowable Subject Matter
Claims 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to dependent claim 11, the disclosures and illustrations of Yamaoka and Potera as discussed above and the disclosures and illustrations of Shimada and Potera as discussed above fail to teach and/or suggest after forming the plurality of trenches and before forming of the plurality of trench gates, performing a flattening process that reduces surface roughness of the plurality of trenches, wherein the flattening process is terminated such that a surface roughness of the end side walls of the inner trenches, end side walls of the end trenches, and longitudinal side walls of the end trenches remain larger than a surface roughness of the intermediate portions of the longitudinal side walls of the inner trenches. Further, the prior art also fails to provide other relevant disclosures which are properly combinable with Yamaoka and Potera to teach and/or suggest the limitations of claim 11. Additionally, the prior art also fails to provide other relevant disclosures which are properly combinable with Shimada and Potera to teach and/or suggest the limitations of claim 11. Therefore, claim 11 includes allowable subject matter. Claim 12 depends from claim 11, and thus, includes the subject matter of claim 11. Therefore, claim 12 includes allowable subject matter.
Response to Arguments
Applicant's arguments filed May 11, 2026 have been fully considered but they are not persuasive.
With respect to claims 1 and 6, the applicant’s argument that Yamaoka does not disclose a gate insulating film disposed in the inner trench has a larger thickness on the at least one of the end side walls than on the at least one of the intermediate portions of the longitudinal side walls because Yamaoka discloses the trench oxide film is for preventing gate leakage current and reducing gate capacitance is not persuasive. The examiner first notes that “[A]pparatus claims cover what a device is, not what a device does.” See Hewlett-Packard Co. Baush & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ 1525, 1528 (Fed. Cir. 1990) (emphasis in original). The examiner next notes that applicant’s argument is directed toward the intended use of the trench oxide film of preventing gate leakage current and reducing gate capacitance rather than structural differences between the gate insulating film and the trench oxide film with gate oxide film. Therefore, the applicant’s argument that Yamaoka does not disclose a gate insulating film disposed in the inner trench has a larger thickness on the at least one of the end side walls than on the at least one of the intermediate portions of the longitudinal side walls is not persuasive because the trench oxide film having an intended use that differs from the claimed gate insulating film does not structurally distinguish the claimed gate insulating film from the trench oxide film and the gate oxide film of Yamaoka.
With respect to claim 15, the examiner respectfully disagrees with the applicant’s argument that Yamaoka does not disclose a single gate insulating film of varying thickness covering the pair of longitudinal side walls of the inner trenches. The examiner respectfully points out that the gate oxide film and the trench oxide film form a single film disposed in the inner trench and covering the pair of end side walls and the pair of longitudinal side walls of the inner trench because the gate oxide film and the trench oxide film do not overlap such that they form two films covering the pair of end side walls and the pair of longitudinal side walls of the inner trench. The examiner further notes the limitation a single gate insulating film does not also require the single gate insulating film to be a continuous film.
With respect to claims 1 and 6, the applicant’s argument that the combination of Shimada and Potera does not clearly show that the combination would have the claimed roughness differential while retaining the thicker silicon oxide and the thin silicon oxide arrangement is not persuasive. The examiner first notes that the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). The examiner next notes that Shimada would have reasonably suggested to one having ordinary skill in the art to retain the thicker silicon oxide and the thin silicon oxide arrangement over surfaces formed using the plasma etch taught by Potera because Shimada discloses the thicker silicon oxide and the thin silicon oxide arrangement are formed over surfaces dry etched using sulfur hexafluoride gas which is commonly used in plasma etching. See Shimada figure 3 and paragraph 32. See US 2009/0141229 to Nako, paragraph 31, which discloses sulfur hexafluoride is in common use as plasma etching gas for etching silicon-based compounds. Therefore, the applicant’s argument that the combination of Shimada and Potera does not clearly show that the combination would have the claimed roughness differential while retaining the thicker silicon oxide and the thin silicon oxide arrangement is not persuasive because the combination of Shimada and Potera discloses this feature.
With respect to claim 15, the examiner respectfully disagrees with the applicant’s argument that Shimada does not disclose a single gate insulating film of varying thickness covering the pair of longitudinal side walls of the inner trenches. The examiner respectfully points out that the thicker silicon oxide film and the thin silicon oxide film form a single film disposed in the inner trench and covering the pair of end side walls and the pair of longitudinal side walls of the inner trench because the thicker silicon oxide film and the thin silicon oxide film do not overlap such that they form two films covering the pair of end side walls and the pair of longitudinal side walls of the inner trench. The examiner further notes the limitation a single gate insulating film does not also require the single gate insulating film to be a continuous film.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899
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