Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The objection to the drawings for failing to include the reference number 210 is withdrawn in view of the amendment to the specification in the response filed on March 18, 2026.
Specification
The corrections to the specification in the response filed on March 18, 2026 are accepted by the examiner.
Claim Objections
The claim objections to claims 2, 6, 10, 11, and 13 are withdrawn in view of applicant’s amendments and remarks in the response filed on March 18, 2026.
Claim Rejections - 35 USC § 112
The rejection of claims 10-11, 17, and 19-20 under 35 U.S.C. 112(b) or 35 U.S.C. (pre-AIA ), second paragraph, is withdrawn in view of applicant’s amendments and remarks in the response filed on March 18, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-7, 12-13, 16-17, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Hao et al. (US 2013/0099311) in view of Lee et al. (US 8,803,251).
Regarding Claim 1:
Hao discloses a semiconductor device comprising:
a conductive region (region near vertical n-type MOSFET, See fig. 3E, ref. no. 380 and paragraph 32) extending in a first direction (direction across the cross sectional view shown in figure 3E, See fig. 3E) and a second direction (direction into the cross sectional view shown in figure 3E, See fig. 3E. The examiner notes the vertical n-type MOSFET are formed in three dimensions.) intersecting the first direction and stacked in a third direction (vertical direction in the cross sectional view shown in figure 3E, See fig. 3E) intersecting the first direction and the second direction; and
a termination region (region near the conductive material that defines a gate runner, See fig. 3E, ref. no. 370 and paragraphs 70-73) at an end of the conductive region in the first direction, wherein the termination region comprises:
an n+ type substrate (n-type substrate, See figs. 3A-3E, ref. nos. 320 and paragraphs 31-32);
an n- type layer (n-type epitaxial layer, See figs. 3A-3E, ref. no. 390, paragraphs 16, 31-32. The examiner notes that a vertical N-type MOSFET has an n-type epitaxial layer.) disposed on an upper surface of the n+ type substrate and having a plurality of first trenches opening upward in the third direction (gate runner trenches, See fig. 3B-3D, ref. no. 344, paragraphs 45 and 48-49); and
a lower gate runner (the conductive material that defines a gate runner, See fig. 3E, ref. no. 370 and paragraph 70-72. The examiner notes that the conductive material that defines a gate runner has a top surface lower than a neighboring structure formed from the conductive material.) covering the plurality of first trenches and disposed on an upper surface of the n-type layer (the conductive material that defines a gate runner covers the gate runner trenches and extends beyond the gate runner trenches, See fig. 3E, ref. nos. 344 and 370), wherein the lower gate runner comprises:
an upper portion (the top of the conductive material that defines a gate runner covers the gate runner trenches and extends beyond the gate runner trenches, See figs. 3B-3D, ref. no. 344 and fig. 3E, ref. no. 370) covering the plurality of first trenches and disposed on an upper surface of the plurality of first trenches; and extended portions disposed inside each of the first trenches (portion of the conductive material that defines a gate runner in gate runner trenches, See fig. 3E, ref. nos. 340 and 370).
Hao does not disclose wherein each of the first trenches includes an empty space inside each respective extended portion of the extended portions.
Lee discloses non-conformally depositing a material in a sufficiently narrow and deep trench results in the formation of a triangular shaped void in the material deposited in the trench (See fig. 4E and col. 4 lines 28-32).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Hao to include the gate runner in a sufficiently narrow and deep trench that will result in the formation of a triangular shaped void in the portion of the material in the trench when formed by non-conformally depositing the material in the trench as taught by Lee in order to support miniaturization of the gate runner through the use of known non-conformal deposition techniques to fill narrow and deep trenches.
Regarding Claim 2:
Hao discloses wherein a first-direction spacing between the first trenches is less than or equal to a first-direction width of each of the first trenches (The examiner first notes Hao discloses the mesa between the gate runner trenches can have a width of approximately between 0.01µm and 50 µm and the gate runner trenches can have a width of approximately between 0.01µm and 50 µm. See fig. 3B, ref. nos. O, N, 341, 344 and paragraphs 48-49. The examiner next notes that all three alternatives for the spacing of the mesa and the gate trenches; the width of the mesa being greater than the width of the gate trenches, the width of the mesa being the same as the width of the gate trenches, and the width of the mesa being less than the width of the gate trenches are disclosed through disclosure of the widths for the mesa and the gate trenches.)
Regarding Claim 4:
Hao discloses wherein each of the extended portions comprises: a trench sidewall portion disposed on a sidewall of the first trenches (portion of the conductive material that defines a gate runner in gate runner trenches has a portion disposed on the sidewalls of the gate runner trenches through intervening polysilicon material, See fig. 3E, ref. nos. 342, 370 and paragraph 57 and 66-67); and a trench bottom portion disposed on a bottom of the first trenches (portion of the conductive material that defines a gate runner in gate runner trenches has a portion disposed on the bottom of the gate runner trenches through intervening polysilicon material, See fig. 3E, ref. nos. 342, 370 and paragraph 57 and 66-67).
Regarding Claim 5:
The examiner now points out that the combination of Hao and Lee discloses the portion of the conductive material that defines the gate runner deposited in a sufficiently narrow and deep trench has a triangular shaped void, as shown in fig. 4E of Lee, in the conductive material shown in fig. 3E of Hao. Therefore, the combination of Hao and Lee discloses the trench sidewall portion has a convex shape toward an inside of the first trenches as it moves upward in the third direction (the conductive material surrounding the top point of the triangular shaped void, See Lee fig. 4E), and the trench bottom portion has a convex shape toward the inside of the first trenches (the conductive material surrounding the bottom points of the triangular shaped void, See Lee fig. 4E).
Regarding Claim 6:
The combination of Hao and Lee discloses wherein the empty space of each of the first trenches is surrounded by the upper portion of the lower gate runner, the trench sidewall portion, and the trench bottom portion (the triangular shaped void is surrounded by the conductive material that defines the gate runner, See Lee fig. 4E).
Regarding Claim 7:
The combination of Hao and Lee discloses the empty space has a shape whose width in the first direction becomes narrower as it moves upward in the third direction (triangular shaped void, See Lee fig. 4E).
Regarding Claim 12:
Hao discloses a semiconductor device comprising:
a conductive region (region near vertical n-type MOSFET, See fig. 3E, ref. no. 380 and paragraph 32) extending in a first direction (direction across the cross sectional view shown in figure 3E, See fig. 3E) and a second direction (direction into the cross sectional view shown in figure 3E, See fig. 3E. The examiner notes the vertical n-type MOSFET are formed in three dimensions.) intersecting the first direction and stacked in a third direction (vertical direction in the cross sectional view shown in figure 3E, See fig. 3E) intersecting the first direction and the second direction; and
a termination region (region near the conductive material that defines a gate runner, See fig. 3E, ref. no. 370 and paragraphs 70-73) at an end of the conductive region in the first direction, wherein the termination region comprises:
an n+ type substrate (n-type substrate, See figs. 3A-3E, ref. nos. 320 and paragraphs 31-32);
an n- type layer (n-type epitaxial layer, See figs. 3A-3E, ref. no. 390, paragraphs 16, 31-32. The examiner notes that a vertical N-type MOSFET has an n-type epitaxial layer.) disposed on an upper surface of the n+ type substrate;
a buffer layer (etched sacrificial gate oxide, See figs. 3B-3E, ref. no. 340 and paragraph 54) disposed on an upper surface of the n-type layer and having a plurality of first trenches opening upward in the third direction (openings etched into the etched sacrificial gate oxide that open upward in the vertical direction, See figs. 3B-3E, ref. no. 340 and paragraph 54); and
a lower gate runner (conductive material that defines a gate runner, See fig. 3E, ref. no. 370 and paragraph 70-72. The examiner notes that the conductive material that defines a gate runner has a top surface lower than a neighboring structure formed from the conductive material.) covering the plurality of first trenches and disposed on an upper surface of the buffer layer (conductive material that defines a gate runner covers the gate runner trenches and extends beyond the gate runner trenches, See fig. 3E, ref. nos. 344 and 370), wherein the lower gate runner comprises:
an upper portion (the top of the conductive material that defines a gate runner covers the gate runner trenches and extends beyond the gate runner trenches, See figs. 3B-3D, ref. no. 344 and fig. 3E, ref. no. 370) covering the plurality of first trenches and disposed on an upper surface of the plurality of first trenches; and extended portions disposed inside each of the first trenches (portion of the conductive material that defines a gate runner in gate runner trenches, See fig. 3E, ref. nos. 340 and 370).
Hao does not disclose wherein each of the first trenches includes an empty space inside each respective extended portion of the extended portions.
Lee discloses non-conformally depositing a material in a sufficiently narrow and deep trench results in the formation of a triangular shaped void in the material deposited in the trench (See fig. 4E and col. 4 lines 28-32).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Hao to include the gate runner in a sufficiently narrow and deep trench that will result in the formation of a triangular shaped void in the portion of the material in the trench when formed by non-conformally depositing the material in the trench as taught by Lee in order to support miniaturization of the gate runner through the use of known non-conformal deposition techniques to fill narrow and deep trenches.
Regarding Claim 13:
Hao discloses wherein a first-direction spacing between the first trenches is less than or equal to a first-direction width of each of the first trenches (The examiner first notes that the dimensions of the pattern etched into the sacrificial gate oxide correspond to the width of the mesa between gate runner trenches and the width of the gate runner trenches. See fig. 3B, ref. nos. O, N, 341, 344 and paragraphs 48-49. The examiner next notes Hao discloses the mesa between the gate runner trenches can have a width of approximately between 0.01µm and 50 µm and the gate runner trenches can have a width of approximately between 0.01µm and 50 µm. The examiner further notes that all three alternatives for the spacing of the mesa and the gate trenches; the width of the mesa being greater than the width of the gate trenches, the width of the mesa being the same as the width of the gate trenches, and the width of the mesa being less than the width of the gate trenches are disclosed through disclosure of the widths for the mesa and the gate trenches.)
Regarding Claim 16:
Hao discloses a method of manufacturing a semiconductor device, the method comprising: forming an n-type layer (n-type epitaxial layer, See figs. 3A-3E, ref. no. 390, paragraphs 16, 31-32. The examiner notes that a vertical N-type MOSFET has an n-type epitaxial layer.) on an upper surface of an n+ type substrate (epitaxially growing the n-type epitaxial layer on an n-type substrate, See figs. 3A-3E, ref. nos. 320, 390 and paragraphs 31-32);
forming a plurality of first trenches (gate-runner trenches, See fig. 3B, ref. no. 344 and paragraph 45) in the n-type layer (forming gate-runner trenches in the n-type epitaxial layer, See fig. 3B, ref. no. 344 and paragraph 45), the plurality of first trenches opening upward toward an upper surface of the n-type layer (the gate-runner trenches open upward toward an upper surface of the n-type epitaxial layer, See fig. 3B, ref. nos. 344, 390);
forming a preliminary gate electrode layer (depositing a conductive material over the gate runner trenches and the top surface of epitaxial layer using a plasma-enhanced CVD process, See fig. 3E, ref. no. 370 and paragraph 70) covering the plurality of first trenches and an upper portion of the n-type layer without filling all of an interior of the plurality of first trenches (the conductive material does not fill all of the interior of the gate runner trenches, See fig. 3E, ref. no. 370, and paragraph 63-65) using a deposition method with a non-conformal step coverage (The examiner notes that a plasma-enhanced CVD process deposits material in a non-conformal manner.); and
etching a portion of the preliminary gate electrode layer that covers the n- type layer to form a lower gate runner (etching the conductive material to form a first portion that has a top surface lower than a neighboring structure formed from the conductive material, See fig. 3E, ref. no. 370 and paragraphs 70-72) that covers the plurality of first trenches and is disposed on the upper surface of the n-type layer (the first portion of the conductive material covers the gate runner trenches and extends beyond the gate runner trenches, See fig. 3E, ref. no. 370) wherein the lower gate runner comprises:
an upper portion (the top of the conductive material that defines a gate runner covers the gate runner trenches and extends beyond the gate runner trenches, See figs. 3B-3D, ref. no. 344 and fig. 3E, ref. no. 370) covering the plurality of first trenches and disposed on an upper surface of the plurality of first trenches; and extended portions disposed inside each of the first trenches (portion of the conductive material that defines a gate runner in gate runner trenches, See fig. 3E, ref. nos. 340 and 370).
Hao does not disclose wherein each of the first trenches includes an empty space inside each respective extended portion of the extended portions.
Lee discloses non-conformally depositing a material in a sufficiently narrow and deep trench results in the formation of a triangular shaped void in the material deposited in the trench (See fig. 4E and col. 4 lines 28-32).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Hao to include the gate runner in a sufficiently narrow and deep trench that will result in the formation of a triangular shaped void in the portion of the material in the trench when formed by non-conformally depositing the material in the trench as taught by Lee in order to support miniaturization of the gate runner through the use of known non-conformal deposition techniques to fill narrow and deep trenches.
Regarding Claim 17:
Hao discloses wherein a first direction thickness of the portion covering the n-type layer of the preliminary gate electrode layer is 0.5 times or more than a second direction width of each of the plurality of first trenches (the thickness of the top of the first portion of the conductive material is at least two times greater than the width of the gate trenches because the first portion of the conductive material electrically couples together the material in the gate-runner trenches, See fig. 3E, ref. no. 370 and paragraph 71. The examiner first notes that figure 3E shows a cross-sectional view of the first portion of the conductive material and the gate trenches. See paragraph 31. The examiner next notes the first portion of the conductive material and the gate trenches have shapes, such as a rectangular shape, that surround active semiconductor devices such as MOSFETs. See fig. 2 ref. no. 22 and paragraph 27. The examiner notes that when a cross-sectional view is taken along a left side or right side of a rectangular shape, such as that shown in figure 2, the dimensions in the cross-sectional view will be in a first direction and when a cross-sectional view is taken along a front side or a back side of a rectangular shape, such as that shown in figure 2, the dimensions in the cross-sectional view will be in a second direction. The examiner further notes the thickness of the top of the first portion of the conductive material and the width of the gate trenches will be in a first direction when the cross-sectional view is taken along a left or right side and the thickness of the top of the first portion of the conductive material and the width of the gate trenches will be in a second direction when the cross-sectional view is taken along a front side or a back side.)
Regarding Claim 21:
The examiner now points out that the combination of Hao and Lee discloses the portion of the conductive material that defines the gate runner deposited in a sufficiently narrow and deep trench has a triangular shaped void, as shown in fig. 4E of Lee, in the conductive material shown in fig. 3E of Hao. Therefore, the combination of Hao and Lee discloses wherein each of the extended portions comprises: a trench sidewall portion disposed on a sidewall of the first trenches (portion of the conductive material that defines a gate runner in gate runner trenches has a portion disposed on the sidewalls of the gate runner trenches through intervening polysilicon material, See Hao fig. 3E, ref. nos. 342, 370 and paragraph 57 and 66-67), and a trench bottom portion disposed on a bottom of the first trenches (portion of the conductive material that defines a gate runner in gate runner trenches has a portion disposed on the bottom of the gate runner trenches through intervening polysilicon material, See fig. 3E, ref. nos. 342, 370 and paragraph 57 and 66-67); wherein the trench sidewall portion has a convex shape toward an inside of the first trenches as it moves upward in a third direction(the conductive material surrounding the top point of the triangular shaped void, See Lee fig. 4E); wherein the trench bottom portion has a convex shape toward the inside of the first trenches (the conductive material surrounding the bottom points of the triangular shaped void, See Lee fig. 4E); and wherein the empty space of each of the first trenches is surrounded by the upper portion of the lower gate runner, the trench sidewall portion, and the trench bottom portion (the triangular shaped void is surrounded by the conductive material that defines the gate runner, See Lee fig. 4E).
Regarding Claim 22:
The examiner now points out that the combination of Hao and Lee discloses the portion of the conductive material that defines the gate runner deposited in a sufficiently narrow and deep trench has a triangular shaped void, as shown in fig. 4E of Lee, in the conductive material shown in fig. 3E of Hao. Therefore, the combination of Hao and Lee discloses wherein each of the extended portions comprises: a trench sidewall portion disposed on a sidewall of the first trenches (portion of the conductive material that defines a gate runner in gate runner trenches has a portion disposed on the sidewalls of the gate runner trenches through intervening polysilicon material, See Hao fig. 3E, ref. nos. 342, 370 and paragraph 57 and 66-67), and a trench bottom portion disposed on a bottom of the first trenches (portion of the conductive material that defines a gate runner in gate runner trenches has a portion disposed on the bottom of the gate runner trenches through intervening polysilicon material, See fig. 3E, ref. nos. 342, 370 and paragraph 57 and 66-67); wherein the trench sidewall portion has a convex shape toward an inside of the first trenches as it moves upward in a third direction(the conductive material surrounding the top point of the triangular shaped void, See Lee fig. 4E); wherein the trench bottom portion has a convex shape toward the inside of the first trenches (the conductive material surrounding the bottom points of the triangular shaped void, See Lee fig. 4E); and wherein the empty space of each of the first trenches is surrounded by the upper portion of the lower gate runner, the trench sidewall portion, and the trench bottom portion (the triangular shaped void is surrounded by the conductive material that defines the gate runner, See Lee fig. 4E).
8. Claims 8-11 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hao et al. (US 2013/0099311) in view of Lee et al. (US 8,803,251) further in view of Ma et al. (US 2014/0353748).
Regarding Claim 8:
The above stated combination of Hao and Lee discloses the above stated semiconductor device. Hao further discloses wherein the conductive region comprises:
the n+ type substrate (n-type substrate, See figs. 3A-3E, ref. nos. 320 and paragraphs 31-32);
an n-type layer disposed on the upper surface of the n+ type substrate (n-type epitaxial layer, See figs. 3A-3E, ref. no. 390, paragraphs 16, 31-32) and having a second trench (recess, See fig. 3D, ref. no. 348 and paragraphs 66-67) opening upward in the third direction;
a p type region (p-type active area implant, See fig. 3D, ref. no. 314 and paragraph 35) disposed within the n-type layer and disposed on a side of the second trench; and
a drain electrode (a drain on the backside of the substrate, See fig. 3E, ref. no. 320 and paragraph 74) disposed insulated from the gate electrode.
The above stated combination of Hao and Lee does not disclose a gate electrode disposed within the second trench; a source electrode disposed insulated from the gate electrode.
Ma discloses a gate electrode disposed (gate conduction layer filling lined gate trench, See fig. 3, ref. no. 2053 and paragraph 28) within a second trench and a source electrode (source electrode, See figs. 3-4, ref. no. 208 and paragraph 35) disposed insulated from the gate electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Hao and Lee to include a gate electrode disposed within a second trench and a source electrode disposed insulated from the gate electrode as taught by Ma in order electrically isolate the gate electrode from the source electrode.
Regarding Claim 9:
Ma discloses wherein the gate electrode is disposed only inside the second trench and does not protrude outside the second trench in the third direction (the gate conduction layer filling lined gate trench does not protrude outside the lined gate trench in the vertical direction, See fig. 3, ref.no. 2051, 2052, 2053, and paragraph 28).
Regarding Claim 10:
Hao discloses the gate runner trenches can have a width of approximately between 0.01µm and 50 µm. (See fig. 3B, ref. nos. O, N, 341, 344 and paragraphs 48-49.) Hao also discloses the gate runner trenches and the recess associated with the active device are of the same scale. (See fig. 3D, ref. nos. 344 and 348). Hao is silent with respect to the specific dimensions the recess associated with the active device, however, it would have been obvious to one of ordinary skill in the art to form the recess associated with the active device with a width greater than or equal to the width of the gate runner trench since it has been held changes in dimensions are an obvious expedient and not a patentable distinction where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device. Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Regarding Claim 11:
Hao discloses the gate runner trenches can have a width of approximately between 0.01µm and 50 µm and a depth of approximately between 0.01µm and 50 µm. (See fig. 3B, ref. nos. O, N, 341, 344 and paragraphs 48-49.) The examiner notes that the range of widths of 0.1um to 2um lies inside the range of widths disclosed by Hao and the range of depths of greater than or equal to 0.3um overlaps the ranges of depths disclosed by Hao overlaps, therefore, a prima facie case of obviousness exists for these ranges. Hao also discloses the gate runner trenches and the recess associated with the active device are of the same scale. (See fig. 3D, ref. nos. 344 and 348). Hao is silent with respect to the specific dimensions the recess associated with the active device, however, it would have been obvious to one of ordinary skill in the art to form the recess associated with the active device with a width greater than or equal to the width of the gate runner trench since it has been held changes in dimensions are an obvious expedient and not a patentable distinction where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device. Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Regarding Claim 15:
Hao discloses the above stated semiconductor device. Hao further discloses wherein the conductive region comprises:
the n+ type substrate (n-type substrate, See figs. 3A-3E, ref. nos. 320 and paragraphs 31-32);
an n-type layer disposed on the upper surface of the n+ type substrate (n-type epitaxial layer, See figs. 3A-3E, ref. no. 390, paragraphs 16, 31-32) and having a second trench (recess, See fig. 3D, ref. no. 348 and paragraphs 66-67) opening upward in the third direction;
a p type region (p-type active area implant, See fig. 3D, ref. no. 314 and paragraph 35) disposed within the n-type layer and disposed on a side of the second trench;
a gate electrode (portion of the conductive material in the recess, See fig. 3E, ref. nos. 348 and 370) disposed within the second trench; and
a drain electrode (a drain on the backside of the substrate, See fig. 3E, ref. no. 320 and paragraph 74) disposed insulated from the gate electrode.
Hao does not disclose a source electrode disposed insulated from the gate electrode.
Ma discloses a source electrode (source electrode, See figs. 3-4, ref. no. 208 and paragraph 35) disposed insulated from the gate electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Hao to include a source electrode disposed insulated from the gate electrode as taught by Ma in order to electrically isolated the source electrode and the gate electrode.
9. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Hao et al. (US 2013/0099311) in view of Lee et al. (US 8,803,251) further in view of Bless et al. (US 2021/0381100).
Regarding Claim 18:
The above stated combination of Hao and Lee discloses the above stated method of method of manufacturing a semiconductor device. Hao further discloses wherein the deposition method with a non-conformal step coverage comprises a plasma-enhanced chemical vapor deposition (PECVD) (depositing a conductive material over the gate runner trenches and the top surface of epitaxial layer using a plasma-enhanced CVD process, See fig. 3E, ref. no. 370 and paragraph 70)
The above stated combination of Hao and Lee is silent about the plasma-enhanced chemical vapor deposition method using a thermal evaporator.
Bless discloses chamber for plasma-enhanced chemical vapor deposition that includes a thermal evaporator (See paragraph 119).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing a semiconductor device of Hao and Lee to include using the plasma-enhanced chemical vapor deposition method using a thermal evaporator as taught by Bless for ease of fabrication of the semiconductor device by using known equipment for semiconductor fabrication.
Allowable Subject Matter
Claims 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: with respect to dependent claim 19, Hao further discloses forming a second trench in the n-type layer (recess, See fig. 3D, ref. no. 348 and paragraph 66), the second trench opening upward toward the upper surface of the n-type layer (See fig. 3D, ref. no. 348) and forming the preliminary gate electrode layer that fills an inside of the second trench and covers the n-type layer using the deposition method with the non-conformal step coverage (depositing a conductive material over the recess and the top surface of epitaxial layer using a plasma-enhanced CVD process, See fig. 3E, ref. nos. 348, 370 and paragraph 70). The disclosures and illustration of Hao and/or Lee as discussed above fail to teach or suggest the limitations of claims 19-20 because Hao does not teach etching a second portion of the preliminary gate electrode layer that covers the n- type layer until an upper surface of the preliminary gate electrode layer is disposed inside the second trench to form a gate electrode inside the second trench and forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode are each insulated from the gate electrode. Additionally, Lee does not teach etching a second portion of the preliminary gate electrode layer that covers the n- type layer until an upper surface of the preliminary gate electrode layer is disposed inside the second trench to form a gate electrode inside the second trench and forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode are each insulated from the gate electrode. The prior art also fails to provide other relevant disclosures which are properly combinable with Hao and/or Lee to teach and/or suggest the limitations of claims 19-20. Therefore, claims 19-20 include allowable subject matter.
Response to Arguments
Applicant's arguments with respect to claims 1-2, 4-13, and 15-20 and the combination of Hao and Lee filed on March 18, 2026 have been fully considered but they are not persuasive. The examiner respectfully disagrees with the applicant’s position that there is no motivation to combine Hao and Lee. The examiner first notes that Lee does not teach away from non-conformally depositing material in a manner that forms a triangular shaped void because Lee is indifferent to the formation of the triangular shaped void. “In FIG. 4E, an oxide 218 is filled into the termination trenches regardless of voids formation inside the trench as long as they are below the nitride layer surface 217 due to the trench profile.” See col. 4 lines 28-31. The examiner further notes that Lee does not call the triangular shaped void formed from non-conformally depositing a material is defect. The examiner next notes that a person of ordinary skill in the art would not view the formation of the triangular shaped void as a defect but rather a person of ordinary skill in the art would recognize the formation of the triangular shaped void as having the benefit of reducing coupling noise between the conductive material in the gate runner trenches. The examiner points out that it is known in the art that forming air gaps in metal line reduces coupling noise between the metal lines. (See CN 109950199 A to Yang et. al., fig. 5I, paragraphs 4-5, 62, and 73.) Accordingly, one of ordinary skill in the art would be motivated to non-conformally deposit material in a manner that forms a triangular shaped void to fill narrower trenches as semiconductor devices are continually miniaturized particularly when this technique has the added benefit of reducing coupling noise.
Applicant’s arguments, see page 6 lines 19-21, filed March 18, 2026 with respect to the rejections of claims 16 and 19-20 under 35 U.S.C. 103 as being unpatentable over Ma in view of Hao further in view of Sakamoto have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection of claim 16 is made under 35 U.S.C. 103 as being unpatentable over Hao in view of Lee.
Conclusion
13. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899
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