DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-15 & 20 is/are rejected under 35 U.S.C. (a)(1) as being anticipated by Morrow et al. (US 20180248012 ).
Regarding claim 1, Morrow discloses that a method for forming a semiconductor device, comprising:
forming a transistor structure 200 on a frontside of a substrate 201 & 202, the transistor structure comprising a first source/drain body 218 and a second source/drain body 208 located in a first source/drain region 208 and a second source/drain region 218, respectively, and a channel body comprising at least one channel layer extending horizontally between the first source/drain body 218 and the second source/drain body 218 (para. 0033);
forming a trench 211 beside the first source/drain region 208, wherein the trench is formed by etching the substrate 202 & 201 such that a lower portion of the trench 211 undercuts the first source/drain region 208 (Fig. 1-2C);
forming a dielectric liner 217 on interior surfaces of the trench;
forming an opening in the dielectric liner 217 (Fig. 2F), underneath the first source/drain region 208; and
subsequent to forming the opening in the dielectric liner (Fig. 2e, note: open shape after deposition), forming a dummy interconnect of a dummy material 214 in the trench (para. 0028, note: a temporary material);
wherein the method further comprises, subsequent to forming the dummy interconnect:
exposing the dummy interconnect 214 from a backside of the substrate 201 & 202;
removing the dummy interconnect selectively to the dielectric liner (Fig. 2n); and
forming a buried interconnect of a conductive material 230 in the trench, wherein the buried interconnect 230 is connected to the first source/drain body 218 via the opening in the dielectric liner 217 (Fig. 2P).
Reclaim 2, Morrow discloses that forming the trench comprises etching back the substrate in a direction towards the backside of the substrate to form an initial trench (Fig. 2e).
Reclaim 3, Morrow discloses that laterally etching back a sidewall of the initial trench to undercut the first source/drain region (Fig. 2e).
Reclaim 4, Morrow discloses that forming the trench further comprises laterally etching back a further sidewall of the initial trench, opposite the sidewall of the initial trench (Fig. 2e).
Reclaim 5, Morrow discloses that forming the trench comprises laterally etching back the sidewall of the initial trench to undercut the first source/drain region (Fig. 2e).
Reclaim 6, Morrow discloses that laterally etching back the sidewall of the initial trench comprises etching back the sidewall of the initial trench while masking an opposite sidewall of the initial trench (Fig. 2e).
Reclaim 7, Morrow discloses that forming the opening in the dielectric liner comprises: forming a mask layer 210 over the frontside of the substrate, patterning a mask opening in the mask layer, the mask opening exposing a removal portion of the dielectric liner, and subjecting the removal portion of the dielectric liner to an isotropic etch from the mask opening in the mask layer to form the opening in the dielectric liner (para. 0027).
Reclaim 8, Morrow discloses that the mask layer comprises a mask material filling the trench, wherein the mask opening is patterned in the mask material by removing the mask material along the removal portion of the dielectric liner, and wherein the mask material is removed by etching from an access opening formed in the substrate at a distal side of the first source/drain region and communicating with the lower portion of the trench for the buried interconnect (para. 0027).
Reclaim 9, Morrow discloses that the opening in the dielectric liner subsequently is formed by etching from the access opening (para. 0027, Fig. 2c).
Reclaim 10, Morrow discloses that the trench for the buried interconnect is formed to extend beside and undercut the first source/drain region and the channel body, and wherein the opening in the dielectric liner is formed underneath the first source/drain region such that the dielectric liner is preserved underneath the channel body (Fig. 2o-p).
Reclaim 11, Morrow discloses that the transistor structure further comprises a gate structure 226 extending across the channel body (Fig. 2p).
Reclaim 12, Morrow discloses that the gate structure is formed prior to forming the trench for the buried interconnect (Fig. 2a).
Reclaim 13, Morrow discloses that the method further comprises cutting the gate structure on a first lateral side of the transistor structure and thereafter forming the trench by etching the substrate on the first lateral side (Fig. 2P).
Reclaim 14, Morrow discloses that the gate structure is cut and the trench for the buried interconnect is formed using a common etch mask (Fig. 2a & 2p).
Reclaim 15, Morrow discloses that subsequent to removing the dummy interconnect and prior to forming the buried interconnect, forming an opening in a bottom dielectric layer formed underneath the transistor structure to expose a portion of the first source/drain body (Fig. 2m-2n), wherein the opening in the bottom dielectric layer is formed by etching the bottom dielectric layer from the opening in the dielectric liner (Fig. 2n).
Reclaim 20, Morrow discloses that subsequent to removing the dummy interconnect, growing 214, via the opening in the dielectric liner 217, an epitaxial source/drain contact portion 230 on an exposed surface portion of the first source/drain body, and thereafter forming the buried interconnect (Fig. 2e).
Allowable Subject Matter
Claims 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SU C KIM/ Primary Examiner, Art Unit 2899