DETAILED ACTION
This Office action responds to the patent application no. 18/524,544 filed on November 30, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to because the line for 162 in FIGs. 1-4, is not long enough to point to the second gate electrode area and currently is pointing to the lower portion of the gate insulation layer 156. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a) because they fail to show “the lower surface 142BL of the second N+ type region 142 may be located … lower than the upper surface 162UL of the second gate electrode 162 in the Y direction” as described in the paragraph (¶) [0060] of the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the lower surface of the second N+ type region is lower than the upper surface of the second gate electrode in the first direction” must be shown or the feature(s) canceled from the claim 3. No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 3 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Claim 1 recites “a first gate electrode having an upper surface that is lower than an upper surface of the P type region in the first direction” and “a second gate electrode having an upper surface that is lower than the upper surface of the first gate electrode in the first direction”. Therefore, when Claim 3 recites “the lower surface of the second N+ type region is lower than the upper surface of the second gate electrode in the first direction”, the specification does not provide enough description for one skilled in the semiconductor art to understand how this new limitation can be formed or manufactured. Based on the specification, only the gates 161 and 162 are below the P type region 130 and the second N+ type region is 142-2 and “the lower surface 142BL of the second N+ type region 142 may be located substantially at the same position as the upper surface 162UL of the second gate electrode 162” in ¶ [0060]
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 18 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kaneko et al. (Kaneko hereinafter) (JP 2005-26391).
Regarding Claims 18 and 19:
Kaneko (see FIGs. 1-5 and 7) teaches
{18} a method of manufacturing a semiconductor device, the method comprising: forming an N- type layer 3 on an upper surface of an N- type substrate 2 in a first direction; forming a P type region 4 in the N- type layer; etching the N- type layer to penetrate the P type region to form a trench 7; filling the trench with a preliminary gate electrode layer; over-etching the preliminary gate electrode layer 8 until an upper surface 13 of the preliminary gate electrode layer is lower than an upper surface of the P type region in the first direction to form a gate electrode and to expose a portion of a side surface of the trench; implanting N type ions into the upper surface of the P type region disposed adjacent to the trench and the exposed portion of the side surface of the trench to form an N+ type region 6; and forming a source electrode 12 and a drain electrode D to be insulated from the gate electrode; and
{19} implanting the N type ions into the upper surface of the P type region disposed adjacent to the trench and the exposed portion of the side surface of the trench to form the N+ type region is performed after forming a hard mask on the P type region exposing the upper surface of the P type region disposed adjacent to the trench.
Kaneko (see ¶ [0021], [0022], [0026]) teaches “a photoresist having an opening in a portion where the N- -type first diffusion region 5 is formed” “in order to form the N+ -type second diffusion region 6, an N-type impurity … is ion-implanted … Thereafter, the photoresist is removed ”; “the trenches 7 at the center and left side of the cross section shown in FIG. 4, the polysilicon 9 is cut away and formed to be recessed below the surface of the P-type diffusion region 4”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kaneko et al. (Kaneko hereinafter) (JP 2005-26391) as applied to claim 18 above, and further in view of Ninomiya (US 2003/003637).
Regarding to Claim 20:
Kaneko does not explicitly teach implanting the N type ions into the upper surface of the P type region disposed adjacent to the trench and the exposed portion of the side surface of the trench to form the N+ type region is performed using a tilt ion implantation method.
Ninomiya (see FIGs. 6 and 7 and ¶ [0056]) teach “the wafter is tilted while impurity ions are introduced; that is the ions are implanted at slant angle … varying the angle at which the wafter is tilted enables control of a depth which the introduced impurities reach”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Kaneko to further include the teaching of Ninomiya to use tilt ion implantation method to form the N-type double diffused structure to control the depth of the ions being implanted.
Claims 1, 2, 4-8, and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kaneko et al. (Kaneko hereinafter) (JP 2005-26391) in view of Noda (WO 2011/108191).
Regarding Claims 1, 2, 4-8, and 12-14:
Kaneko (see FIGs. 1-5 and 7) teaches
{1} a semiconductor device comprising: an N+ type substrate 2; an N- type layer 3 disposed on the N+ type substrate in a first direction and having a trench 7 opening upward in the first direction; a P type region 4 disposed within the N- type layer and disposed on a side of the trench; an N+ type region 6 disposed within the P type region and disposed on the side of the trench; a gate electrode 9/28 disposed within the trench, the gate electrode comprising a first gate electrode 9/28 (left) having an upper surface 13 that is lower than an upper surface of the P type region in the first direction and a second gate electrode 9/28 (middle) having an upper surface that is lower than the upper surface of the first gate electrode 9/28 (left) in the first direction; and a source electrode 12 and a drain electrode D insulated from the gate electrode;
{4} the trench has side surfaces extending in a second direction perpendicular to the first direction and facing each other in a third direction perpendicular to the first direction and different from the second direction;
{7} the gate electrode further comprises a third gate electrode 9/28 (right) having an upper surface at substantially a same level in the first direction as the upper surface of the P type region;
{8, 14} the N+ type region further comprises a third N+ type region 6/25 disposed on a side of the third gate electrode and having a lower surface that is lower than the upper surface of the first gate electrode in the first direction;
{12} a semiconductor device comprising: an N- type layer 3 having a trench 7 opening upward in a first direction; a P type region 4 disposed within the N- type layer and disposed on a side of the trench, an N+ type region 6 disposed within the P type region and disposed on the side of the trench; a gate electrode 9/28 disposed within the trench, wherein the gate electrode comprises a first gate electrode 9/28 (left) having an upper surface 13 that is lower than an upper surface of the P type region in the first direction and a second gate electrode 9/28 (middle) having an upper surface 13 that is lower than the upper surface of the first gate electrode in the first direction; and
{13} the gate electrode further comprises a third gate electrode 9/28 (right) having an upper surface at substantially a same level in the first direction as the upper surface of the P type region.
Kaneko (see ¶ [0026]) teaches “the trenches 7 at the center and left side of the cross section shown in FIG. 4, the polysilicon 9 is cut away and formed to be recessed below the surface of the P-type diffusion region 4”.
However, Kaneko does not explicitly teach {1} wherein the N+ type region comprises: a first N+ type region 6 disposed on a side of the first gate electrode and having a lower surface that is lower than the upper surface of the first gate electrode in the first direction and a second N+ type region 5 disposed on a side of the second gate electrode and having a lower surface that is lower than the lower surface of the first N+ type region in the first direction; {2} the lower surface of the second N+ type region is substantially at a same height as the upper surface of the second gate electrode in the first direction; {4} the second N+ type region has an upper portion and a lower portion having different maximum lengths in the third direction from one side of the trench; {5} the upper portion of the second N+ type region has a greater maximum length in the third direction from the one side of the trench than the lower portion of the second N+ type region; {6} the upper portion of the second N+ type region is disposed on the lower portion of the second N+ type region in the first direction; {12} an emitter electrode 12 and a collector electrode D insulated from the gate electrode; and a P+ type layer disposed between the N- type layer and the collector electrode; and wherein the N+ type region comprises: a first N+ type region disposed on a side of the first gate electrode and having a lower surface that is lower than the upper surface of the first gate electrode in the first direction; and a second N+ type region disposed on a side of the second gate electrode and having a lower surface that is lower than the lower surface of the first N+ type region in the first direction.
Noda (see FIGs. 3a, 3b, 4, 9a, 9b, 10, 14b, 18b, and 23) teaches the source layer 10, 31, 51, 70 formed by angled ion implantation methods, formed into bracket shape with a shallow depth on the upper layer and deeper lower layer, and having high concentration of 5x1020/cm3 and insulated gate bipolar transistor having similar layered structure as the vertical MOSFET and having emitter electrode 302 on the top and a collector electrode 303 on the bottom.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Kaneko to further include the teaching of Noda to anticipate the n+ doping formed not only horizontally, but vertically when angled ion implantation method is used and when the gate electrode is low enough in the trenches so that the appearance of two n+ doped regions are formed to improve the process control and profile control and to utilize the vertical MOSFET structure as an IGBT with emitter electrode instead of source electrode on the top and with collector electrode instead of drain electrode on the bottom to provide switching capability for power supply control.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kaneko et al. (Kaneko hereinafter) (JP 2005-26391) in view of Noda (WO 2011/108191) as applied to claim 1 above, and further in view of Nakamura et al. (Nakamura hereinafter) (US 2009/0236612).
Regarding Claim 3:
Kaneko in the device of Noda does not explicitly teach the lower surface of the second N+ type region is lower than the upper surface of the second gate electrode in the first direction.
Nakamura (see FIGs. 1-3 and ¶ [0057]) teaches vertical MOSFET having an upper layer of source contact region 6 with a doping concentration greater than 3x1019, source extension regions 6-1 with a doping concentration between 5x1018 to 3x1019 and tail part 6-2 which has lower surface located below the top surface of the gate electrode 12.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Kaneko in the device of Noda to further include the teaching of Nakamura to form a tail part lower than the upper surface of the gate electrode to further reduce the resistance of the p-type region.
Claims 9-11 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kaneko et al. (Kaneko hereinafter) (JP 2005-26391) in view of Noda (WO 2011/108191) as applied to claim 1 or 12 above, and further in view of Hashimoto et al. (Hashimoto hereinafter) (US 2016/0013300).
Regarding to Claims 9-11 and 15-17:
Kaneko in the device of Noda does not explicitly teach {9, 15} a P type shield region surrounding a lower surface and both lower edges of the trench; {10, 16} an asymmetric P type region surrounding a first lower edge and a first side of the trench and connected to the P type region; and {11, 17} the asymmetric P type region surrounds a portion of a lower surface of the trench; and the asymmetric P type region does not surround a second lower edge of the trench or a second side of the trench.
Hashimoto (see FIGs. 10, 15, 16) teaches a p-type region 43 around the bottom portion of the trench gate 8 without contacting the p type channel layer 3 or a p- type breakdown voltage holding layer 2 around the bottom portion of the trench gate 8 while contacting the p-type channel layer or a p- type breakdown voltage holding layer 2 between the n- type layer 1 and the p-type channel layer 3.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Kaneko in the device of Noda to further include the teaching of Hashimoto to add p-type shield layer surrounding the gate trench either completely or partially touching the p-type channel layer to achieve the desirable breakdown voltage for the transistor.
Regarding to Claims 10, 11, 16, and 17:
The differences in shape and size of the p-type shield layer will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such shape and size of the p-type shield layer are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the instant invention, it would have been obvious to one of ordinary skill in the art to form asymmetric p-type shield layer partially contacting p-type channel layer to achieve the desirable breakdown voltage for the transistor.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934, 1936s (Fed. Cir. 1990).
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALICE W TANG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814