CTNF 18/524,571 CTNF 79224 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of claims 1-11 and 19-30 in the reply filed on 4/20/26 is acknowledged. 08-06 AIA Claim s 12-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/20/26 . Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted on 10/23/25. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification 06-31 AIA The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-11 and 19-30 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Qian et al. (US PGPub 2022/0199537, hereinafter referred to as “Qian”) . Qian discloses the semiconductor device as claimed. See figures 1-9, and corresponding text, where Qian teaches, in claim 1 , an integrated device comprising: a substrate (106) including: a core layer ([0108]); a bridge die (103) within the core layer and including first contacts (101) and second contacts (102) , the first contacts electrically connected to the second contacts via conductive traces of the bridge die (103) ; at least one dielectric layer on a surface of the core layer and the bridge die; third contacts on a surface of the at least one dielectric layer and electrically connected to the first contacts (figure 1; [0031-0037]); and fourth contacts on the surface of the at least one dielectric layer and electrically connected to the second contacts (figure 1; [0031-0037]). Qian teaches, in claim 2 , wherein the conductive traces are configured to propagate signals between a first die and a second die on a surface of the substrate, and wherein the third contacts are arranged to match a first contact pattern of the first die and the fourth contacts are arranged to match a second contact pattern of the second die (figure 1; [0031-0037]). Qian teaches, in claim 3 , wherein the first die and the second die are in a side-by-side configuration on the surface of the substrate (figure 1; [0031-0037]). Qian teaches, in claim 4 , wherein the first die includes one or more processor cores and also includes fifth contacts arranged according to the first contact pattern, and wherein the second die includes one or more memory cells and also includes sixth contacts arranged according to the second contact pattern (figure 1; [0031-0037]). Qian teaches, in claim 5 , wherein the first die is a first chiplet and the second die is a second chiplet designed to operate in conjunction with the first chiplet (figure 1; [0031-0037]). Qian teaches, in claim 6 , wherein first circuitry of the first chiplet includes one or more first functional circuit blocks and second circuitry of the second chiplet includes one or more second functional circuit blocks, and wherein the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent upon one another (figure 1; [0031-0037]). Qian teaches, in claim 7 , wherein the substrate further comprises one or more metal layers defining additional conductive traces configured to propagate additional signals from the first die to the second die (figure 1; [0031-0037]). Qian teaches, in claim 8 , wherein the conductive traces of the bridge die are longer than the additional conductive traces (figure 1; [0031-0037]). Qian teaches, in claim 9 , wherein the bridge die is devoid of active circuitry (figure 1; [0031-0037]). Qian teaches, in claim 10 , wherein the bridge die includes a silicon die ([0023]). Qian teaches, in claim 11 , further comprising: one or more seventh contacts on the surface of the at least one dielectric layer; at least one second dielectric layer on a second surface of the core layer and the bridge die; and one or more eighth contacts on a surface of the at least one second dielectric layer, the one or more seventh contacts electrically connected to the one or more eighth contacts via one or more signal paths through the substrate (figure 1; [0031-0037]). Qian teaches, in claim 19 , a device comprising: a substrate (106) including: (figure 1; [0031-0037]) a core layer; a bridge die (103) within the core layer and including first contacts (101) and second contacts (102) , the first contacts electrically connected to the second contacts via conductive traces of the bridge die (103) ; at least one dielectric layer on a surface of the core layer and the bridge die; third contacts on a surface of the at least one dielectric layer and electrically connected to the first contacts; and fourth contacts on the surface of the at least one dielectric layer and electrically connected to the second contacts; a first die including fifth contacts electrically connected to the third contacts; and a second die including sixth contacts electrically connected to the fourth contacts (figure 1; [0031-0037]). Qian teaches, in claim 20 , wherein the first die and the second die have a side-by-side configuration on the surface of the at least one dielectric layer (figure 1; [0031-0037]). Qian teaches, in claim 21 , wherein the conductive traces are configured to propagate signals between the first die and the second die (figure 1; [0031-0037]). Qian teaches, in claim 22 , wherein the first die includes one or more processor cores and the second die includes one or more memory cells (figure 1; [0031-0037]). Qian teaches, in claim 23 , wherein the first die is a first chiplet and the second die is a second chiplet designed to operate in conjunction with the first chiplet (figure 1; [0031-0037]). Qian teaches, in claim 24 , wherein first circuitry of the first chiplet includes one or more first functional circuit blocks and second circuitry of the second chiplet includes one or more second functional circuit blocks, and wherein the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent upon one another (figure 1; [0031-0037]). Qian teaches, in claim 25 , wherein the substrate further comprises one or more metal layers defining additional conductive traces configured to propagate additional signals between the first die and the second die (figure 1; [0031-0037]). Qian teaches, in claim 26 , wherein the conductive traces of the bridge die are longer than the additional conductive traces (figure 1; [0031-0037]). Qian teaches, in claim 27 , further comprising a heat management device configured to dissipate heat of at least the first die (figure 1; [0031-0037]). Qian teaches, in claim 28 , wherein the bridge die is devoid of active circuitry (figure 1; [0031-0037]). Qian teaches, in claim 29 , wherein the bridge die includes a silicon die ([0023]). Qian teaches, in claim 30 , further comprising: one or more seventh contacts on the surface of the at least one dielectric layer; at least one second dielectric layer on a second surface of the core layer and the bridge die; and one or more eighth contacts on a surface of the at least one second dielectric layer, the one or more seventh contacts electrically connected to the one or more eighth contacts via one or more signal paths through the substrate (figure 1; [0031-0037]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STANETTA D ISAAC/Examiner, Art Unit 2898 May 30, 2026 Application/Control Number: 18/524,571 Page 2 Art Unit: 2898 Application/Control Number: 18/524,571 Page 3 Art Unit: 2898 Application/Control Number: 18/524,571 Page 4 Art Unit: 2898 Application/Control Number: 18/524,571 Page 5 Art Unit: 2898 Application/Control Number: 18/524,571 Page 6 Art Unit: 2898 Application/Control Number: 18/524,571 Page 7 Art Unit: 2898 Application/Control Number: 18/524,571 Page 8 Art Unit: 2898
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