DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/30/2023 was being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Do_673 et al., (United States Patent Number, US 11,335,673 B2) hereinafter referenced as Do_673.
Regarding claim 1, Do_673 teaches a semiconductor device, comprising: at least one active region layer having source/drain regions laterally disposed relative to one another in a row and having a zone disposed between adjacent source/drain regions (Fig.2A, active region element #R22 has source and drain regions, column 6, rows 40-45); and an embedded jumper electrically connected to two adjacent source/drain regions within the zone (column 6, rows 34-40, and, Fig.3A, jumper, element #CA31 is embedded under upper metal layers, element #V31 and #M31. While Do_673 doesn’t explicitly mention, it is well known in the art that dielectric materials are used between metal levels).
Regarding claim 2, Do_673 teaches the semiconductor device of claim 1 as set forth in the anticipation rejection. Do_673 further teaches the semiconductor device as recited in claim 1, wherein the embedded jumper comprises at least one conducting material (the jumper electrically connects the source/drain, column 6, rows 36-38, therefore must comprise at least one electrically conductive material).
Regarding claim 3, Do_673 teaches the semiconductor device of claim 1 as set forth in the anticipation rejection. Do_673 further teaches the semiconductor device as recited in claim 1, wherein the embedded jumper connects a component in a top region of the semiconductor device to a component in a bottom region of the semiconductor device (Fig.3C, the jumper, element #CB31 connects element #M33 to substrate).
Regarding claim 4, Do_673 teaches the semiconductor device of claim 1 as set forth in the anticipation rejection. Do_673 further teaches the semiconductor device as recited in claim 1, wherein the embedded jumper connects a component in a top region of the semiconductor device to another component in the top region of the semiconductor device (Fig.3C, the jumper, element #CB31 connects element #M33 to element #TS33, where the BEOL is the top region).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Do_673 and in view of Sharma et al., (United States Patent Application Publication Number, US 2025/0098204 A1) hereinafter referenced as Sharma.
Regarding claim 5, Do_673 teaches the semiconductor device of claim 1 as set forth in the anticipation rejection. Do_673 does not teach the semiconductor device as recited in claim 1, wherein the embedded jumper connects at least one component in a bottom region of the semiconductor device to at least one other component in the bottom region of the semiconductor device. Sharma teaches wherein the embedded jumper connects at least one component in a bottom region of the semiconductor device to at least one other component in the bottom region of the semiconductor device (Fig.5C, the jumper, element #275, connects elements #360). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Sharma and disclose wherein the embedded jumper connects at least one component in a bottom region of the semiconductor device to at least one other component in the bottom region of the semiconductor device. As disclosed by Sharma, the backside components located in the bottom region of the semiconductor device can be used to provide voltage/power to the source and drain from backside power rails, and, as disclosed by Do_673, the jumper that connects the components can be further connected to frontside metal lines. This allows backside voltage/power distribution to other elements of the circuit through a robust connection provided by the jumper and the components in the bottom region of the device.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Do_673 and in view of Do et al., (United States Patent Application Publication Number, US 2018/0226323 A1) hereinafter referenced as Do_323.
Regarding claim 6, Do_673 teaches the semiconductor device of claim 1 as set forth in the anticipation rejection. Do_673 does not teach he semiconductor device as recited in claim 1, further comprising a series of embedded jumpers disposed between a plurality of adjacent source/drain regions within respective zones, resulting in a connection across multiple adjacent source/drain regions. Do_323 teaches a series of embedded jumpers disposed between a plurality of adjacent source/drain regions within respective zones resulting in an electrical connection across multiple adjacent source/drain regions (Fig.30, jumpers elements #510 and #530, paragraph [0147], rows 4-15). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Do_323 and disclose the semiconductor device further comprising a series of embedded jumpers disposed between a plurality of adjacent source/drain regions within respective zones to arrange an electrical connection across multiple adjacent source/drain regions. As disclosed by Do_323, this allows connecting the source and drain regions across multiple cells defining an integrated circuit (Fig.30, along horizontal direction), while minimizing the number of metal routing lines, which helps maintaining or reducing the cells footprint (paragraph [0003], rows 5-12).
Claims 9, 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Do_673 and in view of Wieduwilt et al., (United States Patent Application Publication Number, US 2023/0074975 A1) hereinafter referenced as Wieduwilt.
Regarding claim 9, Do_673 teaches the semiconductor device of claim 1 as set forth in the anticipation rejection. Do_673 further teaches the semiconductor device as recited in claim 1, further comprising a diffusion break between the adjacent source/drain regions, wherein the diffusion break prevents electrical conduction between the adjacent source/drain regions (Fig.6, diffusion break, element #CT61, column 11, rows 66-67 and column 12, rows 1-10). Do_673 does not teach the diffusion break formed in another zone between the adjacent source/drain regions. Wieduwilt teaches a diffusion break formed in another zone between the adjacent source/drain regions (Fig.13, the diffusion break is element #1332 which is located between the source/drain regions elements #1312 and #1306, while the jumper, element #1336, is located in the zone between source/drain regions, element #1306 and #1305). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Wieduwilt and disclose the semiconductor device further comprising a diffusion break formed in another zone between the adjacent source/drain regions. As disclosed by Wieduwilt, the diffusion break can be used to separate the source or drain of an antifuse transistor from the source and drain of a selection transistor that together form an antifuse circuit (paragraph [0075], rows 1-9).
Regarding claim 10, Do_673 teaches the semiconductor device of claim 1 as set forth in the anticipation rejection, and the combination of Do_673 and Wieduwilt teaches the semiconductor device of claim 9 as set forth in the obviousness rejection. Do_673 further teaches the semiconductor device as recited in claim 9, wherein the diffusion break includes at least one nonconducting material (Fig.6, diffusion break, element #CT61, column 11, rows 66-67 and column 12, rows 1-10).
Regarding claim 20, Do_673 teaches a semiconductor device, comprising: a row of source/drain regions laterally disposed relative to one another to provide a zone between adjacent source/drain regions (Fig.2A, active region element #R22 has a rows of source and drain regions, column 6, rows 40-45); an embedded jumper connected between adjacent source/drain regions within a zone (column 6, rows 34-40, and, Fig.3A, jumper, element #CA31 is embedded under upper metal layers, element #V31 and #M31. While Do_673 doesn’t explicitly mention, it is well known in the art that dielectric materials are used between metal levels); and a diffusion break disposed between adjacent source/drain regions (Fig.6, diffusion break, element #CT61, column 11, rows 66-67 and column 12, rows 1-10). Do_673 does not teach the diffusion break formed in another zone between the adjacent source/drain regions. Wieduwilt teaches a diffusion break formed in another zone between the adjacent source/drain regions (Fig.13, the diffusion break is element #1332 which is located between the source/drain regions elements #1312 and #1306, while the jumper, element #1336, is located in the zone between source/drain regions, element #1306 and #1305). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Wieduwilt and disclose the semiconductor device further comprising a diffusion break formed in another zone between the adjacent source/drain regions. As disclosed by Wieduwilt, the diffusion break can be used to separate the source or drain of an antifuse transistor from the source and drain of a selection transistor that together form an antifuse circuit (paragraph [0075], rows 1-9).
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma, in view of Do_673.
Regarding claim 11, Sharma teaches a semiconductor device, comprising: a row of source/drain regions laterally disposed relative to one another to provide a zone between adjacent source/drain regions (Fig.5C, source/drain regions, elements #345); a top metallization region of the semiconductor device positioned over the row of source/drain regions (Fig.5B, formed by elements #270 and #275); a bottom metallization region of the semiconductor device positioned below the row of source/drain regions (Fig.5B, element #240 and element #360 shown in Fig.5C); and a jumper electrically connected between two source/drain regions within the zone (Fig.5B, element #257 is within the zone). Sharma does not teach the jumper is embedded. Do_673 teaches the jumper is embedded (Fig.3A, jumper, element #CA31 is embedded under upper metal layers, element #V31 and #M31; While Do_673 doesn’t explicitly mention, it is well known in the art that dielectric materials are used between metal levels). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Do_673 and disclose the jumper is embedded. As disclosed by Do_673, the upper metal lines connected to and above the jumper may form circuit patterns, which allow for an easier routing (column 13, rows 25-35).
Regarding claim 12, the combination of Sharma and Do_673 teaches the semiconductor device of claim 11, as set forth in the obviousness rejection. Sharma further teaches the semiconductor device as recited in claim 11, wherein the embedded jumper connects two adjacent source/drain regions and conducts charge in accordance with a transistor disposed within the row (Fig.5C, element #520 is a gate, with a channel, paragraph [0057], rows 1-10).
Regarding claim 13, the combination of Sharma and Do_673 teaches the semiconductor device of claim 11, as set forth in the obviousness rejection. Sharma further teaches the semiconductor device as recited in claim 11, wherein the embedded jumper electrically connects at least one component in the top metallization region of the semiconductor device to at least one component in the bottom metallization region of the semiconductor device (Fig.5C, the jumper, element #275, electrically connects element #270 located on the left side of the figure to element #360 located on the right side of the figure).
Regarding claim 14, the combination of Sharma and Do_673 teaches the semiconductor device of claim 11, as set forth in the obviousness rejection. Sharma further teaches the semiconductor device as recited in claim 11, wherein the embedded jumper electrically connects a component in the top metallization region of the semiconductor device to another component in the top metallization region of the semiconductor device (Fig.5C the jumper, element #275, electrically connects elements #270).
Regarding claim 15, the combination of Sharma and Do_673 teaches the semiconductor device of claim 11, as set forth in the obviousness rejection. Sharma further teaches the semiconductor device as recited in claim 11, wherein the embedded jumper electrically connects a component in the bottom metallization region of the semiconductor device to another component in the bottom metallization region of the semiconductor device (Fig.5C, the jumper, element #275, electrically connects elements #360).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Sharma in view of Do_673 and in view of Do_323.
Regarding claim 16, the combination of Sharma and Do_673 teaches the semiconductor device of claim 11, as set forth in the obviousness rejection. The combination of Sharma and Do_673 does not teach the semiconductor device as recited in claim 11, further comprising a series of embedded jumpers disposed between a plurality of adjacent source/drain regions within respective zones to arrange an electrical connection across multiple adjacent source/drain regions. Do_323 teaches a series of embedded jumpers disposed between a plurality of adjacent source/drain regions within respective zones to arrange an electrical connection across multiple adjacent source/drain regions (Fig.30, jumpers elements #510 and #530, paragraph [0147], rows 4-15). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Do_323 and disclose the semiconductor device further comprising a series of embedded jumpers disposed between a plurality of adjacent source/drain regions within respective zones to arrange an electrical connection across multiple adjacent source/drain regions. As disclosed by Do_323, this allows connecting the source and drain regions across multiple cells defining an integrated circuit (Fig.30, along horizontal direction), while minimizing the number of metal routing lines which helps maintaining or reducing the cells footprint (paragraph [0003], rows 5-12).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Sharma in view of Do_673 and in view of Wieduwilt.
Regarding claim 19, the combination of Sharma and Do_673 teaches the semiconductor device of claim 11, as set forth in the obviousness rejection. Sharma does not teach the semiconductor device as recited in claim 11, further comprising a nonconducting diffusion break formed in another zone between the adjacent source/drain regions. Do_673 teaches a nonconducting diffusion break formed in between the adjacent source/drain regions
(Fig.6, diffusion break, element #CT62, column 11, rows 66-67 and column 12, rows 1-10). The combination of Sharma and Do_673 does not teach the semiconductor device further comprising a nonconducting diffusion break formed in another zone between the adjacent source/drain regions. Wieduwilt teaches the semiconductor device further comprising a nonconducting diffusion break formed in another zone between the adjacent source/drain regions (Fig.13, the diffusion break is element #1332 which is located between the source/drain regions elements #1312 and #1306, while the jumper, element #1336, is located in the zone between source/drain regions, element #1306 and #1305). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Wieduwilt and disclose the semiconductor device further comprising a nonconducting diffusion break formed in another zone between the adjacent source/drain regions. As disclosed by Wieduwilt, the diffusion break can be used to separate the source or drain of an antifuse transistor from the source and drain of a selection transistor that together form an antifuse circuit (paragraph [0075], rows 1-9).
Allowable Subject Matter
Claims 7, 8, 17 and 18 are allowed.
The following is a statement of reasons for the indication of allowable subject matter.
Regarding claims 7 the cited prior art does not teach or fairly suggests, along with other claimed features: “and the embedded jumper replaces the gate structure.”
Regarding claims 8 the cited prior art does not teach or fairly suggests, along with other claimed features: “the embedded jumper replaces the field effect transistor channel.”
Regarding claims 17 the cited prior art does not teach or fairly suggests, along with other claimed features: “wherein the embedded jumper replaces a gate structure in the zone.”
Regarding claims 18 the cited prior art does not teach or fairly suggests, along with other claimed features: “wherein the embedded jumper replaces semiconductor channels in the zone.”
Conclusion
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899