Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Election was made without traverse in the reply filed on 8/13/2026.
Applicant has elected Species Ai, corresponding to 1-7, 15-17, and 19.
Invention Species Aii and Aiii, corresponding to 8-14, 18 and 20, are withdrawn from further consideration.
Information Disclosure Statements
The information disclosure statements (IDS) submitted recently have been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 5: “wherein the one or more groups comprise varying numbers of the plurality of pixel drivers.”
The drawings are also objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description:
[0024] describes feature 420.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
[0004-9] there is no brief description of Fig. 2; also many of the brief descriptions are lacking verbs
[0016] describes “The one or more pixel drivers 130 can be design to be include…” which appears to need revision in order to conform with standard English
[0019] “FIG. 2 IS a diagram” appears to be a capitalization issue
[0021] teaches a feature 120 that is not in the drawings.
[0022] has a typographical error “cam electrically connect…”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 recites the limitation "configure the one or more pixel drivers" in the last limitation. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-14 inherit this same antecedence issue.
Claim 15 has a similar antecedence issue in its final limitation.
Claims 16-20 inherit this same antecedence issue.
For the sake of compact prosecution the examiner presumes that this one or more pixel drivers feature is referring to the plurality of pixel drivers.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5, 7, 15-17, and 19 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Li (US # 20200098307).
Regarding Claim 1, Li-307 teaches a device (SLM 100) comprising:
a complementary metal-oxide semiconductor (CMOS) backplane (a silicon backplane whose pixel drive circuits each contain a CMOS static RAM latch built from n-channel FETs 258, 259, 260, 261 and p-channel FETs 262, 263; see [0023, 47-48]) comprising multiple light emitting diode (LED) pixels areas (array of conductive mounting plates 391, 392, 393, 394, each a mounting plate for a single emissive device such as an LED; FIG. 3B; [0073]; the plurality of 5x5 conductive mounting plate outlines defined by dashed lines 38la-38le and 382a-382e);
a plurality of pixel drivers (130) inside the CMOS backplane (see [0023]), each pixel driver of the plurality of pixel drivers being coupled to a ground (the sources of n-channel FETs are connected to VSS (ground) over conductor 512, FIG. 2D, [0063]; additionally, where a bias circuit is present, source 332 of bias FET 330 is connected to VSS over conductor 333, FIG. 2C, [0053], and the source of the large L n-channel FET of bias circuit 502 is connected to VSS over conductor 533, FIG. 2D, [0066); VSS is identified as ground at [0063], [0092) and [0096]),
wherein one or more metal interconnect layers of the CMOS backplane (the top metal layer into which the conductive mounting plate is designed, the via layer, and "an additional metal layer"; [0075]; the pixel circuit is "connected to an emissive device through a metal layer," [0071]; the backplane is adapted by "changing a single metal layer," [0002, 007]) configure the one or more pixel drivers into the one or more groups (a plurality of emissive element drivers is mated to a single mounting pad, resulting in a summing of their currents, [0023]; the pixel drive circuits underlying conductive mounting plate 391 are connected to that plate through the via mask, and because they are in parallel the peak current available at the plate is the sum of their individual peak currents, [0073-75]; "as many as 25 parallel pixel drive circuits delivering current to the mounting plate," [0102]) corresponding to the multiple LED pixels areas ([0023, 73]).
Regarding Claim 3, Li-307 teaches the device of claim 1, wherein the one or more metal interconnect layers comprise a top layer (the top metal layer, into which the conductive mounting plate is designed; [0075]; conductive mounting plate 391, FIG. 3B, [0073]) that provides a shorting between the plurality of pixel drivers (the plate ties the outputs of the underlying pixel drive circuits together in parallel so that the current available at the plate is the sum of their individual currents; [0074]; each conductive mounting plate "can receive the output of 25 pixel current mirror drive circuits," and the corresponding witness arrangement 630 has the drains of the mirror circuits of 25 pixels "shorted together"; [0100]).
Regarding Claim 4, Li-307 teaches the device of claim 1, wherein the one or more groups comprise a same number of the plurality of pixel drivers (conductive mounting plate 391 covers a 5x5 area of pixel driver circuits, and conductive mounting plates 392, 393 and 394 "would each cover a 5x5 section of pixel drive circuits," i.e., 25 per plate; [0073]; the plurality of plates of FIG. 3C are all of the same 5x5 outline; [0077]; FIG. 3C).
Regarding Claim 5, Li-307 teaches the device of claim 1, wherein the one or more groups comprise varying numbers of the plurality of pixel drivers (the number of pixel drive circuits connected to a conductive mounting plate is set by "the peak current required to drive the emissive device at the desired intensity," and is changed by changing the via mask to include or exclude specific circuit elements, [0074]; the reference discloses a backplane carrying pixels with LEDs of different colors, which have different bias-voltage and current requirements, [0053, 56], and more than one type of emissive circuit present on the same backplane, [0032]; plates whose emissive devices require different peak currents are accordingly connected to different numbers of pixel drive circuits, [0074]).
Regarding Claim 7, Li-307 teaches the device of claim 1, wherein the device comprises a plurality of LEDs, and each area of the multiple LED pixels areas corresponds to an LED of the plurality of LEDs (an array of emissive devices such as LEDs affixed to the backplane; [0023, 32]; the emissive device mounted to each conductive mounting plate, [0073-74]), and each area of the multiple LED pixels areas corresponds to an LED of the plurality of LEDs (each conductive mounting plate is a single mounting pad carrying an emissive element affixed to it, [0023]; each of plates 391-394 is the mounting plate for one emissive device such as an LED, [0073]; FIGS. 3B, 3C).
Regarding Claim 15, Li-307 teaches a device (SLM 100 with pixel drive circuit array 101 and the emissive devices affixed to the backplane; FIG. 1A; [0023, 29]) comprising:
a complementary metal-oxide semiconductor (CMOS) backplane (CMOS SRAM latch of n-channel FETs 258-261 and p-channel FETs 262, 263, storage element 250; FIG. 2B; [0047], [0049]; memory cell 500 of p-channel and n-channel FETs; FIG. 2D; [0063]) comprising multiple light emitting diode (LED) pixels areas (conductive mounting plates 391-394; FIG. 3B; [0073]; the plurality of 5x5 plate outlines 381a-381e / 382a-382e; FIG. 3C; [0077]);
a plurality of pixel drivers (130, in 4x4 blocks such as layout 360; FIGS. 1B, 3A, 3B; [0032], [0072], [0073]) inside the CMOS backplane, each pixel driver of the plurality of pixel drivers being coupled to a ground ( every pixel drive circuit comprises memory cell 500, [0061], whose n-channel FETs 507 and 509 are connected to VSS (ground) over conductor 512, FIG. 2D, [0063]; further, bias FET source to VSS over conductor 333, FIG. 2C, [0053], and over conductor 533, FIG. 20, [0066]; VSS is ground, [0092, 96]),
wherein the one or more pixel drivers are configured into one or more groups (a plurality of emissive element drivers is mated to a single mounting pad so that their currents sum, [0023]; the drive circuits under each conductive mounting plate are connected in parallel through the via mask and their peak currents sum, [0073-75, 102]) corresponding to the multiple LED pixels areas (one group per conductive mounting plate, each plate being a single mounting pad carrying one affixed emissive element; [0023, 73]; FIGS. 3B, 3C).
Regarding Claim 16, Li-307 teaches the device of claim 15, wherein a hybrid configuration of the device (the grouping is set by two different kinds of means used together: a via-mask and metal-layer change that physically includes or excludes pixel drive circuits from connection to the conductive mounting plate, [0074, 75], and the loading of off-state data into the memory cell of a pixel drive circuit that is physically connected to the plate, which excludes that circuit electrically; "a pixel drive circuit that is connected to a conductive mounting plate may be excluded by loading off state data to its memory cell," [0074]) configures the one or more pixel drivers into the one or more groups (the resulting set of connected, active pixel drive circuits under each plate is the group whose summed current drives that plate's emissive element; [0074, 0075]) corresponding to the multiple LED pixels areas (one such group per conductive mounting plate; [0023, 73]; FIGS. 3B, 3C).
Regarding Claim 17, Li-307 teaches the device of claim 16, wherein the hybrid configuration comprises one or more metal interconnect layers of the CMOS backplane (the top metal layer into which the conductive mounting plate is designed, the via layer, and the additional metal layer that is changed to set which pixel driver circuits are active; [0075]).
Regarding Claim 19, Li-307 teaches the device of claim 15, wherein the device comprises a plurality of LEDs (an array of emissive devices such as LEDs affixed to the backplane; [0023, 32]), and each area of the multiple LED pixels areas corresponds to an LED of the plurality of LEDs (one emissive element affixed to each single mounting pad, [0023]; one emissive device per conductive mounting plate 391-394, [0073]; FIGS. 3B, 3C).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Li-307 (US # 20200098307) in view of Park-425 (US # 20150048425).
Regarding Claim 2, although Li-307 discloses much of the claimed invention, it does not explicitly teach the device of claim 1, wherein the one or more metal interconnect layers comprise a full metal layer stack of the CMOS backplane configuring the one or more pixel drivers into the one or more groups.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Park-425 is in the same or analogous field, and it teaches that a CMOS integrated circuit fanned over a fixed array of transistors may be configured into the desired circuit by customizing all of its metal layers and their via layers (in a traditional gate array of a five-metal design, "all five metal layers and their via layers may be needed for customization"; see [0035]) and it teaches the stack in which such customization is carried out: substrate 201, diffusion layer 202 and gate electrode layer 203 forming the P- and N-type MOS transistors, above which contact layer 205, metal layer 211 , via layer 212, and the further interconnect layers through metal layer 261 and additional interconnect layers 270 are formed, with up to ten metal and via layers commonly used (FIG. 3; [0037]; [0002]). Park-425 states the trade-off between the alternatives: customizing every layer with a unique pattern achieves "the most optimized die size, the highest performance, and the easiest integration," at the cost of a unique mask for each layer ([0003], [0037]), whereas customizing only some metal or via layers above a fixed region reduces mask cost and manufacturing time at the expense of density, power and performance ([0004], [0007]).
A person having ordinary skill in the art would have recognized that modifying the interconnect layers of Li-307 with the full metal stack suggested by Park-425 would be obvious. Specifically, the modification suggested by Park-425 would be to employ a device of claim 1, wherein the one or more metal interconnect layers comprise a full metal layer stack of the CMOS backplane configuring the one or more pixel drivers into the one or more groups. Park-425 teaches that customizing all of the interconnect layers is the recognized way to obtain the most optimized layout and the highest performance for a given circuit ([0003, 35-37]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Li-307 (US # 20200098307).
Regarding Claim 6, although Li-307 as applied to claim 1 discloses much of the claimed invention, it does not explicitly teach the device of claim 1, wherein a group of the one or more groups comprise four (4) pixel drivers of the plurality of pixel drivers.
Nonetheless Li-307 itself teaches that the number of pixel drive circuits connected to a mounting plate is not fixed: "the actual number of pixel drive circuits that need to be connected to conductive mounting plate 391 will depend on the peak current required to drive the emissive device at the desired intensity," and the count is changed simply by changing the via mask to include or exclude specific circuit elements ([0074]); it teaches pixel-drive-circuit blocks of 3x3, 4 x4, 5x5, 4x8 and 4x6 ([0072, 99]) and conductive mounting plates whose 5x5 footprint spans elements of four different 4x4 blocks ([0073]), each plate lying over a number of underlying blocks ([0078]), so that the number of drive circuits under a plate is decoupled from the block size; and it teaches adapting the same backplane to emissive devices of differing sizes and pitches ([0002, 4, 7, 75]). The number of pixel drivers per group is therefore a result-effective variable recognized by Li-307 as controlling the peak current delivered to the emissive device. A person having ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to connect four pixel drive circuits to a conductive mounting plate for an emissive device of smaller size or lower peak-current requirement, because it is not inventive to discover the optimum or workable number of a variable the reference itself identifies as governing the result (MPEP 2144.0S(II)(B)), and Li-307 supplies both the mechanism (via-mask selection, [0074]) and the reason (matching the summed drive current to the emissive element's required intensity, [0074]) for doing so.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899
Prosecution Insights