DETAILED ACTION
This action is responsive to the application filed November 30, 2023. Claims 1 – 20 are pending. Claims 1, 10, and 17 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-5, 9, 10, 12-14, 17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 20210027849).
Regarding independent claim 1, Park discloses a system (Fig. 9: 30000) comprising:
a memory device (Fig. 9: 1100); and
a processing device (Fig. 1: 100, also see para. 19), operatively coupled with the memory device (Fig. 9: 1100), to perform operations comprising:
receiving a request to perform a program operation (Fig. 9: 3100, see para. 97) on a set of cells in a block (Fig. 1: BLK) of the memory device (Fig. 1: 100), the block comprising a plurality of decks (Fig. 3: Page, also see figure 8);
determining whether at least one second deck (Fig. 3: Page, see para. 78-79) of the plurality of decks (Fig. 3: Page, also see figure 8) is physically disposed below at least one first deck (Fig. 3: Page) of the plurality of decks (Fig. 3: Page, also see figure 8), wherein the at least one first deck (Fig. 3: Page) satisfies a criterion (Fig. 7: S720, see para. 78-79, criterion being programmed late or programmed early) pertaining to a functionality of a deck (Fig. 3: Page), and the at least one second deck (Fig. 3: Page, see para. 78-79) of the plurality of decks (Fig. 3: Page, also see figure 8) does not satisfy the criterion (Fig. 7: S720, see para. 78-79, criterion being programmed late or programmed early); and
responsive to determining that the at least one second deck (Fig. 3: Page, see para. 78-79) is physically disposed below the at least one first deck (Fig. 3: Page), performing the program operation (Fig. 9: 3100, see para. 97) on the set of cells in the block (Fig. 1: BLK) using a first bitline voltage (Fig. 8: BL Bias [V]) applied during a program verify phase (see para. 46), wherein the first bitline voltage (Fig. 8: BL Bias [V]) is higher than a default program verify bitline voltage (Fig. 8: BL Bias [V], see para. 46).
Regarding claim 3, Park discloses wherein the processing device (Fig. 1: 100, also see para. 19) is to perform operations further comprising:
responsive to determining that the at least one second deck (Fig. 3: Page, see para. 78-79) is not physically disposed below the at least one first deck (Fig. 3: Page), performing the program operation (Fig. 9: 3100, see para. 97) on the set of cells in the block (Fig. 1: BLK) using the default program verify bitline voltage (Fig. 8: BL Bias [V], see para. 46).
Regarding claim 4, Park discloses wherein the processing device (Fig. 1: 100, also see para. 19) is to perform operations further comprising:
determining whether the at least one first deck (Fig. 3: Page) satisfies the criterion (Fig. 7: S720, see para. 78-79, earlier programmed in the sequential page program order) and the at least one second deck (Fig. 3: Page, see para. 78-79) does not satisfy the criterion (Fig. 7: S720, see para. 78-79, later programmed meaning it is not earlier programmed in the sequential page program order).
Regarding claim 5, Park discloses wherein the processing device (Fig. 1: 100, also see para. 19) is to perform operations further comprising:
responsive to determining that it is not that the at least one first deck (Fig. 3: Page) satisfies the criterion (Fig. 7: S720, see para. 78-79, earlier programmed in the sequential page program order) and the at least one second deck (Fig. 3: Page, see para. 78-79) does not satisfy the criterion (Fig. 7: S720, see para. 78-79, earlier programmed in the sequential page program order), performing the program operation (Fig. 9: 3100, see para. 97) on the set of cells in the block (Fig. 1: BLK) using the default program verify bitline voltage (Fig. 8: BL Bias [V], see para. 46).
Regarding claim 9, Park discloses wherein the processing device (Fig. 1: 100, also see para. 19) is to perform operations further comprising:
identifying the block (Fig. 1: BLK) based on an address of the set of cells (Fig. 3: F1-F8).
Regarding independent claim 10, Park discloses a method (see para. 11) comprising:
receiving, by a processing device (Fig. 1: 100, also see para. 19), a request to perform a program operation (Fig. 9: 3100, see para. 97) on a set of cells in a block (Fig. 1: BLK) of a memory device (Fig. 1: 100), the block (Fig. 1: BLK) comprising a plurality of decks (Fig. 3: Page, also see figure 8);
determining whether at least one second deck (Fig. 3: Page, see para. 78-79) of the plurality of decks (Fig. 3: Page, also see figure 8) is physically disposed below at least one first deck (Fig. 3: Page) of the plurality of decks (Fig. 3: Page, also see figure 8), wherein the at least one first deck (Fig. 3: Page) satisfies a criterion (Fig. 7: S720, see para. 78-79, earlier programmed in the sequential page program order) pertaining to a functionality of a deck (Fig. 3: Page), and
the at least one second deck (Fig. 3: Page, see para. 78-79) of the plurality of decks (Fig. 3: Page, also see figure 8) does not satisfy the criterion (Fig. 7: S720, see para. 78-79, earlier programmed in the sequential page program order and
responsive to determining that the at least one second deck (Fig. 3: Page, see para. 78-79) is physically disposed below the at least one first deck (Fig. 3: Page), performing the program operation (Fig. 9: 3100, see para. 97) on the set of cells in the block (Fig. 1: BLK) using a first bitline voltage (Fig. 8: BL Bias [V], showing a first bitline voltage of 0V or 0.2V) applied during a program verify phase (see para. 46), wherein the first bitline voltage (Fig. 8: BL Bias [V], showing a first bitline voltage of 0V or 0.2V) is higher than a default program verify bitline voltage (Fig. 8: BL Bias [V], see para. 46).
Regarding claim 12, Park discloses wherein the processing device (Fig. 1: 100, also see para. 19) is to perform operations further comprising:
responsive to determining that the at least one second deck (Fig. 3: Page, see para. 78-79) is not physically disposed below the at least one first deck (Fig. 3: Page), performing the program operation (Fig. 9: 3100, see para. 97) on the set of cells in the block (Fig. 1: BLK) using the default program verify bitline voltage (Fig. 8: BL Bias [V], see para. 46).
Regarding claim 13, Park discloses further comprising:
determining whether the at least one first deck (Fig. 3: Page) satisfies the criterion (Fig. 7: S720, see para. 78-79) and the at least one second deck (Fig. 3: Page, see para. 78-79) does not satisfy the criterion (Fig. 7: S720, see para. 78-79).
Regarding claim 14, Park discloses further comprising:
responsive to determining that it is not that the at least one first deck (Fig. 3: Page) satisfies the criterion (Fig. 7: S720, see para. 78-79) and the at least one second deck (Fig. 3: Page, see para. 78-79) does not satisfy the criterion (Fig. 7: S720, see para. 78-79), performing the program operation (Fig. 9: 3100, see para. 97) on the set of cells in the block (Fig. 1: BLK) using the default program verify bitline voltage (Fig. 8: BL Bias [V], see para. 46).
Regarding independent claim 17, Park discloses a non-transitory computer-readable storage medium (Fig. 6: 141) comprising instructions that, when executed by a processing device (Fig. 1: 100, also see para. 19), cause the processing device (Fig. 1: 100, also see para. 19) to perform operations comprising:
receiving a request to perform a program operation (Fig. 9: 3100, see para. 97) on a set of cells in a block (Fig. 1: BLK) of a memory device (Fig. 1: 100), the block (Fig. 1: BLK) comprising a plurality of decks (Fig. 3: Page, also see figure 8);
determining whether at least one second deck (Fig. 3: Page, see para. 78-79) of the plurality of decks (Fig. 3: Page, also see figure 8) is physically disposed below at least one first deck (Fig. 3: Page) of the plurality of decks (Fig. 3: Page, also see figure 8), wherein the at least one first deck (Fig. 3: Page) satisfies a criterion (Fig. 7: S720, see para. 78-79, criterion being programmed late or programmed early) pertaining to a functionality of a deck (Fig. 3: Page), and the at least one second deck (Fig. 3: Page, see para. 78-79) of the plurality of decks (Fig. 3: Page, also see figure 8) does not satisfy the criterion (Fig. 7: S720, see para. 78-79, criterion being programmed late or programmed early); and
responsive to determining that the at least one second deck (Fig. 3: Page, see para. 78-79) is physically disposed below the at least one first deck (Fig. 3: Page), performing the program operation (Fig. 9: 3100, see para. 97) on the set of cells in the block (Fig. 1: BLK) using a first bitline voltage (Fig. 8: BL Bias [V], showing a first bitline voltage of 0V or 0.2V) applied during a program verify phase (Fig. 8, showing 1V having a phase of voltages), wherein the first bitline voltage (Fig. 8: BL Bias [V], showing a first bitline voltage of 0V or 0.2V) is higher than a default program verify bitline voltage (Fig. 8: BL Bias [V], see para. 46).
Regarding claim 20, Park discloses wherein the processing device (Fig. 1: 100, also see para. 19) is to perform operations further comprising:
responsive to determining that the at least one second deck (Fig. 3: Page, see para. 78-79) is not physically disposed below the at least one first deck (Fig. 3: Page), performing the program operation (Fig. 9: 3100, see para. 46) on the set of cells in the block (Fig. 1: BLK) using the default program verify bitline voltage (Fig. 8: BL Bias [V], see para. 46).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 7, 15, 16, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20210027849) in view of Mokhlesi et al. (US 9911488).
Regarding claim 6, Park teaches the limitations of claim 1.
Park further teaches wherein the first bitline voltage (Fig. 8: BL Bias [V]), but does not teach the “…bitline voltage is determined through a characterization measurement on the set of cells associated with the block”.
However, Mokhlesi teaches the first bitline voltage is determined through a characterization measurement (Fig. 11: showing multiple measured characterizations) on the set of cells (Note, Fig. 25, shows sets or groups of cells) associated with the block (Fig. 1A: BLK).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park’s memory device system with Mokhlesi’s example of characterization measurement of the memory cells for the purpose of properly storing data in the memory.
Furthermore, the best representation of the applicant’s limitation is shown in figure 11.
Regarding claim 7, Park teaches the limitations of claim 1.
Park further teaches wherein the first bitline voltage (Fig. 8: BL Bias [V]), but does not disclose “the bitline voltage is determined according to a preset table, wherein the preset table comprises a plurality of records, wherein each record of the plurality of records comprises a value of the first bitline voltage corresponding to at least one of: a cell type, a level, or a numbered wordline”.
However, Mokhlesi teaches the first bitline voltage is determined according to a preset table (Fig. 11), wherein the preset table comprises a plurality of records (Fig. 11, showing a plurality of records), wherein each record of the plurality of records (Fig. 11, showing a plurality of records) comprises a value of the first bitline voltage (Fig. 11, shows the bit line voltage in the table) corresponding to at least one of:
a cell type, a level, or a numbered wordline (Fig. 11, shows the bitline voltages corresponding to the data states shown in figure 8).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park’s memory device system with Mokhlesi’s characterization measurement table for the purpose of properly storing data in the memory.
Regarding claim 15, Park teaches the limitations of claim 10.
Park further teaches wherein the first bitline voltage (Fig. 8: BL Bias [V]); but Park does not teach “…the bitline voltage is determined through a characterization measurement on the set of cells associated with the block”.
However, Mokhlesi teaches the first bitline voltage is determined through a characterization measurement (Fig. 11: showing multiple measured characterizations) on the set of cells (Note, Fig. 25, shows sets or groups of cells) associated with the block (Fig. 1A: BLK).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park’s memory device system with Mokhlesi’s example of characterization measurement of the memory cells for the purpose of properly storing data in the memory.
Furthermore, the best representation of the applicant’s limitation is shown in figure 11.
Regarding claim 16, Park teaches the limitations of claim 10.
Park further teaches wherein the first bitline voltage (Fig. 8: BL Bias [V]), but does not disclose “…the bitline voltage is determined according to a preset table, wherein the preset table comprises a plurality of records, wherein each record of the plurality of records comprises a value of the first bitline voltage corresponding to at least one of: a cell type, a level, or a numbered wordline”.
However, Mokhlesi teaches the first bitline voltage is determined according to a preset table (Fig. 11), wherein the preset table comprises a plurality of records (Fig. 11, showing a plurality of records), wherein each record of the plurality of records (Fig. 11, showing a plurality of records) comprises a value of the first bitline voltage (Fig. 11, shows the bit line voltage in the table) corresponding to at least one of:
a cell type, a level, or a numbered wordline (Fig. 11, shows the bitline voltages corresponding to the data states shown in figure 8).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park’s memory device system with Mokhlesi’s characterization measurement table for the purpose of properly storing data in the memory.
Regarding claim 18, Park teaches the limitations of claim 17.
Park further teaches wherein the first bitline voltage (Fig. 8: BL Bias [V]), but Park does not teach “…the bitline voltage is determined through a characterization measurement on the set of cells associated with the block”.
However, Mokhlesi teaches the first bitline voltage is determined through a characterization measurement (Fig. 11: showing multiple measured characterizations) on the set of cells (Note, Fig. 25, shows sets or groups of cells) associated with the block (Fig. 1A: BLK).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park’s memory device system with Mokhlesi’s example of characterization measurement of the memory cells for the purpose of properly storing data in the memory.
Furthermore, the best representation of the applicant’s limitation is shown in figure 11.
Regarding claim 19, Park teaches the limitations of claim 17.
Park further teaches wherein the first bitline voltage (Fig. 8: BL Bias [V]), but Park does not teach “…the bitline voltage is determined according to a preset table, wherein the preset table comprises a plurality of records, wherein each record of the plurality of records comprises a value of the first bitline voltage corresponding to at least one of: a cell type, a level, or a numbered wordline”.
However, Mokhlesi teaches the first bitline voltage is determined according to a preset table (Fig. 11), wherein the preset table comprises a plurality of records (Fig. 11, showing a plurality of records), wherein each record of the plurality of records (Fig. 11, showing a plurality of records) comprises a value of the first bitline voltage (Fig. 11, shows the bit line voltage in the table) corresponding to at least one of:
a cell type, a level, or a numbered wordline (Fig. 11, shows the bitline voltages corresponding to the data states shown in figure 8).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park’s memory device system with Mokhlesi’s characterization measurement table for the purpose of properly storing data in the memory.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20210027849) in view of Lee et al. (US 20200082891).
Regarding claim 8, Park teaches the limitations of claim 1.
Park further teaches wherein determining whether the at least one second deck (Fig. 3: Page, see para. 78-79) is physically disposed below the at least one first deck (Fig. 3: Page) further comprises:
Park does not teach, “determining whether the block is associated with an indicator according to a data structure.
However, Lee teaches:
determining whether the block (Fig. 10: BLOCK) is associated with an indicator according to a data structure (Fig. 10, showing the data structure as a table).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park’s memory device with Lee’s indicator and data structure for the purpose of conveying crucial information about the block’s condition within the memory device.
Claim 2 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20210027849) in view of Fastow et al. (US 20190043591; "Fastow").
Park teaches the limitations of claims 1 and 10, respectively.
Park is silent to the specific provision of “performing a read operation on the set of cells in the block using a default read bitline voltage.”
However, Fastow teaches performing a read operation on the set of cells in the block using a default read bitline voltage (Fig. 8. See also para. 66; "FIG. 8 illustrates a flow and timing for a deck read and verify operation in accordance with various embodiments. It is here noted that, in embodiments, a block by deck read/verify operation may use the same flow and timing as used in a standard read/verify operation).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s program operation on a memory device (with its PV bitline voltage adjustment) by performing the subsequent read using the standard/default read bitline voltage taught by Fastow. Doing so would maintain compatibility with existing read schemes while avoiding complicating read-level optimization in multi-deck arrays where some decks may be erased.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Namala et al. (US 20220199189) – Half-good blocks in multi-deck 3D NAND devices in which defective decks are disabled while functional decks are operated on based on conditions.
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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