DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species IA (Fig. 3; Claims 1-4, 6-12) in the reply filed on 04/27/2026 is acknowledged.
Claim 5, 13-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention and/or Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/27/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 9-12 is/are rejected under 35 U.S.C. 102(A1) as being anticipated by Oh (US 2021/0377472 A1).
Regarding Claim 1, Oh (Fig. 2-6) discloses a pixel, comprising:
a substrate (“epitaxial silicon layer (EPI)”) configured to generate one or more carriers in response to an incident light beam (“ a photoelectron generation region of a pixel, which refers to a region in which electrons are generated from light incident on the pixel. “) (“generate photoelectrons within a photoelectron generation region 304, which may comprise an EPI layer”); [0015, 0027],
a first vertical gate (PG_A) and a second vertical gate (PG_B) disposed inside the substrate, wherein
the first and second vertical gates are configured to direct the one or more carriers to a first sensing node (node at PG_A) or a second sensing node (node at PG_B); (“Photogate 308a (PG_A) and photogate 308b (PG_B) are spaced apart with the photoelectron generation region 304 therebetween. Incident photons may generate photoelectrons in the photoelectron generation region between PG_A and PG_B. Generated photoelectrons may flow to either of the photogates 308a, 308b depending on the applied electric field 310. Electric charge accumulated at PG_A 308a or PG_B 308b is transferred to the associated storage gate 312a (SG_A) or storage gate 312b (SG_B), respectively.”) [0027]
a first vertical gate input (input to PG_A) electronically coupled to the first vertical gate and configured to receive a first gate control signal (input signal to PG_A); and
a second vertical gate input (input to PG_B) electronically coupled to the second vertical gate and configured to receive a second gate control signal (input signal to PG_A), wherein
(See control signals in Fig. 6, “vertical photogates PG_A and PG_B are modulated out of phase with each other”) [0036]
the first and second vertical gates are configured to direct the one or more carriers to the first sensing node or the second sensing node using the first and second gate control signals. (“depending upon the relative bias between the photogates, photoelectrons are directed to one of vertical photogates PG_A and PG_B during each modulation cycle”) [0036]
Regarding Claim 2, Oh (Fig. 2-6) discloses the pixel of claim 1, wherein:
the first vertical gate is configured to be activated using the first gate control signal and direct the one or more carriers to the first sensing node when activated; and
the second vertical gate is configured to be activated using the second gate control signal and direct the one or more carriers to the second sensing node when activated. (“depending upon the relative bias between the photogates, photoelectrons are directed to one of vertical photogates PG_A and PG_B during each modulation cycle”) [0036]
Regarding Claim 3, Oh (Fig. 2-6) discloses the pixel of claim 2, wherein:
the first vertical gate is deactivated when the second vertical gate is activated; and the second vertical gate is deactivated when the first vertical gate is activated. (“vertical photogates PG_A and PG_B are modulated out of phase with each other”) [0036]
Regarding Claim 4, Oh (Fig. 2-6) discloses the pixel of claim 3, wherein the first and second gate control signals include periodic waveforms and are complements of each other. (Fig. 6) (“vertical photogates PG_A and PG_B are modulated out of phase with each other”) [0036].
Regarding Claim 9, Oh (Fig. 2-6) discloses the pixel comprising:
a substrate (“epitaxial silicon layer (EPI)”) configured to generate one or more carriers in response to an incident light beam (“ a photoelectron generation region of a pixel, which refers to a region in which electrons are generated from light incident on the pixel. “) (“generate photoelectrons within a photoelectron generation region 304, which may comprise an EPI layer”); [0015, 0027],
a first vertical gate (PG_A) and a second vertical gate (PG_B) disposed inside the substrate, wherein
the first and second vertical gates are configured to direct the one or more carriers to a first capacitor (FD_A) or a second capacitor (FD_B);
a first vertical gate input (input to PG_A)electronically coupled to the first vertical gate and configured to receive a first gate control signal (input signal to PG_A); and
a second vertical gate input (input to PG_B) electronically coupled to the second vertical gate and configured to receive a second gate control signal (input signal to PG_B), (See control signals in Fig. 6, “vertical photogates PG_A and PG_B are modulated out of phase with each other”) [0036]
wherein
the first and second vertical gates are configured to direct the one or more carriers to the first capacitor or the second capacitor using the first and second gate control signals. (“charge stored on the storage gates 204a, 204b is transferred to a floating diffusion (FD) capacitor 206a, 206b for a corresponding pixel tap (FD_A and FD_B) via operation of a transfer gate 208a, 208b for each tap. Charge on each FD capacitor 206a, 206b is read as a voltage across a source follower 210a, 210b, thereby providing a signal for that pixel tap.”) [0026]
Regarding Claim 10, Oh (Fig. 2-6) discloses the pixel of claim 9, wherein:
the first vertical gate is configured to be activated using the first gate control signal and direct the one or more carriers to the first capacitor when activated; and
the second vertical gate is configured to be activated using the second gate control signal and direct the one or more carriers to the second capacitor when activated.
(“depending upon the relative bias between the photogates, photoelectrons are directed to one of vertical photogates PG_A and PG_B during each modulation cycle”) [0036] (“charge stored on the storage gates 204a, 204b is transferred to a floating diffusion (FD) capacitor 206a, 206b for a corresponding pixel tap (FD_A and FD_B) via operation of a transfer gate 208a, 208b for each tap. Charge on each FD capacitor 206a, 206b is read as a voltage across a source follower 210a, 210b, thereby providing a signal for that pixel tap.”) [0026]
Regarding Claim 11, Oh (Fig. 2-6) discloses the pixel of claim 10, wherein:
the first vertical gate is deactivated when the second vertical gate is activated; and the second vertical gate is deactivated when the first vertical gate is activated. (“vertical photogates PG_A and PG_B are modulated out of phase with each other”) [0036]
Regarding Claim 12, Oh (Fig. 2-6) discloses the pixel of claim 11, wherein the first and second gate control signals include periodic waveforms and are complements of each other. (Fig. 6) (“vertical photogates PG_A and PG_B are modulated out of phase with each other”) [0036]
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US 2021/0377472 A1) in view of Roy (US 2019/0237499 A1).
Regarding Claim 6, Oh (Fig. 2-6) discloses the pixel of claim 1, further comprising:
a first deep insulation trench on a first side of the substrate (DTI left); and
a second deep insulation trench on a second side of the substrate (DTI right), wherein
Oh does not explicitly disclose the first and second deep insulation trenches are configured to create a pinning potential at the substrate to deplete the substrate.
Roy discloses a first and second deep insulation trenches (125, 123 left and right) are configured to create a pinning potential at a substrate to deplete a substrate. (“capacitive deep trench isolation (CDTI) type, which may be biased to collect and store photo-generated charges in the depletion region of the photosensitive cells of the image sensor.“ ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the pixel in Oh in view of Choi such that the first and second deep insulation trenches are configured to create a pinning potential at the substrate to deplete the substrate in order have capacitive deep trench isolation (CDTI) type, which may be biased to collect and store photo-generated charges in the depletion region of the photosensitive cells of the image sensor. [0044].
Claim(s) 7, 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US 2021/0377472 A1) in view of Choi et al. (US 2021/0025993 A1)
Regarding Claim 7, Oh (Fig. 2-6) discloses the pixel of claim 1, wherein
the first vertical gate and the second vertical gate are configured to be activated alternatively using the first gate control signal and the second gate control signal (“vertical photogates PG_A and PG_B are modulated out of phase with each other”) [0036], wherein
the first gate control signal is a complement of the second gate control signal at a given time, (“vertical photogates PG_A and PG_B are modulated out of phase with each other”) [0036],
Oh does not explicitly disclose the pixel is configured to determine an indirect time of flight (iToF).
Choi (Fig. 4, 5) discloses a pixel is configured to determine an indirect time of flight (iToF). [0024, 0028]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the pixel in Oh in view of Choi such that the pixel is configured to determine an indirect time of flight (iToF) in order have a 3D camera that calculates image depth information of a scene to be imagedbased on indirect time of flight (iTOF) measurements with image sensor [0024].
Regarding Claim 8, Oh (Fig. 2-6) discloses the pixel of claim 1, wherein
Oh does not explicitly disclose the first vertical gate and the second vertical gate are configured to be deactivated simultaneously for a first period of time and the first vertical gate or the second vertical gate to be activated for a second period of time using the first and second gate control signals, and wherein the pixel is configured to provide two-dimensional imaging.
Choi (Fig. 4, 5) discloses a first vertical gate (432A) and the second vertical gate (432B) are configured to be deactivated simultaneously for a first period of time and the first vertical gate or the second vertical gate to be activated for a second period of time using a first (TX1) and second (TX2) gate control signals (See precharge reset in Fig. 5), and wherein a pixel is configured to provide two-dimensional imaging. [0024]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the pixel in Oh in view of Choi such that the first vertical gate and the second vertical gate are configured to be deactivated simultaneously for a first period of time and the first vertical gate or the second vertical gate to be activated for a second period of time using the first and second gate control signals, and wherein the pixel is configured to provide two-dimensional imaging in order to utilized sensing system to capture 2D images [0024] and have the pixel operating in an a 2D intensity mode begin with a precharge reset period, during which time the elements in the pixel are precharged or reset to initial values. [0083]
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jin at al. (US 2023/0268358 A1) discloses a first and second deep insulation trenches (PIS) (Fig. 5, 7)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m.
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/DMITRIY YEMELYANOV/Examiner, Art Unit 2891
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