DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zitouni et al. (US 2004/0075144).
Regarding claim 1, Zitouni discloses a CMOS circuit, comprising:
a substrate of a first conductivity type (p-type, 14, fig. 3 and paragraph 0034) with an emitter of a second conductivity type (n-type, 10, fig. 3 and paragraph 0034) formed on a surface of the substrate (fig. 3);
a well tie of the first conductivity type (24, fig. 3 and paragraph 0027) formed between the emitter (10, fig. 3) and at least one trigger region (28, fig. 3) and comprising a strip of heavier doping for coupling to a supply-voltage reference (fig. 3 and paragraph 0027); and a well-tie extension comprising a deep lateral implant of the first conductivity
type that overlaps at least a portion of the well tie (22, fig. 3 and paragraphs 0027-0029).
Regarding claim 2, Zitouni further discloses a deep implant of the first conductivity type formed at a lower portion of a body of the substrate that
overlaps at least a portion of a lower extent of the deep lateral implant (PBL, 22, lower half, fig.3 and paragraphs 0027-0029).
Regarding claim 3, Zitouni further discloses wherein the deep lateral implant of the first conductivity type comprises a degenerate level of doping (PBL, fig. 3 and paragraphs 0026-0028, 0036).
Regarding claim 4, Zitouni further discloses wherein the deep lateral implant of the first conductivity type (PBL, 22, fig. 3 and paragraphs 0026-0028, 0036) comprises a degenerate level of doping that encompasses the well tie (24, fig. 3) and that forms a guard-ring (32, fig. 3 and paragraphs 0026-0029) that surrounds the emitter.
Regarding claim 5, Zitouni further discloses a deep implant of the first
conductivity type formed at a lower portion of a body of the substrate that
overlaps at least a portion of a lower extent of the deep lateral implant (PBL, 22, lower half, fig.3 and paragraphs 0027-0029).
Regarding claim 6, Zitouni further discloses a first guard-ring of the second
conductivity type surrounding the emitter and the well tie, wherein the guard-ring
comprises a deep well portion with lighter doping extending within a body of the
substrate and a shallow implant profile formed within the well portion with
heavier doping for coupling to a supply voltage (6, fig. 3 and paragraphs 0025-0034).
Regarding claim 7, Zitouni further discloses a deep implant of the first conductivity type formed at a lower portion of the body of the substrate (PBL, 22, lower half, fig.3 and paragraphs 0027-0029); and
wherein the deep lateral implant of the first conductivity type encompasses the
well tie and forms a second guard-ring (32, fig. 3 and paragraph 0029) surrounding the emitter within the first guard-ring (6, fig. 3 and paragraph 0029) that overlaps at least a portion of an upper extent of the deep implant.
Regarding claim 8, Zitouni further discloses wherein the deep lateral implant of the first conductivity type comprises a first deep lateral implant of the first conductivity type with a degenerate level of doping that encompasses the well tie and that forms a second guard-ring that surrounds the emitter within the first guard-ring (32, fig. 3 and paragraph 0029); and
a second deep lateral implant of the first conductivity type with a degenerate level
of doping at least partially surrounds without touching the first guard-ring
and formed between the first guard-ring and at least one latch-up trigger
location (fig. 3).
Regarding claim 9, Zitouni further discloses a deep implant of the first conductivity type formed at a lower portion of the body of the substrate that
overlaps at least a portion of a lower extent of the first deep lateral implant and
the second deep lateral implant (PBL, 22, lower half, fig.3 and paragraphs 0027-0029).
Regarding claim 10, Zitouni further discloses wherein the well tie and well-tie extension (24, 22, fig. 3 and paragraphs 0027-0029) collectively comprise a guard-ring implant of the first conductivity type with heavier doping and with a deep profile surrounding without touching the emitter (fig. 3).
Regarding claim 11, Zitouni discloses a method of providing latch-up immunity for a CMOS circuit, the CMOS circuit comprising a substrate of a first conductivity type (p-type, 14, fig. 3 and paragraph 0034) and an emitter of a second conductivity type (n-type, 10, fig. 3 and paragraph 0034) formed on a surface of the substrate, the method comprising:
providing a well tie of the first conductivity type (24, fig. 3 and paragraph 0027) between the emitter (10, fig. 3) and at least one trigger region (28, fig. 3) and comprising a strip of heavier doping for coupling to a supply-voltage reference (fig. 3 and paragraph 0027); and extending the well tie with a deep lateral implant of the first conductivity type that
overlaps at least a portion of the well tie (22, fig. 3 and paragraphs 0027-0029).
Regarding claim 12, Zitouni further discloses comprising providing a deep implant of the first conductivity type at a lower portion of a body of the substrate that overlaps at least a portion of a lower extent of the deep lateral implant (PBL, 22, lower half, fig.3 and paragraphs 0027-0029).
Regarding claim 13, Zitouni further discloses wherein the extending the well tie comprises extending the well tie with the deep lateral implant of the first conductivity type with a degenerate level of doping (PBL, fig. 3 and paragraphs 0026-0028, 0036).
Regarding claim 14, Zitouni further discloses wherein the extending the well tie comprises extending the well tie with the deep lateral implant of the first conductivity type with a degenerate level of doping (PBL, fig. 3 and paragraphs 0026-0028, 0036) that encompasses the well tie and that forms a guard-ring that surrounds without touching the emitter (32, fig. 3 and paragraph 0029).
Regarding claim 15, Zitouni further discloses providing a deep implant of the first conductivity type at a lower portion of a body of the substrate that overlaps at
least a portion of a lower extent of the deep lateral implant (PBL, 22, lower half, fig.3 and paragraphs 0027-0029).
Regarding claim 16, Zitouni further discloses providing a first guard-ring of the second conductivity type surrounding the emitter and the well tie, wherein the
guard-ring comprises a deep well portion with lighter doping extending within a
body of the substrate and a shallow implant profile formed within the well portion
with heavier doping for coupling to a supply voltage (6, fig. 3 and paragraphs 0025-0034).
Regarding claim 17, Zitouni further discloses providing a deep implant of the first conductivity type at a lower portion of the body of the substrate; and
wherein the extending the well tie comprises extending the well tie with the deep
lateral implant of the first conductivity type (PBL, 22, lower half, fig.3 and paragraphs 0027-0029) that encompasses the well tie and forms a second guard-ring (32, fig. 3) surrounding the emitter within the first guard-ring (6, fig. 3 and paragraph 0029) and overlapping at least a portion of an upper extent of the deep implant.
Regarding claim 18, Zitouni further discloses wherein the extending the well tie comprises extending the well tie with a first deep lateral implant of the first conductivity type with a degenerate level of doping that encompasses the well tie and that forms a second guard-ring (32, fig. 3 and paragraph 0029) surrounding the emitter within the first guard-ring (6, fig. 3); and
providing a second deep lateral implant of the first conductivity type with a
degenerate level of doping at least partially surrounding without directly
interfacing the first guard-ring (PBL, 22, lower half, fig.3 and paragraphs 0027-0029) and formed between the first guard-ring and at least one latch-up trigger location (fig. 3).
Regarding claim 19, Zitouni further discloses providing a deep implant of the first conductivity type at a lower portion of the body of the substrate that overlaps at
least a portion of a lower extent of the first deep lateral implant and the second
deep lateral implant (PBL, 22, lower half, fig.3 and paragraphs 0027-0029).
Regarding claim 20, Zitouni further discloses wherein the extending the well tie comprises extending the well tie with heavier doping to form a guard-ring implant of the first conductivity type with a deep profile surrounding without touching the emitter (32, fig. 3 and paragraph 0029).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent 7777248 and US Patent Application Publication 20020164848 disclose relevant latch-up semiconductor devices.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 2/21/26