Prosecution Insights
Last updated: May 29, 2026
Application No. 18/525,060

DISPLAY UNIT, DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§103
Filed
Nov 30, 2023
Priority
Jan 12, 2022 — continuation of PCTCN2022071498
Examiner
MCCUTCHEON, COLIN RUSSELL
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Xiamen Extremely Pq Display Technology Co. Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
37 granted / 44 resolved
+16.1% vs TC avg
Strong +23% interview lift
Without
With
+23.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
6 currently pending
Career history
64
Total Applications
across all art units

Statute-Specific Performance

§103
90.0%
+50.0% vs TC avg
§102
8.3%
-31.7% vs TC avg
§112
1.7%
-38.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 44 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) was submitted on 11/30/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Objections Claims 9-10 are objected to because of the following informalities: Re Claims 9-10, both claims make reference to “the first substrate” (line 2 of Claim 9 and lines 2-3 of Claim 10), where “a first substrate” was not previously established (improper antecedent basis). For the purposes of examination, the aforementioned “the first substrate” will be interpreted as referring to “a first substrate”. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2, 4-5, and 9-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yang et al (US 20220263000 A1, hereafter Yang). Re Claim 1, Yang discloses a display unit (FIG. 5; [0054]-[0065]), comprising: a transparent patterned substrate layer (10, 23; [0054]), wherein the transparent patterned substrate layer (10, 23) defines a first via (V1; [0063]); a plurality of micro light-emitting components (21; [0054]), disposed on the transparent patterned substrate layer (10, 23; [0054]) and electrically connected to the transparent patterned substrate layer (10, 23; [0054]); a first circuit connection layer (32; [0063]), disposed in the first via (V1) of the transparent patterned substrate layer (10, 23; [0063]) and electrically connected to the transparent patterned substrate layer (10, 23; [0063]); and a first circuit bonding layer (31; [0063]), disposed on a side of the first circuit connection layer (32) facing away from the plurality of micro light-emitting components (21; [0063]) and electrically connected to the circuit connection layer (32; [0063]). Re Claim 2, Yang discloses the display unit according to Claim 1, while further disclosing the display unit comprises a packaging layer (PL2; [0065]) disposed on the transparent patterned substrate layer (10, 23; [0065]); and the packaging layer (PL2) covers the plurality of micro light-emitting components (21; [0065]). Re Claim 4, Yang discloses the display unit according to Claim 1, while further disclosing wherein the transparent patterned substrate (10, 23) layer further defines a second via (V1 in “2nd location” equivalent to FIG. 5 A-A’ portion, see FIG. Z1 below, “2nd location” hereafter referred to as 5c; [0063]); wherein the display unit further comprises: a second circuit connection layer (32 in 5c; [0063]) and a second circuit bonding layer (31 in 5c; see FIG. 1 for separated transmission lines; [0063]); wherein the second circuit connection layer (32 in 5c) is disposed in the second via (V1 in 5c) of the transparent patterned substrate layer (10, 23; [0063]) and is electrically connected to the transparent patterned substrate layer (10, 23; [0063]); and wherein the second circuit bonding layer (31 in 5c) is disposed on a side of the second circuit connection layer (32 in 5c) facing away from the plurality of micro light-emitting components (21; [0063]) and is electrically connected to the second circuit connection layer (32 in 5c; [0063]). PNG media_image1.png 159 429 media_image1.png Greyscale FIG. Z1: Annotated version of FIG. 2 of Yang Re Claim 5, Yang discloses the display unit according to Claim 4, while further disclosing wherein the second via (V1 in 5c) and the first via (V1) are disposed at two opposite ends of the transparent patterned substrate layer (10, 23; [0063]), and the plurality of micro light-emitting components (21) are disposed between the second via (V1 in 5c) and the first via (V1; [0063]). Re Claim 9, Yang discloses the display unit according to Claim 1, while further disclosing wherein the number of the first via (V1) is multiple (V1 in all equivalent locations, particularly V1 in “2nd location” equivalent to FIG. 5 A-A’ portion, see FIG. Z1, “2nd location” hereafter referred to as 5c; [0063]), and the multiple first vias (V1) are disposed around edges of the first substrate (10; [0063]). Re Claim 10, Yang discloses the display unit according to Claim 1, while further disclosing wherein the number of the first via (V1) is multiple (V1 in all equivalent locations, particularly V1 in “2nd location” equivalent to FIG. 5 A-A’ portion, see FIG. Z1, “2nd location” hereafter referred to as 5c; [0063]), and the multiple first vias (V1) are disposed at two opposite ends of the first substrate (10; [0063]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 11-12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yang, as applied to Claim 1, in view of Wang et al (US 2024/0404436 A1, hereafter Wang). Re Claim 11, Yang discloses a display device (FIG. 2; [0054]), comprising: a display substrate (“flexible printed circuit board”; [0053]); a first display unit (FIG. 5; [0054]-[0065]), wherein the first display unit is the display unit according to claim 1, and the first display unit is disposed on the side of the display substrate (“flexible printed circuit board”, side with first circuit bonding layer 31; [0063]). Yang does not explicitly disclose: a first bonding pad, disposed on a side of the display substrate (“flexible printed circuit board”); wherein the first bonding pad is disposed corresponding to the first circuit bonding layer (31) of the first display unit and is electrically connected to the first circuit bonding layer (31) of the first display unit. However, Wang teaches a display device (FIG. 2, with reference to FIG. 3; [0067]-[0087]), comprising: a first bonding pad (35; [0069]), disposed on a side of the display substrate (B2 housing layer, driving chip; [0067]-[0069], [0078]); wherein the first bonding pad (35) is disposed corresponding to the first circuit bonding layer (221; [0102]) of the first display unit ([0102]) and is electrically connected to the first circuit bonding layer (221; [0102]) of the first display unit ([0102]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 1 with the limitations taught by Wang to utilize bonding pads (Wang: 35) for connection of the transmission lines (Yang: 31) to the driving chip as taught by Wang ([0078]). Re Claim 12, Yang and Wang teach the display device according to Claim 11, while Yang further teaches wherein the transparent patterned substrate layer (10, 23) of the first display unit further defines a second via (V1 in “2nd location” equivalent to FIG. 5 A-A’ portion, see FIG. Z1, “2nd location” hereafter referred to as 5c; [0063]), the second via (V1 in 5c) and the first via (V1) are disposed on two opposite ends of the transparent patterned substrate layer (10, 23; [0063]), and the plurality of micro light-emitting components (21) are disposed between the second via (V1 in 5c) and the first via (V1; [0063]); wherein the first display unit further comprises: a second circuit connection layer (32 in 5c; [0063]) and a second circuit bonding layer (31 in 5c; see FIG. 1 for separated transmission lines; [0063]); the second circuit connection layer (32 in 5c) is disposed in the second via (V1 in 5c) of the transparent patterned substrate layer (10, 23; [0063]) and is electrically connected to the transparent patterned substrate layer (10, 23; [0063]); and the second circuit bonding layer (31 in 5c) is disposed on a side of the second circuit connection layer (32 in 5c) facing away from the plurality of micro light-emitting components (21) and is electrically connected to the second circuit connection layer (32 in 5c; [0063]); and Additionally, Wang teaches wherein the display device further comprises a second bonding pad (35, corresponding to 5c of Yang; [0069]) disposed on the side of the display substrate (B2 housing layer, driving chip; [0078]), and the second bonding pad (35, corresponding to 5c of Yang) is disposed corresponding to the second circuit bonding layer (221, corresponding to 5c of Yang; [0102]) and is electrically connected to the second circuit bonding layer (221, corresponding to 5c of Yang; [0102]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 11 with the limitations taught by Wang to utilize bonding pads (Wang: 35) for connection of the transmission lines (Yang: 31) to the driving chip as taught by Wang ([0078]). Re Claim 16, Yang and Wang teach the display device according to Claim 11, while Wang further teaches the display device comprises a panel drive circuit (“driving chip”; [0083]) disposed on the side of the display substrate (B2 housing layer, driving chip, particularly lead portions of “driving chip”; [0083]) and electrically connected to the first bonding pad (35; [0083]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 11 with the limitations taught by Wang to utilize the leads of the driving chip (Wang: “driving chip”) in contact with the bonding pads (Wang: 35) as output connections for the driving chip (Wang: “driving chip”) as taught by Wang ([0083]). Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yang and Wang, as applied to Claim 11, further in view of Dong et al (US 2024/0071964 A1, hereafter Dong). Re Claim 13, Yang and Wang teach the display device according to Claim 11, while Wang further teaches the display substrate (B2 housing layer, driving chip) comprises a second substrate (B2 housing layer, driving chip; [0078]), wherein the first display unit and the first bonding pad (35) are disposed on a same side of the second substrate (B2 housing layer, driving chip; [0067]-[0069], [0078]). Yang and Wang do not explicitly disclose wherein the display substrate (Wang: B2 housing layer, driving chip) comprises a transparent conductive layer, disposed on the second substrate (Wang: B2 housing layer, driving chip) and disposed between the first bonding pad (Wang: 35) and the second substrate (Wang: B2 housing layer, driving chip), wherein the transparent conductive layer is electrically connected to the first bonding pad (Wang: 35). However, Dong teaches a display substrate (FIG. 1B; [0071]-[0084]) comprising a transparent conductive layer (109; [0083]), disposed on the second substrate (21; [0089]) and disposed between the first bonding pad (1041, 1061; [0081]) and the second substrate (21; [0089]), wherein the transparent conductive layer (109) is electrically connected to the first bonding pad (1041, 1061; [0081]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 11 with the limitations taught by Dong to use a conductive layer (Dong: 109) to facilitate connection between the bonding pad (Wang: 35)/display unit and the driving chip (Wang: “driving chip”) through intermediate layers as taught by Dong ([0081]-[0089]). Allowable Subject Matter Claim 20 is allowed. Claims 3, 6-8, 14-15, and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Re Claim 3, the prior art cannot anticipate, or render obvious, the limitations of: the first circuit bonding layer is disposed on a side of the first substrate facing away from the drive control circuit layer, in combination with the additionally claimed features of Claim 3. Re Claim 14, the prior art cannot anticipate, or render obvious, the limitations of: the first bonding pad penetrates through the circuit protection layer, in combination with the additionally claimed features of Claim 14. Re Claim 17, the prior art cannot anticipate, or render obvious, the limitations of: the first circuit bonding layer of the second display unit is electrically connected to the second bonding pad, in combination with the additionally claimed features of Claim 17. Re Claim 18, the prior art cannot anticipate, or render obvious, the limitations of: wherein the chip on film is provided with two bonding ends, one of the two bonding ends is bonded to the first bonding pad, in combination with the additionally claimed features of Claim 18. Re Claim 19, the prior art cannot anticipate, or render obvious, the limitations of: sequentially forming a compensation layer and a second substrate on a side of a glass substrate; […] separating the second substrate from the compensation layer, in combination with the additionally claimed features of Claim 19. Re Claim 20, the prior art cannot anticipate, or render obvious, the limitations of: the plurality of displaying units are tiled through electrically connecting the plurality of bonding pads with the corresponding first circuit bonding layers and the corresponding second circuit bonding layers of the plurality of displaying units, in combination with the additionally claimed features of Claim 20. In Re Claims 6-8 and Claim 15, they are objected to due to their dependence from Claims 3 and 14, respectively. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892 /NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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Prosecution Timeline

Nov 30, 2023
Application Filed
Apr 28, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
99%
With Interview (+23.3%)
3y 3m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 44 resolved cases by this examiner. Grant probability derived from career allowance rate.

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