Prosecution Insights
Last updated: April 19, 2026
Application No. 18/525,269

ANALYZING TRANSMISSION LINES

Final Rejection §102§103
Filed
Nov 30, 2023
Examiner
VELEZ, ROBERTO
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Teradyne Inc.
OA Round
2 (Final)
66%
Grant Probability
Favorable
3-4
OA Rounds
2y 10m
To Grant
88%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allow Rate
173 granted / 260 resolved
-1.5% vs TC avg
Strong +22% interview lift
Without
With
+21.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
21 currently pending
Career history
281
Total Applications
across all art units

Statute-Specific Performance

§101
2.3%
-37.7% vs TC avg
§103
52.5%
+12.5% vs TC avg
§102
27.9%
-12.1% vs TC avg
§112
14.7%
-25.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 260 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 02/19/2026 have been fully considered but they are not persuasive. Applicant argues that Gohel et al. fails to disclose or suggest constructing an approximation of the waveform using the data for the waveform from the memory; and identifying an attribute of the transmission line based on the approximation of the waveform. The examiner respectfully disagrees. Gohel et al. shows Fig. 3A-3H constructions or illustrations of approximated waveforms representative of the data obtained from signals as a result of the performed tests on line 215. Each illustration (3A-3H) includes a constructed waveform that identifies or shows an attribute of the transmission line 215. In other words, whether the transmission line is performing within acceptable voltage ranges, as shown by the result of pass or fail. Therefore, Gohel et al. does teach and suggest the recited claim limitations. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2, 12, 15-16, 18-21 and 45 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gohel et al. (US PGPUB 2006/0161827). Regarding claims 1 and 45, Gohel et al. teaches automatic test equipment (ATE) (139) comprising: a transmitter (210) to output a waveform to a transmission line (215) (as shown in fig. 1-2A and disclosed in para. 0038); circuitry or detecting means (103 and 120) to detect data for the waveform on the transmission line (215) (as shown in fi. 1-2A and disclosed in para. 0031 and 0042-0056), the waveform comprising a reflected waveform (as disclosed in para. 0042-0056), the circuitry (120 and 211A-211D) being configured to scan the waveform across a range of times (as disclosed in para. 0041 and 0046) and across a range of voltages (as shown in fig. 3A-3F) to obtain the data for the waveform; and memory to store the data detected by the circuitry (as disclosed in para. 0023, 0024, 0031 and 0052); and one or more processing devices (120 and 201) configured to perform operations comprising: constructing an approximation of the waveform using the data for the waveform from the memory (as shown in fig. 3A-3F); and identifying an attribute of the transmission line (215) based on the approximation of the waveform (as discussed in para. 0062-0071). Regarding claim 2, Gohel et al. teaches the limitations of claim 1, in addition, Gohel et al. teaches wherein the circuitry (120 and 211A-211D) is configured to obtain the data at more than one time in the range of times (as shown in fig. 3A-3F and disclosed in para. 0062-0071). Regarding claim 12, Gohel et al. teaches the limitations of claim 1, in addition, Gohel et al. teaches wherein the waveform comprises an edge (as shown in fig. 3A-3F). Regarding claim 15, Gohel et al. teaches the limitations of claim 1, in addition, Gohel et al. teaches wherein identifying the attribute comprises: identifying one or more segments of the transmission line based on the data (as shown in fig. 3A-3F); identifying an attribute for each of the one or more segments (as shown in fig. 3A-3F); and determining whether each of the one or more segments is within an acceptable tolerance based a corresponding attribute (as shown in fig. 3A-3F). Regarding claim 16, Gohel et al. teaches the limitations of claim 1, in addition, Gohel et al. teaches wherein identifying the attribute comprises: analyzing the approximation of the waveform to obtain information about the transmission line (215) (as discussed in para. 0062-0071); and outputting (using 217 and 219) the information about the transmission line (215) (as discussed in para. 0062-0071). Regarding claim 18, Gohel et al. teaches the limitations of claim 1, in addition, Gohel et al. teaches wherein the circuitry (120 and 211A-211D) is configured to detect data for multiple instances of the waveform on the transmission line (215) (as shown in fig. 3A-3F and disclosed in para. 0062-0071) and to store the data for the multiple instances of the waveform in the memory (as disclosed in para. 0023, 0024, 0031 and 0052); and wherein the one or more processing devices (120 and 201) are configured to compare the data for the multiple instances of the waveform based on a test limit (as shown in fig. 3A-3F and disclosed in para. 0062-0071) and to determine whether there is an intermittent fault on the transmission line (215) based on the comparison (as shown in fig. 3A-3F and disclosed in para. 0062-0071). Regarding claim 19, Gohel et al. teaches wherein identifying the attribute comprises: analyzing the approximation of the waveform to obtain information about the transmission line (215) (as discussed in para. 0062-0071); and detecting a fault on the transmission line (215) by comparing the information to one or more test limits programmed into the ATE (139) (as discussed in para. 0062-0071). Regarding claim 20, Gohel et al. teaches the limitations of claim 1, in addition, Gohel et al. teaches multiple transmitters (211A-211D each has a transmitter 210, as discussed in para. 0027), each transmitter (210) to output a waveform to a respective transmission line (as shown in fig. 1 and disclosed in para. 0027-0030), the transmitter (210) being among the multiple transmitters (211A-211D each has a transmitter 210); and multiple instances of the circuitry (211A-211D) to detect data for a respective waveform on a respective transmission line (as shown in fig. 1), the circuitry (211A-211D) being among the multiple instances, each instance of the circuitry being configured to scan the respective waveform across a range of times (as disclosed in para. 0041 and 0046) and across a range of voltages (as shown in fig. 3A-3F) to obtain respective data for the respective waveform and to store the respective data in the memory (as disclosed in para. 0023, 0024, 0031 and 0052); wherein the one or more processing devices (120 and 201) are configured to analyze the respective data for the respective waveforms to attempt to identify at least one of a hard transmission line fault, a crosstalk fault, or an intermittent fault (as discussed in para. 0062-0071). Regarding claim 21, Gohel et al. teaches the limitations of claim 1, in addition, Gohel et al. teaches wherein identifying the attribute comprises: one or more processing devices (120 and 201) configured to perform operations comprising: constructing an approximation of the waveform using the data for the waveform from the memory (as shown in fig. 3A-3F); and detecting a fault in an interconnect on the transmission line (215) (as discussed in para. 0062-0071). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 3, 11 and 49-50 are rejected under 35 U.S.C. 103 as being unpatentable over Gohel et al. (US PGPUB 2006/0161827) in view of Johnson et al. (US Pat. 9,164,158). Regarding claim 3, Gohel et al. teaches the limitations of claim 1, in addition, Gohel et al. teaches wherein the circuitry (120 and 211A-211D) has a threshold (V1-V4) that is settable to different values to affect scanning across the range of voltages (as shown in fig. 3A-3F). Gohel et al. fails to specifically teach wherein the circuitry comprises delay elements to affect scanning across the range of times. However, Johnson et al. teaches wherein the circuitry comprises delay elements (63 and 64) to affect scanning across the range of times (as shown in fig. 3 and disclosed in col. 6, lines 35-57). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the circuitry comprise delay elements to affect scanning across the range of times as taught by Johnson et al. with the invention of Gohel et al. in order to improve the accuracy of the measurements (Johnson et al. col. 6, lines 44-46). Regarding claim 11, Gohel et al. teaches the limitations of claim 1. Gohel et al. fails to specifically teach a test instrument comprising pin electronics associated with a communication channel to a device under test (DUT), the transmitter being implemented on the pin electronics. However, Johnson et al. teaches a test instrument comprising pin electronics (PE) associated with a communication channel (20) to a device under test (DUT), the transmitter (51) being implemented on the pin electronics (as shown in fig. 2-3 and disclosed in col. 5, lines 28-49). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the test instrument comprising pin electronics associated with a communication channel to a device under test (DUT), the transmitter being implemented on the pin electronics as taught by Johnson et al. with the invention of Gohel et al. in order to perform particular test functions (Johnson et al. col. 5, lines 28-31). Regarding claim 49, Gohel et al. teaches the limitations of claim 1. Gohel et al. fails to specifically teach wherein the circuitry comprises a pin electronic circuit and the one or more processing devices are separate from the pin electronic circuit. However, Johnson et al. teaches wherein the circuitry comprises a pin electronic circuit (34) and the one or more processing devices (50 and 52) are separate from the pin electronic circuit (34). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the circuitry comprise a pin electronic circuit and the one or more processing devices are separate from the pin electronic circuit as taught by Johnson et al. with the invention of Gohel et al. in order to individually and separately perform particular operations without interruption. Regarding claim 50, Gohel et al. teaches the limitations of claim 1. Gohel et al. fails to specifically teach wherein the circuitry comprises a pin electronic circuit and the one or more processing devices are shared between the pin electronics circuit and another pin electronics circuit. However, Johnson et al. teaches wherein the circuitry comprises a pin electronic circuit (34) and the one or more processing devices (50and 52) are shared between the pin electronics circuit and another pin electronics circuit (as shown in fig. 2). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the circuitry comprise a pin electronic circuit and the one or more processing devices are shared between the pin electronics circuit and another pin electronics circuit as taught by Johnson et al. with the invention of Gohel et al. in order to save on equipment costs. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Gohel et al. (US PGPUB 2006/0161827) in view of Bechhoefer et al. (EP 1477820A2). Regarding claim 13, Gohel et al. teaches the limitations of claim 1. Gohel et al. fails to specifically teach wherein the attribute comprises the impedance of the transmission line or part of the transmission line. However, Bechhoefer et al. teaches wherein the attribute comprises an impedance of the transmission line or part of the transmission line (as discussed in para. 0038). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the attribute comprise the impedance of the transmission line or part of the transmission line as taught by Bechhoefer et al. with the invention of Gohel et al. in order to prevent signal reflections and power loss. Claims 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Gohel et al. (US PGPUB 2006/0161827) in view of Spehlmann (US PGPUB 2017/0146332). Regarding claim 14, Gohel et al. teaches the limitations of claim 12. Gohel et al. fails to specifically teach wherein the attribute comprises a length of the transmission line. However, Spehlmann teaches wherein the attribute comprises a length of the transmission line (as shown in fig. 2 and disclosed in para. 0034). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the attribute comprise a length of the transmission line as taught by Spehlmann with the invention of Gohel et al. in order to detect breaks or short circuits (Spehlmann para. 0017). Regarding claim 17, Gohel et al. teaches the limitations of claim 16. Gohel et al. fails to specifically teach wherein the information comprises at least one of:(i) a location of an open circuit on the transmission line, (ii) a location of a short circuit on the transmission line, (iii) one or more impedances on the transmission line, or (iv) a length of the transmission line or a segment of the transmission line. However, Spehlmann teaches wherein the information comprises at least one of:(i) a location of an open circuit on the transmission line, (ii) a location of a short circuit on the transmission line, (iii) one or more impedances on the transmission line, or (iv) a length of the transmission line or a segment of the transmission line (as shown in fig. 2 and disclosed in para. 0036). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the information comprise at least one of:(i) a location of an open circuit on the transmission line, (ii) a location of a short circuit on the transmission line, (iii) one or more impedances on the transmission line, or (iv) a length of the transmission line or a segment of the transmission line as taught by Spehlmann with the invention of Gohel et al. in order to identify a transmission line for repair or to alter test protocols to avoid the faulty transmission line (Spehlmann para. 0022). Claims 46-47 are rejected under 35 U.S.C. 103 as being unpatentable over Gohel et al. (US PGPUB 2006/0161827) in view of CHANG et al. (KR 100853403 B1). Regarding claim 46, Gohel et al. teaches the limitations of claim 1. Gohel et al. fails to specifically teach wherein the circuitry and the one or more processing devices are both part of a pin electronics circuit. However, CHANG et al. teaches wherein the circuitry (131 and 136) and the one or more processing devices (135) are both part of a pin electronics circuit (130) (as shown in fig. 5). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the circuitry and the one or more processing devices both part of a pin electronics circuit as taught by CHANG et al. with the invention of Gohel et al. in order to efficiently have a compact and completely functional pin electronics circuit. Regarding claim 47, Gohel et al. teaches the limitations of claim 1. Gohel et al. fails to specifically teach wherein the one or more processing devices are part of the circuitry. However, CHANG et al. teaches wherein the one or more processing devices (135) are part of the circuitry (130) (as shown in fig. 5). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the one or more processing devices are part of the circuitry as taught by CHANG et al. with the invention of Gohel et al. in order to efficiently have a compact and completely functional circuitry. Claim 48 is rejected under 35 U.S.C. 103 as being unpatentable over Gohel et al. (US PGPUB 2006/0161827) and CHANG et al. (KR 100853403 B1) as applied to claim 47 above, and further in view of Gohel et al. (US PGPUB 2018/0316420). Regarding claim 48, the combination of Gohel et al. and CHANG et al. teaches the limitations of claim 47. The combination of Gohel et al. and CHANG et al. fails to specifically teach wherein the one or more processing devices comprise programmable logic. However, Gohel et al. teaches wherein the one or more processing devices comprise programmable logic (as disclosed in para. 0054). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the one or more processing devices comprise programmable logic as taught by Gohel et al. with the invention of the combination of Gohel et al. and CHANG et al. in order to use a device that’s accurate and performs robustly at high temperatures. Allowable Subject Matter Claims 4-10 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding claim 4, the prior art fails to specifically teach wherein, to detect the data for the waveform, the circuitry is configured to perform operations comprising: (a) receiving a value for the threshold; (b) for the value of the threshold that was received, performing operations comprising:(i) sampling the waveform at times in the range that are separated by a time period to obtain data for the waveform;(ii) incrementing the times using a delay element to produce incremented times, the delay element adding a delay to each time, the delay being a fraction of the time period; (iii) repeating operations (i) and (ii) a predetermined number of times, each time replacing the times with the incremented times;(c) obtaining an updated value for the threshold; and(d) repeating operations (a) through (c) a predetermined number of times, each time using the updated value for the threshold as the value for the threshold, in combination with all the limitations of the claim. Claims 5-10 depending from claim 4, and/or further depending from another claim depending from claim 4, are allowed for the same reasons in combination with the limitations of their dependency. Claims 38-44 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERTO VELEZ whose telephone number is (571)272-8597. The examiner can normally be reached Mon-Fri 5:30am-3:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at (571)272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ROBERTO VELEZ/Primary Examiner, Art Unit 2858
Read full office action

Prosecution Timeline

Nov 30, 2023
Application Filed
Nov 14, 2025
Non-Final Rejection — §102, §103
Feb 19, 2026
Response Filed
Mar 06, 2026
Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
66%
Grant Probability
88%
With Interview (+21.6%)
2y 10m
Median Time to Grant
Moderate
PTA Risk
Based on 260 resolved cases by this examiner. Grant probability derived from career allow rate.

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