DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/16/2026 has been entered.
For further details see the rejections/objections for Claim(s) 1-4, 6-11 and 22-24 herein.
Claim Objections
Claim 7 is objected to because of the following informalities:
Claim 7 recites a term “a drain of the respective sense transistor” in lines 8-9. Examiner suggests amending the term to recite “the drain of the respective sense transistor” to restore antecedent clarity.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-8, 10-11 and 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Clayton et al. (US 2022/082595; hereinafter Clayton) in view of Chauhan et al. (US 20180123578).
Regarding claim 1, Clayton teaches in figure(s) 1-4 a chip (200; fig. 2), comprising:
a power grid (220; fig. 2);
power switches (204) coupled between the power grid (220) and a circuit (202);
current sensors (208) configured to generate sense currents (IR) based on load currents (I) passing through the power switches (204; para. 18);
a readout circuit (214) having an input and an output; and
signal routing (212) coupling the current sensors to the input of the readout circuit (214).
wherein the respective current mirror of each of the current sensors comprises:
a respective sense transistor (306; fig. 4);
a respective amplifier (402); and
a respective feedback transistor (302),
Clayton does not teach explicitly wherein each of the current sensors comprises:
a respective current mirror coupled to a gate of a respective one of the power switches; and
a respective current buffer having an input and an output, wherein the input of the respective current buffer is coupled to the respective current mirror, and the output of the respective current buffer is coupled to the signal routing.
wherein a drain of the respective feedback transistor is coupled to a drain of the respective sense transistor, a gate of the respective feedback transistor is coupled to the output of the respective amplifier, and a source of the respective feedback transistor is coupled to the input of the respective current buffer.
However, Chauhan teaches in figure(s) 1-12 wherein each of the current sensors comprises:
a respective current mirror (310; fig. 3) coupled to a gate of a respective one of the power switches (309); and
a respective current buffer (413, 1107@VMID; figs. 4,3,11) having an input and an output, wherein the input of the respective current buffer is coupled to the respective current mirror (@VMON), and the output of the respective current buffer is coupled to the signal routing (Vout; fig. 4).
wherein a drain of the respective feedback transistor (FB-FET; fig. 5) is coupled to a drain of the respective sense transistor (SENS-FET), a gate of the respective feedback transistor is coupled to the output of the respective amplifier (507), and a source of the respective feedback transistor is coupled to the input of the respective current buffer (413, 1107@VMID; figs. 4,3,11).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Clayton by having wherein each of the current sensors comprises: a respective current mirror coupled to a gate of a respective one of the power switches; and a respective current buffer having an input and an output, wherein the input of the respective current buffer is coupled to the respective current mirror, and the output of the respective current buffer is coupled to the signal routing, wherein a drain of the respective feedback transistor is coupled to a drain of the respective sense transistor, a gate of the respective feedback transistor is coupled to the output of the respective amplifier, and a source of the respective feedback transistor is coupled to the input of the respective current buffer as taught by Chauhan in order to provide use of known technique to improve similar devices (methods, or products) in the same way for power efficiency as evidenced by "a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load" (abs.).
Regarding claim 2, Clayton teaches in figure(s) 1-4 the chip of claim 1, wherein each of the sense currents is proportional to a respective one of the load currents (abs. - plurality of sensing circuits are configured to generate a plurality of currents, respectively, that are proportional to a plurality of load currents, respectively).
Regarding claim 3, Clayton teaches in figure(s) 1-4 the chip of claim 1, wherein each of the power switches comprises a respective switch transistor (204).
Regarding claim 4, Clayton teaches in figure(s) 1-4 the chip of claim 1, wherein each of the power switches comprises a respective p-type field effect transistor (PFET) (302; fig. 3).
Regarding claim 6, Clayton teaches in figure(s) 1-4 the chip of claim 1, wherein each of the power switches comprises a respective switch transistor (204).
Regarding claim 7, Clayton teaches in figure(s) 1-4 the chip of claim 1, wherein a gate of the respective sense transistor is coupled to the gate of the respective one of the power switches (302), and a source of the respective sense transistor is coupled to the power grid (Vdd); wherein a first input of the respective amplifier is coupled to a drain of the respective one of the power switches (302), and the second input of the respective amplifier is coupled to a drain of the respective sense transistor (306).
Regarding claim 8, Clayton teaches in figure(s) 1-4 the circuit of claim 1, wherein the readout circuit comprises: a transimpedance amplifier (216) having an input and an output, wherein the input of the transimpedance amplifier is coupled to the input of the readout circuit, and an analog-to-digital converter (ADC) (218) coupled to the output of the transimpedance amplifier.
Regarding claim 10, Clayton teaches in figure(s) 1-4 the chip of claim 8, wherein the transimpedance amplifier (216) is configured to convert a sum of the sense currents at the input of the transimpedance amplifier into an output voltage (va) at the output of the transimpedance amplifier.
Regarding claim 11, Clayton teaches in figure(s) 1-4 the chip of claim 1, wherein the readout circuit (214) is configured to convert a sum of the sense currents at the input of the readout circuit into a digital signal (DS).
Regarding claim 22, Clayton teaches in figure(s) 1-4 a method for measuring current, comprising:
generating sense currents (IR; fig. 2) based on load currents (I) passing through power switches (204) coupled between a power grid (220) and a circuit (202);
summing, via signal routing, the sense currents to obtain a combined current (∑IR; fig. 2); and
converting the combined current into a digital signal (218; fig. 2), wherein the respective current mirror of each of the current sensors comprises:
a respective sense transistor (306; fig. 4);
a respective amplifier (402); and
a respective feedback transistor (302),
Clayton does not teach explicitly wherein generating the sense currents comprises:
coupling a gate of a respective one of the power switches to a respective current mirror;
coupling an input of a respective current buffer to the respective current mirror; and
coupling an output of the respective current buffer to the signal routing;
the method further comprises: coupling a drain of the respective feedback transistor to a drain of the respective sense transistor, coupling a gate of the respective feedback transistor to the output of the respective amplifier, and coupling a source of the respective feedback transistor to the input of the respective current buffer.
However, Chauhan teaches in figure(s) 1-12 wherein generating the sense currents comprises:
coupling a gate of a respective one of the power switches (309; fig. 3) to a respective current mirror (310);
coupling an input of a respective current buffer (413, 1107@VMID; figs. 4,3,11) to the respective current mirror (@VMON); and
coupling an output of the respective current buffer to the signal routing (Vout; fig. 4).
the method further comprises: coupling a drain of the respective feedback transistor (FB-FET; fig. 5) to a drain of the respective sense transistor (SENS-FET), coupling a gate of the respective feedback transistor to the output of the respective amplifier (507), and coupling a source of the respective feedback transistor to the input of the respective current buffer (413, 1107@VMID; figs. 4,3,11).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Clayton by having wherein generating the sense currents comprises: coupling a gate of a respective one of the power switches to a respective current mirror; coupling an input of a respective current buffer to the respective current mirror; and coupling an output of the respective current buffer to the signal routing; the method further comprises: coupling a drain of the respective feedback transistor to a drain of the respective sense transistor, coupling a gate of the respective feedback transistor to the output of the respective amplifier, and coupling a source of the respective feedback transistor to the input of the respective current buffer as taught by Chauhan in order to provide use of known technique to improve similar devices (methods, or products) in the same way for power efficiency as evidenced by "a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load" (abs.).
Regarding claim 23, Clayton teaches in figure(s) 1-4 the method of claim 22, wherein each of the sense currents is proportional to a respective one of the load currents (abs. - plurality of sensing circuits are configured to generate a plurality of currents, respectively, that are proportional to a plurality of load currents, respectively).
Regarding claim 24, Clayton teaches in figure(s) 1-4 the method of claim 22, wherein converting the combined current into the digital signal comprises: converting the combined current into a voltage (va ); and converting the voltage into the digital signal (DS).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Clayton in view of Chauhan, and further in view of Schuppener et al. (US 20140111280).
Regarding claim 9, Clayton in view of Chauhan teaches the chip of claim 8,
Clayton does not teach explicitly wherein the transimpedance amplifier comprises: an operational amplifier having a first input, a second input, and an output, wherein the first input of the operational amplifier is coupled to the input of the transimpedance amplifier, the second input of the operational amplifier is coupled to a ground, and the output of the operational amplifier is coupled to the output of the transimpedance amplifier; and a feedback resistor coupled between the output of the operational amplifier and the first input of the operational amplifier.
However, Schuppener teaches in figure(s) 1-7 wherein the transimpedance amplifier comprises: an operational amplifier (40; fig. 1) having a first input, a second input, and an output, wherein the first input of the operational amplifier is coupled to the input of the transimpedance amplifier (4), the second input of the operational amplifier is coupled to a ground, and the output of the operational amplifier is coupled to the output of the transimpedance amplifier; and a feedback resistor (Rf) coupled between the output of the operational amplifier and the first input of the operational amplifier.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Clayton by having wherein the transimpedance amplifier comprises: an operational amplifier having a first input, a second input, and an output, wherein the first input of the operational amplifier is coupled to the input of the transimpedance amplifier, the second input of the operational amplifier is coupled to a ground, and the output of the operational amplifier is coupled to the output of the transimpedance amplifier; and a feedback resistor coupled between the output of the operational amplifier and the first input of the operational amplifier as taught by Schuppener in order to provide combining prior art elements according to known methods to yield predictable results as evidenced by "A feedback resistor is coupled in series between an output node of the amplifier and an inverting input node of the amplifier to provide a virtual ground node which is coupled to the input node, the inverting input node of the amplifier and to the feedback resistor. A current source is coupled to the virtual ground node so as to compensate for an offset current in an input signal which is coupled to the input node of the electronic device." (abstract).
Allowable Subject Matter
Claim(s) 12-13, 15-18, 20 and 25-27 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Independent claim(s) 12 and 25 have been amended to include limitations/features from cancelled dependent claim 21, which were indicated as allowable subject matter in the previous Office Action mailed.
Claim(s) 13, 15-18, 20 and 26-27 are allowable for dependent upon the allowable base claim(s).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKM ZAKARIA whose telephone number is (571). The examiner can normally be reached on 8-5 PM (PST).
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/AKM ZAKARIA/
Primary Examiner, Art Unit 2858
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