Prosecution Insights
Last updated: April 19, 2026
Application No. 18/525,362

THREE-DIMENSIONAL MEMORY ARRAY FORMATION TECHNIQUES

Non-Final OA §102§103
Filed
Nov 30, 2023
Examiner
FERNANDES, ERROL V
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology, Inc.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
96%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
667 granted / 786 resolved
+16.9% vs TC avg
Moderate +12% lift
Without
With
+11.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
28 currently pending
Career history
814
Total Applications
across all art units

Statute-Specific Performance

§103
58.7%
+18.7% vs TC avg
§102
36.7%
-3.3% vs TC avg
§112
4.0%
-36.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 786 resolved cases

Office Action

§102 §103
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2 and 4-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang US 2020/0335509 A1. Regarding claims 1, 2, and 4-11, Yang discloses: A method (Figs. 2 and 4B), comprising: forming, over a substrate (200 as shown in Fig. 2), a stack of layers (210/220 as shown in Fig. 2); forming an array of pillars (320) that each extend at least partially through the stack of layers in a first direction (320 vertically through that stack of layers in Fig. 4B) non-parallel to the substrate, the array of pillars being arranged in columns of pillars extending in a second direction (320 shown left-to-right in Fig. 4B) parallel to the substrate and rows of pillars extending in a third direction (320 shown top-to-down in Fig. 4B) parallel to the substrate; forming a slit (350) at least partially through the stack of layers and extending in the second direction, a first portion of the slit through a first portion (350b) of the stack of layers having a first width and a second portion of the slit through a second portion (350a) of the stack of layers having a second width less than the first width; and forming a dielectric material (352) in the slit, the dielectric material having the first width at the first portion of the slit and the second width at the second portion of the slit. (claim 2) Fig. 4B; a second column of pillars (320 in 310b) comprising a second quantity of pillars greater than a first column of pillars (320 in 310a) comprising a first quantity of pillars, wherein the first width is greater than the second width based at least in part of the first quantity of pillars being less than the second quantity of pillars (Fig. 4B less pillars in 310b than 310a). (claim 4) Fig. 4B; slit shown with first and second portion at interface of 310a/310b where quantity of pillars 320 in 310b are less than quantity of pillars 320 in 310a. (claims 5 and 6) Fig. 4B; quantity of pillars 320 in 310b are less than quantity of pillars 320 in 310a. (claim 7) Figs. 2G and 4B; steps S430-S436. (claim 8) Figs. 2G and 4B; step S450. (claim 9) Figs. 2G and 4B; step S490, a contact region 354. (claim 10) Fig. 4B. (claim 11) Fig. 4B; 320 in 310a. Regarding claims 13, 14 and 16, Yang discloses: An apparatus (Figs. 2 and 4B), comprising: a substrate (200 as shown in Fig. 2); a stack of materials (210/220 as shown in Fig. 2) over the substrate and comprising a plurality of levels of memory cells (3D memory cells); an array of pillars (320) over the substrate and extending at least partially through the stack of materials in a first direction (320 vertically through that stack of layers in Fig. 4B) non-parallel to the substrate, the array of pillars configured to provide structural support to the plurality of levels of memory cells, the array of pillars arranged in columns of pillars extending in a second direction (320 shown left-to-right in Fig. 4B) parallel to the substrate and rows of pillars extending in a third direction (320 shown top-to-down in Fig. 4B) parallel to the substrate; and a dielectric material (352) located in a slit (350) through the stack of materials and extending in the second direction, a first portion of the slit through a first portion (350b) of the stack of materials having a first width and a second portion (350b) of the slit through a second portion of the stack of materials having a second width, the dielectric material having the first width at the first portion of the slit and the second width at the second portion of the slit. (claim 14) Fig. 4B; a second column of pillars (320 in 310b) comprising a second quantity of pillars greater than a first column of pillars (320 in 310a) comprising a first quantity of pillars, wherein the first width is greater than the second width based at least in part of the first quantity of pillars being less than the second quantity of pillars (Fig. 4B less pillars in 310b than 310a). (claim 16) Fig. 4B. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang US 2020/0335509 A1. Regarding claim 3, although Yang does not specifically disclose “wherein forming the array of pillars comprises: forming a mask comprising a pillar patterning for the array of pillars over the stack of layers, wherein the pillar patterning comprises the first column of pillars and the second column of pillars; etching an array of cavities at least partially through the stack of layers in accordance with the pillar patterning; and forming the array of pillars in the array of cavities”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to understand that such a method for forming the pillars, as disclosed by Yang’s step Fig. 2G S440 para 0046, would be a standard operation in determining such features requiring masking, etching and deposition. Allowable Subject Matter Claims 12, 15 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations of claim 12 stating “forming a second array of pillars that each extend at least partially through the stack of layers in the first direction; removing, via the slit, a plurality of layers of the stack of layers; forming, via the slit, a plurality of word lines within locations of the removed plurality of layers; and forming, via the slit, an array of memory cells within the locations of the removed plurality of layers, the array of memory cells comprising a plurality of levels of memory cells, wherein each memory cell of the plurality of levels of memory cells are coupled with a respective word line of the plurality of word lines and a pillar of the second array of pillars, and wherein the dielectric material is formed in the slit after the array of memory cells is formed ”; of claim 15 stating “a contact region comprising a plurality of contacts coupled with control circuitry configured to access the plurality of levels of memory cells, wherein a width of the dielectric material transitions from the second width to the first width at an interface between the contact region and the array of pillars”; and of claim 17 stating “a second array of pillars that each extend at least partially through the stack of materials in the first direction; and a plurality of word lines included in the stack of materials, wherein each memory cell of the plurality of levels of memory cells are coupled with a respective word line of the plurality of word lines and a pillar of the second array of pillars”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention. Claims 18-20 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art fails to teach or clearly suggest the limitations of claim 18 stating “ a first width of a first portion the dielectric material that is adjacent to the array of first pillars being less than a second width of a second portion of the dielectric material that is adjacent to the array of second pillars”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERROL V FERNANDES/Primary Examiner, AU 2893
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Prosecution Timeline

Nov 30, 2023
Application Filed
Mar 20, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
96%
With Interview (+11.6%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 786 resolved cases by this examiner. Grant probability derived from career allow rate.

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