Prosecution Insights
Last updated: July 17, 2026
Application No. 18/525,467

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME

Non-Final OA §102§103
Filed
Nov 30, 2023
Priority
Sep 19, 2022 — CN 202211139021.2 +1 more
Examiner
WARREN, MATTHEW E
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Changxin Memory Technologies Inc.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
879 granted / 1003 resolved
+19.6% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
17 currently pending
Career history
1024
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
69.9%
+29.9% vs TC avg
§102
25.8%
-14.2% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1003 resolved cases

Office Action

§102 §103
DETAILED ACTION This Office Action is in response to the Election filed on March 5, 2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Group I, claims 1-11 in the reply filed on March 5, 2026 is acknowledged. The traversal is on the ground(s) that both inventions I and II have the same features. This is not found persuasive because the two inventions are classified in which require two separate searches. Method subclasses do not overlap with semiconductor device classes in that method limitations often include specific chemistry, processing steps, sequences or concepts that are not relevant to actual semiconductor structure itself. Method claims require a specialization or background in chemistry while Device claims require a specialization or background in electrical engineering. An examiner who examines method claims only may not have the necessary expertise in examining device claims, and vice-versa. Even if such were not the case, a complete examination of both inventions would require search and consideration within different classes. A burden is placed on the examiner in such a situation. The requirement is still deemed proper and is therefore made FINAL. Claims 12-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply. Priority Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China on September 19, 2022. It is noted, however, that applicant has not filed a certified copy of the CN202211139021.2 application as required by 37 CFR 1.55. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-6 and 8-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koyanagi (US Pub. 2020/0020670 A1). In re claim 1, Koyanagi shows (fig. 16) a semiconductor structure, comprising: a plurality of dies P3, P4), stacked sequentially along a first direction (z), the first direction being a direction perpendicular to a plane (x,y) of the plurality of dies; wherein, each of the plurality of dies comprises: a base (CC1; SC0, SC1); and n first conductive structures (123-1, 123-2, 123-9, 123-10) penetrating the base along the first direction, wherein n is greater than or equal to 2; wherein, in at least one group of the corresponding first conductive structures (123-1, 123-2) in all the dies, projections of the group of the corresponding first conductive structures (123-9, 123-10) in two adjacent layers of the dies (SC0, SC1) along the first direction are not overlapped with each other. In re claim 2, Koyanagi shows (fig. 16) first interconnects (125-7, 125-8, 125-9, 125-10), wherein the corresponding first conductive structures in two adjacent layers of the dies are connected through the first interconnects. In re claim 3, Koyanagi shows (fig. 16) the n first conductive structures are located on a same circumference; in a projection in the first direction, projections of the corresponding first conductive structures in two adjacent layers of the dies are not overlapped with each other. In re claim 4, Koyanagi shows (figs. 24, 25) lines connecting the projections of the corresponding first conductive structures (223-7a, 225-8, 223-8a, 225-9) in two adjacent layers of the dies with a center of a projection of the circumference respectively form a preset angle, and the preset angle ranges from 30° to 90° (fig. 24). In re claim 5, Koyanagi shows (fig. 16) the corresponding first conductive structures in respective layers of the dies spiral up at the preset angle along a preset direction in the first direction, wherein the preset direction is clockwise or counterclockwise. In re claim 6, Koyanagi shows (fig. 16) each of the first conductive structures (123-1,123-2, etc) comprises a first through-silicon via [0192] and a first conductive bump (MB-1, MB-2), the first through-silicon via is located on the first conductive bump, the first through-silicon via penetrates the base along the first direction, and the first conductive bump is located between two adjacent layers of the dies. In re claim 8, Koyanagi shows (fig. 16) one end of each of the first interconnects is connected with the first through-silicon via, and the other end of the first interconnect is connected with the first conductive bump. In re claim 9, Koyanagi shows (fig. 16) comprises a second conductive structure (123-3, 123-8) located at a center of the circumference formed by the n first conductive structures and penetrating the base along the first direction. In re claim 10, Koyanagi shows (fig. 16) second interconnects (others of 125-1, 125-2), the second conductive structures in two adjacent layers of the dies being connected through the second interconnects. In re claim 11, Koyanagi shows (fig. 16) the first conductive structures are signal conductive structures [0193-0297], and the second conductive structure is a dummy conductive structure (since it is not connected to the circuit structure). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Koyanagi (US Pub. 2020/0020670 A1) as applied to claim 1 above, and further in view of the cited case law. In re claim 7, Koyanagi shows all of the elements of the claim except the first conductive bump comprises at least one concave surface; the concave surfaces on the adjacent first conductive bumps are opposite to each other. It would have been obvious to one of ordinary skill in the art at the time the invention was made to form the bumps having any suitable shape since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zhang (US Pub. 2024/0136284-A1), Lee (US Pub. 2016/0013157-A1), Nin (US Pub. 2012/0267776-A1), Shibata (US Pub. 2006/0267212-A1), (KR-102743042 B1), and Huang (CN-113178433-A) show various elements of the claims including the plurality of dies, stacked in a first direction and the conductive structures penetrating the base of the dies. Most of the references do not explicitly disclose the projections of the of the group of corresponding first conductive structures in two adjacent layers are not overlapped with each other. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at 571-272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW E WARREN/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Nov 30, 2023
Application Filed
May 14, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
93%
With Interview (+5.6%)
2y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1003 resolved cases by this examiner. Grant probability derived from career allowance rate.

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