DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-15, in the reply filed on 4/23/26 is acknowledged.
Rejection over JP H01120028 A
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, and 7 is/are rejected under 35 U.S.C. 102a1 as being clearly anticipated by JP H01120028 A, hereafter referred to as Japan.
Regarding claim 1, Japan (figure 1) teaches an integrated circuit die comprising:
a substrate 11;
a semiconductor device (under 12) formed on the substrate 11; and
a passivation layer 12 formed over the substrate 11, the passivation layer 12 having chamfered corners 121/122 disposed in corner regions of the integrated circuit die (under 12), wherein the chamfered corners 121/122 of the passivation layer 12 are dimensioned to mitigate damage to the passivation layer in the corner regions during die singulation (abstract).
With respect to claim 2, Japan (figure 1) teaches in a first corner region 121 of the integrated circuit die (under 12), the passivation layer 12 comprises a first chamfered surface 121 that extends between a first side surface of the passivation layer 12 and a second side surface of the passivation layer 12.
As to claim 3, Japan, which teaches 135 degrees, teaches a first angle between the first side surface and the first chamfered surface is between 130 and 140 degrees, and a second angle between the second side surface and the first chamfered surface is between 130 and 140 degrees.
In re claim 7, Japan, which teaches silicon oxide, teaches the passivation layer comprises silicon nitride or silicon oxide.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4-6, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP H01120028 A, as applied to claim 1 above.
Concerning claim 4, though Japan may fail to teach the first corner region further comprises a first corner of the substrate, a first side surface of the substrate, and a second side surface of the substrate, the first and second side surfaces of the substrate intersect at the first corner of the substrate, a first perpendicular distance between the first corner of the substrate and the first chamfered surface of the passivation layer is greater than a second perpendicular distance between the first corner of the substrate and an intersection between a first plane and a second plane, and the first side surface lies within the first plane and the second side surface lies within the second plane, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative perpendicular distance (MPEP 2144.05). A skilled artisan would determine the optimal perpendicular distance in order to minimize the damage caused by singulation.
Pertaining to claim 5, though Japan may fail to teach the first perpendicular distance is between 1.1 and 10 times greater than the second perpendicular distance, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative perpendicular distance (MPEP 2144.05).
In claim 6, though Japan fails to teach the semiconductor device comprises at least one gallium nitride (GaN) transistor, it would have been obvious to one of ordinary skill in the art at the time of the invention to use GaN in the invention of Japan because GaN is a conventionally known and used material. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Regarding claim 8, though Japan fails to teach the substrate comprises at least one of GaN or silicon carbide (SiC) , it would have been obvious to one of ordinary skill in the art at the time of the invention to use GaN or SiC in the invention of Japan because GaN or SiC are conventionally known and used materials. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Claim(s) 9-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP H01120028 A, hereafter referred to as Japan.
With respect to claim 9, Japan (figure 1) teaches an integrated circuit die comprising:
a semiconductor substrate 11;
a semiconductor device (under 12) formed on the semiconductor substrate 11; and
a passivation layer 12 formed over the semiconductor substrate 11, the passivation layer 12 comprising a plurality of chamfered corners 121/122 disposed at respective corner regions of the integrated circuit die (under 12), wherein a first corner region 121 of the integrated circuit die (under 12) includes a first chamfered corner 121 of the plurality of chamfered corners 121/122 and a first corner of the semiconductor substrate 11, and wherein the chamfered surface 121/122 extends between a first side surface of the passivation layer 12 and a second side surface of the passivation layer 12, the first side surface lies within the first plane, and the second side surface lies within the second plane.
Though Japan fails to teach a first perpendicular distance between a chamfered surface of the first chamfered corner and the first corner of the semiconductor substrate is greater than a second perpendicular distance between the first corner of the semiconductor substrate and an intersection between a first plane and a second plane, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative perpendicular distance (MPEP 2144.05). A skilled artisan would determine the optimal perpendicular distance in order to minimize the damage caused by singulation.
As to claim 10, Japan, which teaches 135 degrees, teaches an angle between the chamfered surface and a side surface of the passivation layer that is adjacent to the chamfered surface is between 130 degrees and 140 degrees.
In re claim 11, though Japan fails to teach the first perpendicular distance is between 1.1 and 10 times greater than the second perpendicular distance, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative perpendicular distance (MPEP 2144.05). A skilled artisan would determine the optimal perpendicular distance in order to minimize the damage caused by singulation.
Concerning claim 12, though Japan fails to teach the semiconductor device comprises at least one gallium nitride (GaN) transistor, it would have been obvious to one of ordinary skill in the art at the time of the invention to use GaN in the invention of Japan because GaN is a conventionally known and used material. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Pertaining to claim 13, Japan, which teaches silicon oxide, teaches the passivation layer comprises silicon nitride or silicon oxide.
In claim 14, though Japan fails to teach the semiconductor substrate comprises at least one of GaN or silicon carbide (SiC), it would have been obvious to one of ordinary skill in the art at the time of the invention to use GaN or SiC in the invention of Japan because GaN or SiC are conventionally known and used materials. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Regarding claim 15, though Japan fails to teach the semiconductor substrate comprises a SiC base substrate and at least one epitaxially-grown GaN layer formed over the SiC base substrate, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Japan because it is conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Rejections over Aoki, US 10,600,899
Claim(s) 1, 2, and 6-8 is/are rejected under 35 U.S.C. 102a1 as being clearly anticipated by Aoki, US 10,600,899.
With respect to claim 1, Aoki (figures 1 & 3) teaches an integrated circuit die comprising:
a substrate 10;
a semiconductor device S formed on the substrate 10; and
a passivation layer 22/23 formed over the substrate 10, the passivation layer 22/23 having chamfered corners 121/122 disposed in corner regions of the integrated circuit die (under 12), wherein the chamfered corners of the passivation layer 22/23 are dimensioned to mitigate damage to the passivation layer in the corner regions during die singulation (column 1, lines 16-49).
With respect to claim 2, Aoki (figures 1 & 3) teaches in a first corner region of the integrated circuit die S, the passivation layer 22/23 comprises a first chamfered surface that extends between a first side surface of the passivation layer 22/23 and a second side surface of the passivation layer 22/23.
As to claim 6, Aoki (column 3, lines 32-42) teaches the semiconductor device comprises at least one gallium nitride (GaN) transistor.
In re claim 7, Aoki (column 3, line 63-column 4, line 5) teaches the passivation layer comprises silicon nitride or silicon oxide.
Concerning claim 8, Aoki (column 3, lines 32-42) teaches the substrate comprises at least one of GaN or silicon carbide (SiC).
Claim(s) 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Aoki, US 10,600,899, as applied to claim 1 above.
Pertaining to claim 3, though Aoki fails to teach a first angle between the first side surface and the first chamfered surface is between 130 and 140 degrees, and a second angle between the second side surface and the first chamfered surface is between 130 and 140 degrees, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the angle (MPEP 2144.05).
In claim 4, though Aoki fails to teach the first corner region further comprises a first corner of the substrate, a first side surface of the substrate, and a second side surface of the substrate, the first and second side surfaces of the substrate intersect at the first corner of the substrate, a first perpendicular distance between the first corner of the substrate and the first chamfered surface of the passivation layer is greater than a second perpendicular distance between the first corner of the substrate and an intersection between a first plane and a second plane, and the first side surface lies within the first plane and the second side surface lies within the second plane, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative perpendicular distance (MPEP 2144.05). A skilled artisan would determine the optimal perpendicular distance in order to minimize the damage caused by singulation.
Regarding claim 5, though Aoki fails to teach the first perpendicular distance is between 1.1 and 10 times greater than the second perpendicular distance, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative perpendicular distance (MPEP 2144.05).
Claim(s) 9-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Aoki, US 10,600,899.
With respect to claim 9, Aoki (figures 1 & 3) teaches an integrated circuit die comprising:
a semiconductor substrate 10;
a semiconductor device S formed on the semiconductor substrate 10; and
a passivation layer 22/23 formed over the semiconductor substrate 10, the passivation layer 22/23 comprising a plurality of chamfered corners disposed at respective corner regions of the integrated circuit die 1, wherein a first corner region of the integrated circuit die 1 includes a first chamfered corner of the plurality of chamfered corners and a first corner of the semiconductor substrate 10, wherein the chamfered surface extends between a first side surface of the passivation layer and a second side surface of the passivation layer, the first side surface lies within the first plane, and the second side surface lies within the second plane.
Though Aoki fails to teach a first perpendicular distance between a chamfered surface of the first chamfered corner and the first corner of the semiconductor substrate is greater than a second perpendicular distance between the first corner of the semiconductor substrate and an intersection between a first plane and a second plane, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative perpendicular distance (MPEP 2144.05). A skilled artisan would determine the optimal perpendicular distance in order to minimize the damage caused by singulation.
As to claim 10, though Aoki fails to teach an angle between the chamfered surface and a side surface of the passivation layer that is adjacent to the chamfered surface is between 130 degrees and 140 degrees, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the angle (MPEP 2144.05).
In re claim 11, though Aoki fails to teach the first perpendicular distance is between 1.1 and 10 times greater than the second perpendicular distance, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative perpendicular distance (MPEP 2144.05).
Concerning claim 12, Aoki (column 3, lines 32-42) teaches the semiconductor device comprises at least one gallium nitride (GaN) transistor.
Pertaining to claim 13, Aoki (column 3, line 63-column 4, line 5) teaches the passivation layer comprises silicon nitride or silicon oxide.
In claim 14, Aoki (column 3, lines 32-42) teaches the semiconductor substrate comprises at least one of GaN or silicon carbide (SiC).
Regarding claim 15, though Aoki fails to teach semiconductor substrate comprises a SiC base substrate and at least one epitaxially-grown GaN layer formed over the SiC base substrate, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Aoki because it is conventionally known and used equivalent. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
Rejections over Kunishige et al., US 2022/0344229
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102a1 as being clearly anticipated by Kunishige et al., US 2022/0344229.
With respect to claim 1, Kunishige (figures 1 & 2) teaches an integrated circuit die comprising:
a substrate 10;
a semiconductor device (attached to 11/12) formed on the substrate 11; and
a passivation layer 20 formed over the substrate 10, the passivation layer 20 having chamfered corners 20a disposed in corner regions of the integrated circuit die (attached to 11/12), wherein the chamfered corners 20a of the passivation layer 20 are dimensioned to mitigate damage to the passivation layer in the corner regions during die singulation (inherent to the stress suppression of paragraphs 0007-0009).
As to claim 2, Kunishige (figures 1 & 2) teaches in a first corner region 10a of the integrated circuit die 10, the passivation layer 20 comprises a first chamfered surface 20a that extends between a first side surface of the passivation layer 20 and a second side surface of the passivation layer 20.
Claim(s) 3-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kunishige et al., US 2022/0344229, as applied to claim 1.
In re claim 3, though Kunishige fails to teach a first angle between the first side surface and the first chamfered surface is between 130 and 140 degrees, and a second angle between the second side surface and the first chamfered surface is between 130 and 140 degrees, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the angle (MPEP 2144.05).
Concerning claim 4, though Kunishige fails to teach the first corner region further comprises a first corner of the substrate, a first side surface of the substrate, and a second side surface of the substrate, the first and second side surfaces of the substrate intersect at the first corner of the substrate, a first perpendicular distance between the first corner of the substrate and the first chamfered surface of the passivation layer is greater than a second perpendicular distance between the first corner of the substrate and an intersection between a first plane and a second plane, and the first side surface lies within the first plane and the second side surface lies within the second plane, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative perpendicular distance (MPEP 2144.05).
Pertaining to claim 5, though Kunishige fails to teach the first perpendicular distance is between 1.1 and 10 times greater than the second perpendicular distance, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative perpendicular distance (MPEP 2144.05).
In claim 6, though Kunishige fails to teach the semiconductor device comprises at least one gallium nitride (GaN) transistor, it would have been obvious to one of ordinary skill in the art at the time of the invention to use GaN in the invention of Kunishige because GaN is a conventionally known and used in the art material. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
In re claim 7, though Kunishige, which teaches a polyimide (paragraph 0020), fails to teach the passivation layer comprises silicon nitride or silicon oxide, it would have been obvious to one of ordinary skill in the art at the time of the invention to use silicon nitride or silicon oxide in place of the polyimide in the invention of Kunishige because they are known equivalent materials. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
Concerning claim 8, though Kunishige fails to teach the substrate comprises at least one of GaN or silicon carbide (SiC) , it would have been obvious to one of ordinary skill in the art at the time of the invention to use GaN or SiC in the invention of Kunishige because GaN or SiC are conventionally known and used in the art materials. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Claim(s) 9-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kunishige et al., US 2022/0344229
Pertaining to claim 9, Kunishige (figures 1 & 2) teaches an integrated circuit die comprising:
a semiconductor substrate 10;
a semiconductor device (attached to 11/12) formed on the semiconductor substrate 10; and
a passivation layer 20 formed over the semiconductor substrate 10, the passivation layer 20 comprising a plurality of chamfered corners 20a disposed at respective corner regions of the integrated circuit die 10, wherein a first corner region of the integrated circuit die 10 includes a first chamfered corner 20a of the plurality of chamfered corners 30a and a first corner of the semiconductor substrate 10, wherein the chamfered surface 20a extends between a first side surface of the passivation layer 20 and a second side surface of the passivation layer 20, the first side surface lies within the first plane, and the second side surface lies within the second plane.
Though Kunishige fails to teach a first perpendicular distance between a chamfered surface of the first chamfered corner and the first corner of the semiconductor substrate is greater than a second perpendicular distance between the first corner of the semiconductor substrate and an intersection between a first plane and a second plane, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative perpendicular distance (MPEP 2144.05). a skilled artisan knows that controlling this distance affects the damage control.
In claim 10, though Kunishige fails to teach an angle between the chamfered surface and a side surface of the passivation layer that is adjacent to the chamfered surface is between 130 degrees and 140 degrees, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the angle (MPEP 2144.05).
Regarding claim 11, though Kunishige fails to teach the first perpendicular distance is between 1.1 and 10 times greater than the second perpendicular distance, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative perpendicular distance (MPEP 2144.05).
With respect to claim 12, though Kunishige fails to teach the semiconductor device comprises at least one gallium nitride (GaN) transistor, it would have been obvious to one of ordinary skill in the art at the time of the invention to use GaN in the invention of Kunishige because GaN is a conventionally known and used in the art material. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
As to claim 13, though Kunishige, which teaches a polyimide (paragraph 0020), fails to teach the passivation layer comprises silicon nitride or silicon oxide, it would have been obvious to one of ordinary skill in the art at the time of the invention to use silicon nitride or silicon oxide in place of the polyimide in the invention of Kunishige because they are known equivalent materials. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
In re claim 14, though Kunishige fails to teach the substrate comprises at least one of GaN or silicon carbide (SiC) , it would have been obvious to one of ordinary skill in the art at the time of the invention to use GaN or SiC in the invention of Kunishige because GaN or SiC are conventionally known and used in the art materials. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Concerning claim 15, though Kunishige fails to teach the semiconductor substrate comprises a SiC base substrate and at least one epitaxially-grown GaN layer formed over the SiC base substrate,, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Kunishige because it is conventionally known and used equivalent. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cite prior art teach similar inventions to the present one.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID A ZARNEKE whose telephone number is (571)272-1937. The examiner can normally be reached M-F.
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/DAVID A ZARNEKE/Primary Examiner, Art Unit 2891 6/22/26
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