DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I (Claims 1-11, 20, and 21) in the reply filed on 6/29/2026 is acknowledged.
Claims 12-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/29/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 11/30/2023 and 6/11/2026. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 6-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kumagai et al (US 2013/0313711 A1, hereafter Kumagai).
Re Claim 1, Kumagai discloses a package (FIG. 6; [0034]-[0040]) comprising:
a plurality of terminals (6, 10; [0027]);
a mark portion (5; [0022]) on which a mark (5) for identification is provided ([0022]); and
a base plate (1; [0021]),
wherein the plurality of terminals (6, 10) and the mark portion (5) are provided on one surface of the base plate (1, top surface; [0027]), and
wherein a smooth portion (2, top surface, specifically 0.5 μm region extending from each side of mark 5, hereafter just referred to as 2, top surface; [0024]), which is smoother than another portion (12a, 12b; [0024]) between the plurality of terminals (6, 10) and the mark portion (5; [0024]), is provided on the one surface (1, top surface; [0024]) and between at least one terminal (6, 10, any) among the plurality of terminals (6, 10) and the mark portion (5; [0036], in part).
Re Claim 2, Kumagai discloses the package according to Claim 1, while further disclosing wherein the smooth portion (2, top surface) is disposed so as to surround the mark portion (5; [0024]).
Re Claim 6, Kumagai discloses the package according to Claim 1, while further disclosing wherein a width of the smooth portion (2, top surface) is 0.25 micrometer (μm) or more and 1.0 μm or less ([0024], defined in Claim 1 to be specifically the 0.5 μm region of 2’s top surface extending from each side of mark 5).
Re Claim 7, Kumagai discloses the package according to Claim 1, while further disclosing wherein a surface of the smooth portion (2, top surface) has a similar configuration to that of a surface of the mark (5, negative space not marked up by laser; [0022]) for identification provided in the mark portion (5; [0022]).
Re Claim 8, Kumagai discloses the package according to Claim 1, while further disclosing wherein the base plate (1) is an insulating base plate ([0021]).
Re Claim 9, Kumagai discloses the package according to Claim 1, while further disclosing wherein the base plate (1) includes alumina ([0021]) or steatite.
Claims 1, 4-5, 10, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ozawa (US 2017/0287805 A1).
Re Claim 1, Ozawa discloses a package (FIG. 1; [0036]-[0046]) comprising:
a plurality of terminals (31; [0039]);
a mark portion (“identification mark”; [0107], formed in 53S) on which a mark for identification is provided ([0107]); and
a base plate (21; [0037]),
wherein the plurality of terminals (31) and the mark portion (“identification mark”) are provided on one surface of the base plate (21, top surface; [0039]), and
wherein a smooth portion (51, bottom surface; [0050]), which is smoother than another portion (52R; [0050]) between the plurality of terminals (31) and the mark portion (“identification mark”; [0050]), is provided on the one surface (21, top surface; [0050]) and between at least one terminal (31, any) among the plurality of terminals (31) and the mark portion (“identification mark”; [0050]).
Re Claim 4, Ozawa discloses the package according to Claim 1, while further disclosing wherein an arithmetic mean roughness of the smooth portion (51, bottom surface; [0050], < 0.1 μm) is 1/4 or less of an arithmetic mean roughness of the other portion (52R; [0050], chosen as appropriate from 0.1 μm or higher).
Re Claim 5, Ozawa discloses the package according to Claim 1, while further disclosing wherein an arithmetic mean roughness of the smooth portion (51, bottom surface) is 1.0 micrometer (μm) or less ([0050]).
Re Claim 10, Ozawa discloses the package according to Claim 1, while further disclosing wherein the mark portion (“identification mark”) is disposed in a central region of the one surface (21, top surface; [0107], by nature of being located in the smooth upper surface 53S, which is a central portion of 50).
Re Claim 20, Ozawa discloses a semiconductor device (10A; FIG. 1; [0036]-[0038]) comprising:
the package according to claim 1; and
a semiconductor chip (30; [0036]) mounted on the package ([0036]-[0038]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under U.S.C. 103 as being unpatentable over Kumagai, as applied to Claim 1, further in view of Frisa et al (US 2006/0269851 A1, hereafter Frisa).
Re Claim 3, Kumagai discloses the package according to Claim 1, but does not explicitly disclose wherein the mark (5) for identification is a data matrix.
However, Frisa teaches ([0030]) wherein the mark (24; [0030]) for identification is a data matrix ([0030]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the package as discussed with regard to Claim 1 with the limitations taught by Frisa to use a data matrix (Frisa: 24) as the mark for identification as a functionally equivalent means of predictably storing data to convey information as taught by Frisa ([0030]).
Claims 11 is rejected under U.S.C. 103 as being unpatentable over Ozawa, as applied to Claim 1, further in view of Kunitake et al (US 2024/0260257 A1, hereafter Kunitake).
Re Claim 11, Ozawa discloses the package according to Claim 1, while further disclosing wherein the one surface (21, top surface) is a surface opposite to a mounting surface (21, bottom surface; [0038], which a motherboard is mounted onto).
Ozawa does not explicitly disclose a semiconductor chip is to be mounted on the mounting surface (21, bottom surface).
However, Kunitake teaches a package (1200, 1201; FIGS. 36A-36B; [0677]) comprising wherein a semiconductor chip (1221; [0678]) is to be mounted on the mounting surface (1201, bottom surface; [0678], 1221 is effectively mounted on the bottom surface of 1201 by nature of the motherboard comprising 1221, direct physical contact not specified in claim limitations).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the package as discussed with regard to Claim 1 with the limitations taught by Kunitake to include other devices on the motherboard to act as DRAM for the computing device as a whole as taught by Kunitake ([0678]).
Claim 21 is rejected under U.S.C. 103 as being unpatentable over Ozawa, as applied to Claim 1, further in view of Chang et al (US 2023/0350600 A1, hereafter Chang).
Re Claim 21, Ozawa discloses an apparatus (10A and the mounted “motherboard”; FIG. 1; [0036]-[0038]) comprising a semiconductor device (10A) having the package according to claim 1, and a semiconductor chip (30; [0036], specifically a CPU, see [0040]) mounted on the package ([0036]-[0038]).
Ozawa does not explicitly disclose a processing device configured to process a signal output from the semiconductor device (10A).
However, Chang teaches an apparatus (FIG. 8; [0128]) comprising a processing device (102; [0128]) configured to process a signal output from the semiconductor device (11; [0128]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the package as discussed with regard to Claim 1 with the limitations taught by Chang to include a processing device (Chang: 102) as a part of the motherboard of Ozawa along with the CPU (Ozawa: 30) to allow for processing of the CPU signal into a control signal to operate the device at large, such as resulting in emission of colored light as taught by Chang ([0128]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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