Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action responds to the Application filed on 11/30/2023.
Claims 1-20 are pending.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. (U.S. Pub. No. 2017/0272077 A1) in view of Diba et al. (U.S. Pat. No. 6,466,049 B1).
As per claim 1, Sharma discloses:
A programmable logic device (PLD) comprising:
a plurality of slices (See Figure 2, i.e. splice 200), each slice comprising a plurality a lookup tables (LUT) and flip-flops (See Figure 2, i.e. LUT 202 & flipflop 206) configured to operate in response to a plurality of control signals (See Figure 2, i.e. control 207);
routing logic configured to selectively route the control signals to each of the plurality of slices (See Para [0034], i.e. programmable multiplexers (e.g., programmable multiplexers 212 and 214) for selecting desired signal paths for logic cell 200 and/or between logic cells 200).
Sharma does not teach the limitations: wherein the control signals comprise at least a signal selectively configurable as a clock enable signal or a local set-reset signal.
However, Diba discloses: wherein the control signals comprise at least a signal selectively configurable as a clock enable signal or a local set-reset signal (See Figure 3A, i.e. Set & reset use as Clock enable 369 CE, also use as set and reset of circuit 330, See Col 6; Line 14 to Col 7; Line15, i.e. switching circuit 330 includes a series of switches that allow either a set or a reset signal to be utilized as the CE control signal…switching circuit 330 facilitates the clock enable function provided by multiplexer 320 by selectively passing the unused SET control signal or RESET control signal to the select terminal of multiplexer 320… a first state, both the SET control signal and the RESET control signal are passed to the set terminal S and the reset terminal R, respectively, of flip flop 310… a second state, the SET control signal is passed to set terminal S of flip flop 310, and the RESET control signal is transmitted as the CE control signal).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Diba into
the teaching of Sharma because it would allow designer to incorporate clock enable
control circuit without requiring additional control signal structures in a programable
logic device (See Col 4; Lines 10-17 & Col 6; Lines 14-26).
As per claim 2, Sharma and Diba discloses all of the features of claim 1 as discloses above wherein Sharma also discloses wherein each LUT is a four input LUT (4-LUT) (See Figure 3, i.e. 4-LUT 202).
As per claim 3, Sharma and Diba discloses all of the features of claim 1 as discloses above wherein Sharma also discloses wherein the plurality of control signals comprises a plurality of clock signals, and wherein the routing logic comprises multiplexing circuitry configured to selectively route the clock signals to each of the plurality of slices as a clock input (See Para [0014], i.e. logic cells arranged within programmable function blocks (e.g., PFBs and/or PLBs), all driven by clock signals propagated throughout the PLD, See Para [0025], i.e. clock driver sources, See Para [0017]-[0021], i.e. the select logic for a multiplexer may be analyzed efficiently, See Para [0033]-[0034]).
As per claim 4, Sharma and Diba discloses all of the features of claim 1 as discloses above wherein Diba also discloses wherein the plurality of control signals comprises a plurality of clock enable signals, and wherein the routing logic comprises multiplexing circuitry configured to selectively route the clock enable signals to each of the plurality of slices as a clock enable input (See Figure 3A, i.e. Set & reset use as Clock enable 369 CE, also use as set and reset of circuit 330, See Col 6; Line 14 to Col 7; Line15, i.e. switching circuit 330 includes a series of switches that allow either a set or a reset signal to be utilized as the CE control signal…switching circuit 330 facilitates the clock enable function provided by multiplexer 320 by selectively passing the unused SET control signal or RESET control signal to the select terminal of multiplexer 320… a first state, both the SET control signal and the RESET control signal are passed to the set terminal S and the reset terminal R, respectively, of flip flop 310… a second state, the SET control signal is passed to set terminal S of flip flop 310, and the RESET control signal is transmitted as the CE control signal).
As per claim 5, Sharma and Diba discloses all of the features of claim 4 as discloses above wherein Diba also discloses wherein the plurality of control signals further comprises a control signal configurable for routing as a clock enable signal and/or local set-reset (LSR) signal (See Figure 3A, i.e. Set & reset use as Clock enable 369 CE, also use as set and reset of circuit 330, See Col 6; Line 14 to Col 7; Line15, i.e. switching circuit 330 includes a series of switches that allow either a set or a reset signal to be utilized as the CE control signal…switching circuit 330 facilitates the clock enable function provided by multiplexer 320 by selectively passing the unused SET control signal or RESET control signal to the select terminal of multiplexer 320… a first state, both the SET control signal and the RESET control signal are passed to the set terminal S and the reset terminal R, respectively, of flip flop 310… a second state, the SET control signal is passed to set terminal S of flip flop 310, and the RESET control signal is transmitted as the CE control signal).
As per claim 6, Sharma and Diba discloses all of the features of claim 1 as discloses above wherein Diba also discloses wherein the plurality of control signals comprises at least one local set-reset signal, and wherein the routing logic comprises multiplexing circuitry configured to selectively route the local set-reset signal to each of the plurality of slices as a local set-reset signal input (See Figure 3A, i.e. Set & reset use as Clock enable 369 CE, also use as set and reset of circuit 330, See Col 6; Line 14 to Col 7; Line15, i.e. switching circuit 330 includes a series of switches that allow either a set or a reset signal to be utilized as the CE control signal…switching circuit 330 facilitates the clock enable function provided by multiplexer 320 by selectively passing the unused SET control signal or RESET control signal to the select terminal of multiplexer 320… a first state, both the SET control signal and the RESET control signal are passed to the set terminal S and the reset terminal R, respectively, of flip flop 310… a second state, the SET control signal is passed to set terminal S of flip flop 310, and the RESET control signal is transmitted as the CE control signal).
As per claim 7, Sharma and Diba discloses all of the features of claim 1 as discloses above wherein Diba also discloses wherein the control signals comprise at least a first clock signal, a second clock signal, a first clock enable signal, a second clock enable signal, a first local set-reset signal, and the configurable signal (See Figure 3A, i.e. Set & reset use as Clock enable 369 CE, also use as set and reset of circuit 330, See Col 6; Line 14 to Col 7; Line15, i.e. switching circuit 330 includes a series of switches that allow either a set or a reset signal to be utilized as the CE control signal…switching circuit 330 facilitates the clock enable function provided by multiplexer 320 by selectively passing the unused SET control signal or RESET control signal to the select terminal of multiplexer 320… a first state, both the SET control signal and the RESET control signal are passed to the set terminal S and the reset terminal R, respectively, of flip flop 310… a second state, the SET control signal is passed to set terminal S of flip flop 310, and the RESET control signal is transmitted as the CE control signal).
As per claim 8, Sharma and Diba discloses all of the features of claim 7 as discloses above wherein Diba also discloses wherein the routing logic selectively routes one of the clock signals, one of the clock enable signals, and one of the local set-reset signals to each of the slices (See Figure 3A, i.e. Set & reset use as Clock enable 369 CE, also use as set and reset of circuit 330, See Col 6; Line 14 to Col 7; Line15, i.e. switching circuit 330 includes a series of switches that allow either a set or a reset signal to be utilized as the CE control signal…switching circuit 330 facilitates the clock enable function provided by multiplexer 320 by selectively passing the unused SET control signal or RESET control signal to the select terminal of multiplexer 320… a first state, both the SET control signal and the RESET control signal are passed to the set terminal S and the reset terminal R, respectively, of flip flop 310… a second state, the SET control signal is passed to set terminal S of flip flop 310, and the RESET control signal is transmitted as the CE control signal).
As per claim 9, Sharma and Diba discloses all of the features of claim 8 as discloses above wherein Sharma also discloses wherein the slices are configured to route each of the received control signals to one or more of the flip-flops on a corresponding control signal path without further multiplexing and/or routing logic (See Figure 2, i.e. LUT 202 & flipflop 206).
As per claim 10, Sharma and Diba discloses all of the features of claim 8 as discloses above wherein Sharma also discloses wherein a plurality of slice are clocked by the same clock signal (See Figure 2, i.e. control 207).
As per claim 11, Sharma and Diba discloses all of the features of claim 1 as discloses above wherein Sharma also discloses a method for programming the PLD of claim 1, comprising: generating configuration data to configure the routing logic of the PLD in accordance with a synthesized design; and programming the PLD with the configuration data (See Figure 3, i.e. 330, 360 – generation configuration data).
As per claim 12, Sharma discloses:
A method comprising: receiving a design identifying operations to be performed by a programmable logic device (PLD) (See Figure 3, i.e. 310);
synthesizing the design into a plurality of PLD components, wherein the synthesizing comprises detecting a logic function operation, a ripple arithmetic operation, and/or an extended logic function operation in the design (See Figure 3, i.e. 320 – synthesize design, See Para [0040]-[0043], i.e. identifying an abstract logic implementation of the user design as a plurality of logic components);
implementing the detected operation using logic cells within a programmable logic block (PLB) of the PLD (See Figure 3, i.e. 330 and Para [0044], i.e. mapping process that identifies components of PLD 100 that may be used to implement the user design), each logic cell comprising a lookup table (LUT) (See Figure 2, i.e. LUT 202, See Para [0033]-[0037]);
placing logic cells in the PLD (See Figure 3, i.e. 340 – place PLD components, See Para [0045], i.e. performs a placement process to assign the mapped netlist components to particular physical components);
and routing connections to the logic cells to pass a plurality of control signals, wherein the routing comprises evaluating control signal routing scenarios including implementing control signal routing logic in the programmable logic block and implementing the control signal routing logic on the PLD for input to the programmable logic block (See Figure 3, i.e. 350 – route connections, 360 – generate configuration data, 380 – configure PLD, See Para [0046]-[0048], i.e. performs a routing process to route connections (e.g., using routing resources 180) among the components of PLD 100 based on the placement layout determined in block 340 to realize the physical interconnections among the placed components, See Para [0034], i.e. programmable multiplexers (e.g., programmable multiplexers 212 and 214) for selecting desired signal paths for logic cell 200 and/or between logic cells 200).
Sharma does not teach the limitations: routing connections to the logic cells to pass a plurality of control signals comprising at least a signal selectively configurable as a clock enable signal or a local set-reset signal.
However, Diba discloses: routing connections to the logic cells to pass a plurality of control signals comprising at least a signal selectively configurable as a clock enable signal or a local set-reset signal (See Figure 3A, i.e. Set & reset use as Clock enable 369 CE, also use as set and reset of circuit 330, See Col 6; Line 14 to Col 7; Line15, i.e. switching circuit 330 includes a series of switches that allow either a set or a reset signal to be utilized as the CE control signal…switching circuit 330 facilitates the clock enable function provided by multiplexer 320 by selectively passing the unused SET control signal or RESET control signal to the select terminal of multiplexer 320… a first state, both the SET control signal and the RESET control signal are passed to the set terminal S and the reset terminal R, respectively, of flip flop 310… a second state, the SET control signal is passed to set terminal S of flip flop 310, and the RESET control signal is transmitted as the CE control signal).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Diba into
the teaching of Sharma because it would allow designer to incorporate clock enable
control circuit without requiring additional control signal structures in a programable
logic device (See Col 4; Lines 10-17 & Col 6; Lines 14-26).
As per claim 13, Sharma and Diba discloses all of the features of claim 1 as discloses above wherein Sharma also discloses configuring routing logic on the PLD to receive a plurality of control signals and selectively route the control signals to the PLB See Figure 3, i.e. 350 – route connections, 360 – generate configuration data, 380 – configure PLD, See Para [0046]-[0048], i.e. performs a routing process to route connections (e.g., using routing resources 180) among the components of PLD 100 based on the placement layout determined in block 340 to realize the physical interconnections among the placed components, See Para [0034], i.e. programmable multiplexers (e.g., programmable multiplexers 212 and 214) for selecting desired signal paths for logic cell 200 and/or between logic cells 200).
As per claim 14, Sharma and Diba discloses all of the features of claim 12 as discloses above wherein Sharma also discloses wherein routing connections further comprises routing a plurality of clock signals to the routing logic; and wherein the routing logic includes multiplexing circuitry configured to selectively route the clock signals to the PLD as a clock input (See Para [0014], i.e. logic cells arranged within programmable function blocks (e.g., PFBs and/or PLBs), all driven by clock signals propagated throughout the PLD, See Para [0025], i.e. clock driver sources, See Para [0017]-[0021], i.e. the select logic for a multiplexer may be analyzed efficiently, See Para [0033]-[0034]).
As per claim 15, Sharma and Diba discloses all of the features of claim 12 as discloses above wherein Diba also discloses wherein routing connections further comprises routing a plurality of clock enable signals to the routing logic; and wherein the routing logic includes multiplexing circuitry configured to selectively route the clock enable signals to the PLD as a clock enable input (See Figure 3A, i.e. Set & reset use as Clock enable 369 CE, also use as set and reset of circuit 330, See Col 6; Line 14 to Col 7; Line15, i.e. switching circuit 330 includes a series of switches that allow either a set or a reset signal to be utilized as the CE control signal…switching circuit 330 facilitates the clock enable function provided by multiplexer 320 by selectively passing the unused SET control signal or RESET control signal to the select terminal of multiplexer 320… a first state, both the SET control signal and the RESET control signal are passed to the set terminal S and the reset terminal R, respectively, of flip flop 310… a second state, the SET control signal is passed to set terminal S of flip flop 310, and the RESET control signal is transmitted as the CE control signal).
As per claim 16, Sharma and Diba discloses all of the features of claim 12 as discloses above wherein Diba also discloses wherein routing connections further comprises defining a configurable control signal path; and wherein the routing logic is configurable to receive a clock enable signal and/or a local set-reset (LSR) signal from the configurable control signal path and selectively route the received signal to a clock enable input or local set-reset input of the PLB (See Figure 3A, i.e. Set & reset use as Clock enable 369 CE, also use as set and reset of circuit 330, See Col 6; Line 14 to Col 7; Line15, i.e. switching circuit 330 includes a series of switches that allow either a set or a reset signal to be utilized as the CE control signal…switching circuit 330 facilitates the clock enable function provided by multiplexer 320 by selectively passing the unused SET control signal or RESET control signal to the select terminal of multiplexer 320… a first state, both the SET control signal and the RESET control signal are passed to the set terminal S and the reset terminal R, respectively, of flip flop 310… a second state, the SET control signal is passed to set terminal S of flip flop 310, and the RESET control signal is transmitted as the CE control signal).
As per claim 17, Sharma and Diba discloses all of the features of claim 12 as discloses above wherein Diba also discloses wherein routing connections further comprises routing at least one local set-reset signal to the routing logic; and wherein the routing logic includes multiplexing circuitry configured to selectively route the at least one local set-reset signal to the PLD as an LSR input (See Figure 3A, i.e. Set & reset use as Clock enable 369 CE, also use as set and reset of circuit 330, See Col 6; Line 14 to Col 7; Line15, i.e. switching circuit 330 includes a series of switches that allow either a set or a reset signal to be utilized as the CE control signal…switching circuit 330 facilitates the clock enable function provided by multiplexer 320 by selectively passing the unused SET control signal or RESET control signal to the select terminal of multiplexer 320… a first state, both the SET control signal and the RESET control signal are passed to the set terminal S and the reset terminal R, respectively, of flip flop 310… a second state, the SET control signal is passed to set terminal S of flip flop 310, and the RESET control signal is transmitted as the CE control signal).
As per claim 18, Sharma and Diba discloses all of the features of claim 12 as discloses above wherein Diba also discloses wherein routing connections further comprises routing at least a first clock signal, a second clock signal, a first clock enable signal, a second clock enable signal, a first local set-reset signal, and the configurable signal (See Figure 3A, i.e. Set & reset use as Clock enable 369 CE, also use as set and reset of circuit 330, See Col 6; Line 14 to Col 7; Line15, i.e. switching circuit 330 includes a series of switches that allow either a set or a reset signal to be utilized as the CE control signal…switching circuit 330 facilitates the clock enable function provided by multiplexer 320 by selectively passing the unused SET control signal or RESET control signal to the select terminal of multiplexer 320… a first state, both the SET control signal and the RESET control signal are passed to the set terminal S and the reset terminal R, respectively, of flip flop 310… a second state, the SET control signal is passed to set terminal S of flip flop 310, and the RESET control signal is transmitted as the CE control signal).
As per claim 19, Sharma and Diba discloses all of the features of claim 18 as discloses above wherein Diba also discloses wherein the routing connections further comprises routing one of the clock signals, one of the clock enable signals, and one of the local set-reset signals to the PLB (See Figure 3A, i.e. Set & reset use as Clock enable 369 CE, also use as set and reset of circuit 330, See Col 6; Line 14 to Col 7; Line15, i.e. switching circuit 330 includes a series of switches that allow either a set or a reset signal to be utilized as the CE control signal…switching circuit 330 facilitates the clock enable function provided by multiplexer 320 by selectively passing the unused SET control signal or RESET control signal to the select terminal of multiplexer 320… a first state, both the SET control signal and the RESET control signal are passed to the set terminal S and the reset terminal R, respectively, of flip flop 310… a second state, the SET control signal is passed to set terminal S of flip flop 310, and the RESET control signal is transmitted as the CE control signal).
As per claim 20, Sharma discloses:
A non-transitory machine-readable medium storing a plurality of machine-readable instructions which when executed by one or more processors of a computer system are adapted to cause the computer system to perform a computer-implemented method comprising (See Figure 1, i.e. processor & machine readable medium 136):
receiving a design identifying operations to be performed by a programmable logic device (PLD) (See Figure 3, i.e. 310);
synthesizing the design into a plurality of PLD components, wherein the synthesizing comprises detecting a logic function operation, a ripple arithmetic operation, and/or an extended logic function operation in the design (See Figure 3, i.e. 320 – synthesize design, See Para [0040]-[0043], i.e. identifying an abstract logic implementation of the user design as a plurality of logic components);
implementing the detected operation using logic cells within a programmable logic block (PLB) of the PLD (See Figure 3, i.e. 330 and Para [0044], i.e. mapping process that identifies components of PLD 100 that may be used to implement the user design), each logic cell comprising a lookup table (LUT); placing logic cells in the PLD (See Figure 2, i.e. LUT 202, See Para [0033]-[0037]); and
routing connections to the logic cells to pass a plurality of control signals wherein the routing comprises evaluating control signal routing scenarios including implementing control signal routing logic in the programmable logic block and implementing the control signal routing logic on the PLD for input to the programmable logic block (See Figure 3, i.e. 350 – route connections, 360 – generate configuration data, 380 – configure PLD, See Para [0046]-[0048], i.e. performs a routing process to route connections (e.g., using routing resources 180) among the components of PLD 100 based on the placement layout determined in block 340 to realize the physical interconnections among the placed components, See Para [0034], i.e. programmable multiplexers (e.g., programmable multiplexers 212 and 214) for selecting desired signal paths for logic cell 200 and/or between logic cells 200).
Sharma does not teach the limitations: routing connections to the logic cells to pass a plurality of control signals comprising at least a signal selectively configurable as a clock enable signal or a local set-reset signal.
However, Diba discloses: routing connections to the logic cells to pass a plurality of control signals comprising at least a signal selectively configurable as a clock enable signal or a local set-reset signal (See Figure 3A, i.e. Set & reset use as Clock enable 369 CE, also use as set and reset of circuit 330, See Col 6; Line 14 to Col 7; Line15, i.e. switching circuit 330 includes a series of switches that allow either a set or a reset signal to be utilized as the CE control signal…switching circuit 330 facilitates the clock enable function provided by multiplexer 320 by selectively passing the unused SET control signal or RESET control signal to the select terminal of multiplexer 320… a first state, both the SET control signal and the RESET control signal are passed to the set terminal S and the reset terminal R, respectively, of flip flop 310… a second state, the SET control signal is passed to set terminal S of flip flop 310, and the RESET control signal is transmitted as the CE control signal).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Diba into
the teaching of Sharma because it would allow designer to incorporate clock enable
control circuit without requiring additional control signal structures in a programable
logic device (See Col 4; Lines 10-17 & Col 6; Lines 14-26).
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM.
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/NHA T NGUYEN/Primary Examiner, Art Unit 2851
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