DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
EXAMINER’S AMENDMENT
Authorization for this examiner’s amendment was given in a telephonic conversation with attorney of record, Abazar Mireshghi (Reg. No. 70,811) on 09/23/2024, during which it was agreed to amend claim 1 as below and cancel claim 2.
Claim 1 recites:
A method of fabricating a display apparatus, the method comprising: providing a substrate having a first thin film transistor region and a second thin film transistor region; forming a first oxide semiconductor layer on the substrate in the first thin film transistor region; forming a first gate insulating layer covering the first oxide semiconductor layer in the first thin film transistor region; forming a second oxide semiconductor layer on the substrate in the second thin film transistor region; forming a second gate insulating layer on the substrate on which the first gate insulating layer and the second oxide semiconductor layer are previously formed; forming a first gate electrode in the first thin film transistor region and forming a second gate electrode in the second thin film transistor region, over the second gate insulating layer; and forming a first gate electrode stack and a second gate electrode stack by etching the first gate insulating layer, which is under the first gate electrode, and etching the second gate insulating layer, which is under the first and second gate electrodes, by using the first gate electrode and the second gate electrode as etching masks, wherein the forming of the first gate insulating layer comprises: forming an insulating layer for the first gate insulating layer on the substrate; and removing
Claims 2 has been cancelled.
Claims 3-13 will be examined as filed on 07/29/2026.
Response to Amendment
The Amendment filed on 07/30/2026 has been entered. Claims 1 and 3-20 remain pending in the application. Claims 14-20 have been withdrawn from consideration by the applicant, in the Response to Election / Restriction filed on 03/10/2026. Claim 2 has been canceled. Applicant’s amendments have overcome the specification informalities listed in the Non-Final Office Action mailed on 04/30/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation “wherein the buffer layer”. There is insufficient antecedent basis for this limitation. For the purpose of examination, this limitation of claim 13 will be interpreted as “wherein a buffer layer”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-7 and 9-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by disclosed prior art, Imai et al., (United States Patent Number, US 11,569,324 B2), hereinafter referenced as Imai.
Regarding claim 1, Imai teaches a method of fabricating a display apparatus, the method comprising: providing a substrate having a first thin film transistor region and a second thin film transistor region (Fig.4H, substrate element #1, first thin film transistor region is the left half of the figure, second thin film transistor region is the right half of the figure); forming a first oxide semiconductor layer on the substrate in the first thin film transistor region (Fig.4H, element #14(OS1)); forming a first gate insulating layer covering the first oxide semiconductor layer in the first thin film transistor region (Fig.4H, element #L1 covers element #14(OS1)); forming a second oxide semiconductor layer on the substrate in the second thin film transistor region (Fig.4H, element #24(OS2)); forming a second gate insulating layer on the substrate on which the first gate insulating layer and the second oxide semiconductor layer are previously formed (Fig.4G and 4H, element #L2 is formed after the formation of the layers #L1 and #24(OS2)); forming a first gate electrode in the first thin film transistor region (Fig.4H, element #16(M1)) and forming a second gate electrode in the second thin film transistor region (Fig.4H, element #26(M1)), over the second gate insulating layer (Fig.4H, element #16(M1) and #26(M1) are over element #L2); and forming a first gate electrode stack and a second gate electrode stack (Fig.4I, first gate electrode stack is formed by elements #15 and #16(M1), and second gate electrode stack is formed by elements #25(L2) and #26(M1)), by etching the first gate insulating layer, which is under the first gate electrode (Fig.4I, part of element #L1 is etched), and etching the second gate insulating layer, which is under the first and second gate electrodes (Fig.4I, part of element #L2 is etched), by using the first gate electrode and the second gate electrode as etching masks (Fig.4I, elements #16(M1) and #26(M1) are used as masks, column 9, rows 38-41), wherein the forming of the first gate insulating layer, comprises: forming an insulating layer for the first gate insulating layer on the substrate (Fig.4H, element #L1 is formed); and removing the insulating layer from the second thin film transistor region (Fig.4I, a portion of element #L1 is removed from the right side of the figure. Note that a broad interpretation of “removing the insulating layer” includes removing a portion of, a percentage of, or removing completely the insulating layer).
Regarding claim 4, Imai teaches the method of claim 1 as set forth in the anticipation rejection. Imai further teaches the method of claim 1, wherein a thickness of each of the first gate insulating layer and the second gate insulating layer is from about 600 Å to about 2000 Å (column 14, rows 46-53).
Regarding claim 5, Imai teaches the method of claim 1 as set forth in the anticipation rejection. Imai further teaches the method of claim 1, wherein each of the first gate insulating layer and the second gate insulating layer comprises at least one of silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2) (column 14, rows 32-34).
Regarding claim 6, Imai teaches the method of claims 1 and 5 as set forth in the anticipation rejection. Imai further teaches the method of claim 5, wherein the first gate insulating layer and the second gate insulating layer are formed of a same material (column 14, rows 38-39).
Regarding claim 7, Imai teaches the method of claims 1 and 5 as set forth in the anticipation rejection. Imai further teaches the method of claim 5, wherein the first gate insulating layer and the second gate insulating layer are formed of different materials from each other (column 14, rows 32-38).
Regarding claim 9, Imai teaches the method of claim 1 as set forth in the anticipation rejection. Imai further teaches the method of claim 1, wherein the second oxide semiconductor layer has a higher electron mobility than that of the first oxide semiconductor layer (Table 1, mobility of the second oxide semiconductor is higher than 20cm^2/Vs, and the mobility of the first oxide semiconductor is between 5 and 20 cm^2/Vs).
Regarding claim 10, Imai teaches the method of claims 1 and 9 as set forth in the anticipation rejection. Imai further teaches the method of claim 9, wherein the first oxide semiconductor layer has an electron mobility of about 1 to about 20 cm2/V·s, and wherein the second oxide semiconductor layer has an electron mobility of about 30 to about 80 cm2/V·s (Table 1, mobility of the second oxide semiconductor is higher than 20cm^2/Vs, and the mobility of the first oxide semiconductor is between 5 and 20 cm^2/Vs).
Regarding claim 11, Imai teaches the method of claims 1 and 9 as set forth in the anticipation rejection. Imai further teaches the method of claim 9, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises an indium-gallium-zinc oxide (InGaZnO), a hafnium-indium-zinc oxide (HfInZnO), an indium-tin-zinc oxide (InSnZnO), an aluminum-indium-tin oxide (AlInZnO), a gallium-tin-zinc oxide (GaSnZnO), a gallium-aluminum-zinc oxide (GaAlZnO), an aluminum-tin-zinc oxide (AlSnZnO), an indium-zinc oxide (InZnO), an indium-gallium oxide (InGaO), a zinc-tin oxide (ZnSnO), an aluminum-tin oxide (AlZnO), or any combination thereof (column 15, rows 46-55).
Regarding claim 12, Imai teaches the method of claims 1, 9 and 11 as set forth in the anticipation rejection. Imai further teaches the method of claim 11, wherein the first oxide semiconductor layer comprises InGaZnO, HfInZnO, AlInZnO, InZnO, InGaO, AlZnO, or any combination thereof (column 15, rows 46-59), and the second oxide semiconductor layer comprises InSnZnO, InSnGaZnO, GaSnZnO, ZnSnO, or any combination thereof (column 15, rows 50-51).
Regarding claim 13, Imai teaches the method of claim 1, as set forth in the anticipation rejection. Imai further teaches the method of claim 1, wherein the display apparatus further comprises: a first bottom metal layer in the first thin film transistor region (Fig.4E, element #12(ML)); and a second bottom metal layer in the second thin film transistor region (Fig.4E, element #22(ML)); wherein a buffer layer is on the first bottom metal layer and the second bottom metal layer (Fig.4H, element #3), and wherein the first gate electrode and the first bottom metal layer overlap one another in a thickness direction, and the second gate electrode and the second bottom metal layer overlap one another in the thickness direction (Fig.4I elements #12(ML) and #16(M1) overlap one another in vertical direction as seen in cross sectional view, and elements #22(ML) and #26(M1) overlap one another in vertical direction as seen in cross sectional view).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Imai.
Regarding claim 3, Imai teaches the method of claim 1 as set forth in the anticipation rejection. Imai further teaches the method of claim 1, further comprising: forming an interlayer insulating layer on the substrate (Fig.4J, element #5); forming, on the interlayer insulating layer, a first source electrode and a first drain electrode to be in contact with the first oxide semiconductor layer (Fig.4K, element #17(M2) and #18(M2)), and a second source electrode and a second drain electrode to be in contact with the second oxide semiconductor layer (Fig.4K, element #27(M2) and #28(M2)); forming a planarization layer on the interlayer insulating layer the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode (Fig.4L, element #7). In a different embodiment, Imai teaches forming an organic light-emitting device that is connected to the first source electrode or the first drain electrode on the planarization layer (Fig.11, transistor element #71, corresponds to the transistor in the first region, column 21, rows 37-39, column 24, rows 66-67, and column 25, rows 1-2, has the drain connected to an OLED, element #80, column 25, rows 19-22, see also Fig.5 for drain connection on the planarization layer). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teachings of Imai and disclose forming an organic light-emitting device that is connected to the first source electrode or the first drain electrode on the planarization layer. As disclosed by Imai, this allows the manufacture of pixels as part of an active matrix used in a display device.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Imai, in view of Isobe et al., (United States Patent Number US 6,620,658 B2) hereinafter referenced as Isobe.
Regarding claim 8, Imai teaches the method of claim 1 as set forth in the anticipation rejection. Imai does not teach teaches the method of claim 1 wherein a concentration of hydrogen in the first gate insulating layer is higher than a concentration of hydrogen in the second gate insulating layer. Isobe teaches wherein a concentration of hydrogen in the first gate insulating layer is higher than a concentration of hydrogen in the second gate insulating layer (column 3, rows 16-23). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Isobe and disclose a concentration of hydrogen in the first gate insulating layer is higher than a concentration of hydrogen in the second gate insulating layer. As disclosed by Isobe, hydrogen in the first insulating layer can be diffused into the semiconductor to adjust the threshold voltage of the transistor and relive internal stress, while the second insulating layer, having less hydrogen is denser and prevents oxygen diffusion to the outside (column 2, rows 63-67, column 3 rows 1-5).
Response to Arguments
Applicant’s arguments filed on 07/29/2026 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to claim 1 relate to the limitation “wherein the first gate insulating layer is not formed in the second thin film transistor region”, which has been removed from the claim (see examiner’s amendment above). This limitation raises new matter issues, since paragraph [0087] of the written description states: “the gate insulating layer 121 is removed from the region where the switching thin film transistor T2 is to be formed“. To be removed from the second thin film transistor region T2, the first gate insulating layer 121 must be previously formed in the second thin film transistor region. Furthermore, this limitation is not compatible with the limitation of claim 2 as filed on 07/29/2026 (and currently incorporated in claim 1):” removing the insulating layer from the second thin film transistor region”. As a result, the arguments with respect to claim 1 are moot.
Note that during the interview on 07/23/2026, the amendments to claim 1 presented and discussed were different from the ones filed on 07/29/2026 (see Office Action Appendix dated 07/30/2026). These amendments recite: “wherein the display apparatus further comprises a buffer layer on substrate, and wherein the first and second oxide semiconductor layers directly contact the buffer layer”. While no agreement was reached regarding the patentability of the claims, these amendments seem to overcome the 102 rejection of claim 1 as set forth in the Non-final Rejection filed on 04/30/2026.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (United States Patent Application Publication Number, US 2021/0036028 A1) teaches a method of fabricating a display apparatus, the method comprising: providing a substrate (Fig.11, element #110) having a first thin film transistor region (Fig.11, left side of the figure) and a second thin film transistor region (Fig.11, right side of the figure); forming a first oxide semiconductor layer on the substrate in the first thin film transistor region (Fig.11, element #350); forming a first gate insulating layer covering the first oxide semiconductor layer in the first thin film transistor region (Fig.15, element #370); forming a second oxide semiconductor layer on the substrate in the second thin film transistor region (Fig.11, element #450); forming a second gate insulating layer on the substrate on which the first gate insulating layer and the second oxide semiconductor layer are formed (Fig.15, element #IL1), forming a first gate electrode in the first thin film transistor region (Fig.17 element #310); and forming a second gate electrode in the second thin film transistor region over the second gate insulating layer(Fig.11 element #410).
Kim further teaches wherein the forming of the first gate insulating layer comprises: forming an insulating layer for the first gate insulating layer on the substrate (Fig.14, element #OXL); and removing the insulating layer from the second thin film transistor region (Fig.15, element #OXL is completely removed from the right half of the figure).
Park et al. (United States Patent Application Publication Number, US 2020/0075641 A1) teaches a method of fabricating a display apparatus, the method comprising: providing a substrate (Fig.6, element #110) having a first thin film transistor region (Fig.6, left side of the figure) and a second thin film transistor region (Fig.6, right side of the figure); forming a first oxide semiconductor layer on the substrate in the first thin film transistor region (Fig.7, element #120s); forming a first gate insulating layer covering the first oxide semiconductor layer in the first thin film transistor region (Fig.7, element #130a); forming a second oxide semiconductor layer on the substrate in the second thin film transistor region (Fig.7, element #120d); forming a second gate insulating layer on the substrate on which the first gate insulating layer and the second oxide semiconductor layer are previously formed (Fig.10, element #140s); forming a first gate electrode in the first thin film transistor region (Fig.10, element #150s) and forming a second gate electrode in the second thin film transistor region over the second gate insulating layer (Fig.10, element #150d); and forming a first gate electrode stack and a second gate electrode stack by using the first gate electrode and the second gate electrode as etching masks (Fig.11).
Park further teaches wherein the forming of the first gate insulating layer comprises: forming an insulating layer for the first gate insulating layer on the substrate; and removing the insulating layer from the second thin film transistor region (Fig.9, element #130, is removed completely from the second thin film transistor region).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRISTIAN A TIVARUS whose telephone number is (703)756-4688. The examiner can normally be reached Monday- Friday 8:00 AM -5:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
