DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-15 and 21-25) in the reply filed on March 13, 2026 is acknowledged.
Information Disclosure Statement
The references cited within the IDS documents have been considered.
IDS document dates: November 30, 2023; October 18, 2024.
Specification (Title)
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 21-23, and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Frougier et al. (US 2023/0170396 A1, hereinafter referred to as ‘Frougier’).
As to claim 1, Frougier teaches a method (figures 1-2J), comprising:
forming a stack of alternating oxide semiconductor channel layers (165, para. 0019) and sacrificial layers (210) over a substrate (140) – (see fig. 2A);
removing first portions of the sacrificial layers to expose channel regions of the oxide semiconductor channel layers (see fig. 2G);
forming a gate structure (125) wrapping around each of the channel regions of the oxide semiconductor channel layers (fig. 2H);
removing second portions of the sacrificial layers to expose source/drain regions of the oxide semiconductor channel layers (again see fig. 2G); and
forming source/drain electrodes (120/155) wrapping around and in contact with each of the source/drain regions of the oxide semiconductor channel layers, wherein the source/drain electrodes are made of a metal-containing material (see fig. 1).
As to claim 3, Frougier teaches the sacrificial layers (210) are made of a conductive material (α-SiGe, para. 0024).
As to claim 21, Frougier teaches a method (figures 1 and 2A-2J), comprising:
forming oxide semiconductor channel layers (165, para. 0019) vertically stacked one above another over a substrate (see also fig. 2A);
forming a gate structure (125) wrapping around each of channel regions of the oxide semiconductor channel layers (see also fig. 2H); and
forming source/drain electrodes (120/155) electrically connected to source/drain regions of the oxide semiconductor channel layers.
As to claim 22, Frougier teaches further comprising forming conductive layers (155) vertically stacked one above another over the substrate, wherein the conductive layers are interposed between adjacent two of the oxide semiconductor channel layers. See figure 1.
As to claim 23, Frougier teaches the source/drain electrodes interface with the conductive layers. See figure 1.
As to claim 25, Frougier teaches the source/drain electrodes (120/155) wraps around each of the source/drain regions of the oxide semiconductor channel layers. See figure 1.
Allowable Subject Matter
Claims 8-15 are allowable.
The following is an examiner’s statement of reasons for allowability.
The prior art of record does not teach or suggest the disclosed invention regarding a method, particularly characterized by the steps comprising:
removing first portions of the sacrificial layers to expose channel regions of the oxide semiconductor channel layers;
forming a gate structure wrapping around each of the channel regions of the oxide semiconductor channel layers; and
forming source/drain electrodes over source/drain regions of the oxide semiconductor channel layers, wherein second portions of the sacrificial layers remain on sidewalls of the gate structure after the source/drain electrodes are formed, as recited within independent claim 8. Claims 9-15 are dependent upon claim 8.
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Claims 2, 4, 5, 6, 7, and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record does not teach or suggest the disclosed invention regarding:
In claim 2, wherein the sacrificial layers are made of a dielectric material.
In claim 4, wherein the sacrificial layers have portions remaining on sidewalls of the gate structure after the source/drain electrodes are formed.
In claim 5, comprising performing an annealing process after removing the first portions of the sacrificial layers, such that the second portions of the sacrificial layers attract oxygen atoms from the source/drain regions of the oxide semiconductor channel layers to generate oxygen vacancies in the source/drain regions of the oxide semiconductor channel layers.
In claim 6, comprising performing an annealing process after forming the source/drain electrodes, such that the source/drain electrodes attract oxygen atoms from the source/drain regions of the oxide semiconductor channel layers to generate oxygen vacancies in the source/drain regions of the oxide semiconductor channel layers.
In claim 7, comprising:
transferring the substrate to a plasma chamber;
generating an ion plasma and a radical plasma through a radio frequency power source, wherein the ion plasma and the radical plasma comprises a same element; and
blocking the ion plasma through an ion filter, while leaving the radical plasma reaching exposed surfaces of the source/drain regions of the oxide semiconductor channel layers to form doped regions in the source/drain regions of the oxide semiconductor channel layers.
In claim 24, wherein the conductive layers comprise titanium nitride (TiN).
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see the attached form PTO-892 for pertinent cited art.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Scott B. Geyer (telephone: 571-272-1958). The examiner can normally be reached on Monday to Friday, 10AM - 4PM (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at: http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim (telephone: 571-272-8458). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only.
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/SCOTT B GEYER/ Primary Examiner, Art Unit 2812
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