DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of Species 1 in the reply filed on June 17, 2026 is acknowledged. The traversal is on the grounds that there is no undue burden on searching all claims. This is not found persuasive because the restriction requirement was drawn to separate species - stating that there is no burden for non-elected species is a mere conclusory statement without addressing if species are mutually exclusive or not; the applicant can also state on record that the species are obvious variants.
The requirement is still deemed proper and is therefore made FINAL.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The references cited within the IDS document (dated March 18, 2024) have been considered.
Specification (Title)
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Keeth et al. (US 2010/0059898 A1, hereinafter referred to as ‘Keeth’).
As to claim 1, Keeth teaches a semiconductor structure (figure 3), comprising device structures arranged in a stack, wherein the device structures comprise:
substrates (e.g. 390, 330, 320); and
through-substrate vias (TSVs) (326, 336, 396) located in the substrates and comprising first TSVs, wherein
each of the device structures comprises the corresponding substrate and the corresponding first TSV,
each of the first TSVs passes through the corresponding substrate,
the number of the TSVs (i.e. 4) in the endmost device structure (390) is less than the number (i.e. 12) of the TSVs in another of the device structures (330), and
the first TSV in the endmost device structure and the first TSV in another of the device structures are aligned with each other and electrically connected to each other.
As to claim 17, Keeth teaches each of the device structures comprises a wafer structure or a chip structure (see figure 3, e.g. 390, 330, 320).
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 2012/0309118 A1, hereinafter referred to as ‘Wang’).
As to claim 1, Wang teaches a semiconductor structure (figure 2), comprising device structures arranged in a stack, wherein the device structures comprise:
substrates (20, 30); and
through-substrate vias (TSVs) (21, 31) located in the substrates and comprising first TSVs, wherein
each of the device structures comprises the corresponding substrate and the corresponding first TSV,
each of the first TSVs passes through the corresponding substrate,
the number of the TSVs (i.e. 2) in the endmost device structure (30) is less than the number (i.e. 3) of the TSVs in another of the device structures (20), and
the first TSV in the endmost device structure and the first TSV in another of the device structures are aligned with each other and electrically connected to each other.
As to claim 2, Wang teaches the number (2) of the TSVs in the endmost device structure is less than the number (3) of the TSVs in each of the remaining device structures, and
the first TSV in the endmost device structure and the first TSVs in the remaining device structures are aligned with each other and electrically connected to each other. See figure 2.
Claims 1, 2, 7, 10, 11, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Youn et al. (US 2011/0156232 A1, hereinafter referred to as ‘Youn’).
As to claim 1, Youn teaches a semiconductor structure (figure 6A), comprising device structures arranged in a stack, wherein the device structures comprise:
substrates (5110, 5210); and
through-substrate vias (TSVs) (e.g. 5121_1, 5221_1) located in the substrates and comprising first TSVs, wherein
each of the device structures comprises the corresponding substrate and the corresponding first TSV,
each of the first TSVs passes through the corresponding substrate,
the number of the TSVs (i.e. 2) in the endmost device structure (5210) is less than the number (i.e. 4) of the TSVs in another of the device structures (5110), and
the first TSV in the endmost device structure and the first TSV in another of the device structures are aligned with each other and electrically connected to each other.
As to claim 2, Youn teaches the number (2) of the TSVs in the endmost device structure (5210) is less than the number (4) of the TSVs in each of the remaining device structures (5110), and
the first TSV in the endmost device structure and the first TSVs in the remaining device structures are aligned with each other and electrically connected to each other. See figure 6A.
As to claim 7, Youn teaches dielectric layers located on the substrates; and bonding pads located in the dielectric layers. See annotated figure 6A below.
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As to claim 10, Youn teaches the bonding pads and the first TSVs are aligned with each other, as shown in figure 6A.
As to claim 11, Youn teaches the bonding pads and the first TSVs aligned with each other are electrically connected to each other, as shown in figure 6A.
As to claim 17, Youn teaches each of the device structures comprises a wafer structure or a chip structure, as shown in figure 6A.
Allowable Subject Matter
Claims 3, 6, 8, 9, 12, 18, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. (Claims 4, 5, 13, 15, 16, and 20 are also objected to as being dependent upon objected claims.)
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see the attached form PTO-892 for pertinent cited art.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Scott B. Geyer (telephone: 571-272-1958). The examiner can normally be reached on Monday to Friday, 10AM - 4PM (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at: http://www.uspto.gov/interviewpractice.
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/SCOTT B GEYER/ Primary Examiner, Art Unit 2812
Prosecution Insights