DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant's response of 09/01/2026 has been acknowledged. Claims 1, 8, and 15 have been amended. No new matter has been added.
This office action considers claims 1-20 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant’s arguments filed 08/24/2026 with respect to the rejection of claim 1 have been fully considered but are moot in view of the new grounds of rejection.
Applicant’s arguments filed 08/24/2026 with respect to the rejection of claims 8 and 15 have been fully considered and are persuasive. All rejections for claims 8-20 have been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Rabkin et al. (US 20160181272 A1 – hereinafter Rabkin-272) in view of Rabkin et al. (US 9177966 B1 – hereinafter Rabkin-966), Kim et al. (US 20220068954 A1 – hereinafter Kim), and Ishihara et al. (US 20200176474 A1 – hereinafter Ishihara)
Regarding independent claim 1, Rabkin-272 teaches:
(Currently Amended) A three-dimensional (3D) NAND memory
structure ([Title] – “Fabricating 3D NAND Memory Having Monolithic Crystalline Silicon Vertical NAND Channel” – hereinafter ‘MEM’) comprising:
a silicon substrate (201 – Fig. 8G – [0087] – “the silicon substrate 201”);
a plurality of alternating material layers (Fig. 4C annotated, see below –
hereinafter ‘VS’) arranged in a vertical stack on the silicon substrate (201), wherein a channel hole (C0 – Fig. 5A – [0049] – “column C0”) extends through the plurality of alternating material layers (VS) to the silicon substrate (201), and wherein the channel hole (C0) is perpendicular to the plurality of alternating material layers (VS – Fig. 4C shows this); and
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a channel (Fig. 5A annotated, see below – hereinafter ‘CH’) inside the channel hole (C0), wherein the channel comprises:
a tunneling layer (696 – Fig. 5A – [0062] – “layer 696 comprises a layer of Al.sub.2O.sub.3 and a layer of SiO.sub.2”) around an interior of the channel hole (C0 – Fig. 5A shows this), the tunneling layer (696) contacting the plurality of alternating material layers (VS – Fig. 5A shows this); and
a hollow epitaxial silicon core (699 – Fig. 5B – [0104] – “the mono-silicon crystalline vertical NAND channel 699 is formed using vapor phase epitaxial
growth to grow the mono-crystalline silicon from the bottom of the vertically-oriented channel upwards to the top of the vertically-oriented channel”) inside the tunneling layer (696), wherein the hollow epitaxial silicon core (699) contacts the silicon substrate (201 – Fig. 5C shows);
a core gap material ([0073] – “Step 710a is just one example of the initial filling of the memory holes” – hereinafter ‘CGM’) within the hollow epitaxial silicon core (699); and
a layer of epitaxial silicon that extends beyond the channel hole, wherein the layer of epitaxial silicon is between the silicon substrate and the plurality of alternating material layers, wherein an upper surface of the layer of epitaxial silicon is directly connected with the hollow epitaxial silicon core (699) and the core gap material (CGM), and wherein a portion of the layer of epitaxial silicon, aligned beneath the hollow epitaxial silicon core (699), extends through an oxide layer formed between the layer of epitaxial silicon and the silicon substrate.
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Rabkin-272 does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Rabkin-966 teaches
a hollow (1 – Fig. 1B – [38 = 7:3] – “the hollow channel 1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the hollow structure as taught by Rabkin-966 into Rabkin-272.
An ordinary artisan would have been motivated to use the known technique of Rabkin-966 in the manner set forth above to produce the predictable result of [1 – 50:55] – “a hollow semiconductor channel layer surrounding a middle region in the at least one opening, and forming at least one of an air gap or a low-k insulating material having a dielectric constant of less than 3.9 located in the middle region.” This hollow structure provides room for other materials if required.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Rabkin-272 and Rabkin-966 do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Kim teaches
a layer of epitaxial silicon (910 – Fig. 2B – [0051] – “memory-side substrate
semiconductor layer 910 can be an epitaxial silicon layer”) that extends beyond the channel hole (60 – Fig. 2 – [0052] – “vertical semiconductor channel 60” – this corresponds to a channel hole), wherein the layer of epitaxial silicon (910) is between the silicon substrate (908 – Fig. 2 – [0051] – “memory die 900 can include a memory-side substrate 908 that includes a memory-side substrate semiconductor layer 910”) and the plurality of alternating material layers (32 and 46 – Fig. 2 – [0083] – “the memory die 900 comprises: an alternating stack of insulating layers 32 and electrically conductive layers 46 located on a memory-side substrate 908”), wherein an upper surface of the layer of epitaxial silicon (910) is directly connected (kim (Fig. 2B shows direct contact) with the hollow epitaxial silicon core and the core gap material.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the epitaxial silicon structure as taught by Kim into Rabkin-272 and Rabkin-966.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable result of [0042] – “a three-dimensional memory device containing a logic (e.g., driver) circuit containing vertical field effect transistors and methods of manufacturing the same, the various aspects of which are described below. The vertical field effect transistors occupy less space over the substrate than lateral (i.e., horizontal) field effect transistor.”
Rabkin-272, Rabkin-966, and Kim do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Ishihara teaches
a portion of the layer of epitaxial silicon (SB – Fig. 4B – [0038] – “semiconductor base SB is formed at the bottom of the memory hole MH. The semiconductor base SB is, for example, a P-type or undoped silicon layer, and is epitaxially grown on the source layer SL”), aligned beneath the hollow epitaxial silicon core, extends through an oxide layer (13 – Fig. 4B – [0035] – “interlayer insulating films 13, 15 are, for example, silicon oxide films”) formed between the layer of epitaxial silicon (SB) and the silicon substrate (SL – Fig. 4B – [0023] – “source layer SL may be a conductive polysilicon layer provided on a silicon substrate with an interlayer insulating film (not shown) interposed therebetween”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the epitaxial silicon structure as taught by Ishihara into Rabkin-272, Rabkin-966, and Kim.
An ordinary artisan would have been motivated to use the known technique of Ishihara in the manner set forth above to produce the predictable result of providing an insulating material between the silicon substrate and the gate.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 2, Rabkin-272 as modified by Rabkin-966, Kim, and Ishihara, teaches claim 1 from which claim 2 depends. Rabkin-272 further teaches
(original) The 3D NAND memory structure of claim 1, wherein the
silicon substrate (201) comprises a single-crystal silicon from which the hollow (1) epitaxial silicon core (699) is grown through the channel hole ([0055] – “The mono-crystalline silicon channel 699 is in direct physical and direct electrical contact with the substrate 201, which may be formed from silicon”).
Rabkin-272, Kim, and Ishihara do not expressly disclose the other limitations of claim 2.
However, in an analogous art, Rabkin-966 teaches
a hollow (1 – Fig. 1B – [38 = 7:3] – “the hollow channel 1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the hollow structure as taught by Rabkin-966 into Rabkin-272, Kim, and Ishihara.
An ordinary artisan would have been motivated to use the known technique of Rabkin-966 in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 3, Rabkin-272 as modified by Rabkin-966, Kim, and Ishihara, teaches claim 1 from which claim 3 depends. Rabkin-272 further teaches
(original) The 3D NAND memory structure of claim 1, wherein the
plurality of alternating material layers (VS) comprise alternating layers of an oxide material (D0-D8 – Fig. 8G – [0118] – “horizontal layers D0-D8 in the stack 1000 may be silicon oxide”) and a nitride material (SAC0-SAC7 – Fig. 8G – [0118] – “Horizontal layers SAC0-SAC7 may be silicon nitride”).
Regarding claim 4, Rabkin-272 as modified by Rabkin-966, Kim, and Ishihara, teaches claim 1 from which claim 4 depends. Rabkin-272 further teaches
(original) The 3D NAND memory structure of claim 1, wherein the
plurality of alternating material layers (VS) comprise alternating layers of an oxide material (D0-D8) and a metal (WL0- WL6 – Fig. 3B – [0033] – “Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WL1, and control gate 106CG is connected to word line WL0”), wherein the metal forms a gate electrode (CG – Fig. 3B – [0033] – “Each of the transistors 100, 102, 104 and 106 has a control gate (CG)”) for individual memory cells ({[0033] – “For example, transistor 100 has control gate 100CG charge storage region 1600CSR. Transistor 102 includes control gate 102CG and a charge storage region 102CSR. Transistor 104 includes control gate 104CG and charge storage region 104CSR. Transistor 106 includes a control gate 106CG and a charge storage region 106CSR”, {[0034] – “Note that although FIG. 1 shows four memory cells in the NAND string, the use of four memory cells is only provided as an example. A NAND string can have fewer than four memory cells or more than four memory cells”} – each transistor in Fig. 1 represent an individual memory cell).
Regarding claim 5, Rabkin-272 as modified by Rabkin-966, Kim, and Ishihara, teaches claim 4 from which claim 5 depends. Rabkin-272 further teaches
epitaxial silicon core (699).
Rabkin-272, Kim, and Ishihara do not expressly disclose the other limitations of claim 5.
However, in an analogous art, Rabkin-966 teaches
(original) The 3D NAND memory structure of claim 1, wherein the hollow (1)
epitaxial silicon core extends into the silicon substrate (100 – Fig. 2 – [5:10-11] – “substrate 100 can be any semiconducting substrate known in the art, such as monocrystalline silicon” – Fig. 2 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the hollow structure as taught by Rabkin-966 into Rabkin-272, Kim, and Ishihara.
An ordinary artisan would have been motivated to use the known technique of Rabkin-966 in the manner set forth above to produce the predictable result as stated above in claim 1.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Rabkin-272 in view of Rabkin-966, Kim, Ishihara, and Wu (US 20210225865 A1 – hereinafter Wu).
Regarding claim 6, Rabkin-272 as modified by Rabkin-966, Kim, and Ishihara, teaches claim 1 from which claim 6 depends. Rabkin-272 further teaches
epitaxial silicon core (699).
Rabkin-272, Kim, and Ishihara do not expressly disclose the other limitations of claim 6.
However, in an analogous art, Rabkin-966 teaches
a hollow (1 – Fig. 1B – [38 = 7:3] – “the hollow channel 1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the hollow structure as taught by Rabkin-966 into Rabkin-272, Kim, and Ishihara.
An ordinary artisan would have been motivated to use the known technique of Rabkin-966 in the manner set forth above to produce the predictable result as stated above in claim 1.
Rabkin-272, Kim, Ishihara, and Rabkin-966 do not expressly disclose the other limitations of claim 6.
However, in an analogous art, Wu teaches
(previously presented) The 3D NAND memory structure of claim 1, wherein
the layer of epitaxial silicon (184) connects the hollow epitaxial silicon core to a plurality of other channels (150 – Fig. 10 – [0031] – “channel holes 150”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the epitaxial silicon structure as taught by Wu into Rabkin-272, Kim, Ishihara, and Rabkin-966.
An ordinary artisan would have been motivated to use the known technique of Wu in the manner set forth above to produce the predictable result of [0004] – “a cavity is etched and selective epitaxial growth of single crystalline silicon and polysilicon is performed in the cavity.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 7, Rabkin-272 as modified by Rabkin-966, Kim, Ishihara, and Wu, teaches claim 6 from which claim 7 depends. Rabkin-272 further teaches
(original) The 3D NAND memory structure of claim 6, further
comprising a support structure (NSA0 – NSA5 – Fig. 1 – {[0043] – “U-shaped NAND strings NSA0 to NSA5”}, {[0097] – “NAND strings in the memory holes serve as anchors which support the silicon oxide layers”}) that extends through the plurality of alternating material layers (VS) and the layer of epitaxial silicon (184), wherein the support structure (NSA0 – NSA5) extends into the silicon substrate.
Rabkin-272, Kim, and Ishihara do not expressly disclose the other limitations of claim 7.
However, in an analogous art, Rabkin-966 teaches
wherein the support structure extends (100 – Fig. 2 show this) into the silicon substrate (100).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the support structure as taught by Rabkin-966 into Rabkin-272, Kim, and Ishihara.
An ordinary artisan would have been motivated to use the known technique of Rabkin-966 in the manner set forth above to produce the predictable result providing more stable support to the alternating layers.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Rabkin-272, Kim, Ishihara, and Rabkin-966 do not expressly disclose the other limitations of claim 7.
However, in an analogous art, Wu teaches
layer of epitaxial silicon (184).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the epitaxial silicon structure as taught by Wu into Rabkin-272, Kim, Ishihara, and Rabkin-966.
An ordinary artisan would have been motivated to use the known technique of Wu in the manner set forth above to produce the predictable result of as stated above in claim 6.
Allowable Subject Matter
Claims 8-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
In reference to claim 8, the prior art of record to the examiner’s knowledge does not teach or render obvious, at least to one skilled in the art, the instant invention regarding removing, through the gap, the channel liner from the channel hole while the core gap material is present within the center of the channel hole in combination with the other recited limitations.
Claims 9-14 depend on claim 8 and are therefore allowable.
In reference to claim 15, the prior art of record to the examiner’s knowledge does not teach or render obvious, at least to one skilled in the art, the instant invention regarding removing, through the gap, the channel liner from the channel hole while the core gap material is present within the center of the channel hole in combination with the other recited limitations.
Claims 16-20 depend on claim 15 and are therefore allowable.
Pertinent Art
For the benefits of the Applicant, US 20210118901 A1 and US 20200020713 A1 are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including the core gap material remaining.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
