DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant's response of 05/11/2026 has been acknowledged. Claims 1, 6, 8, 15, 17, and 18 have been amended. No new matter has been added.
This office action considers claims 1-20 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant’s arguments filed 05/11/2026 with respect to the rejection of claims 1, 8, and 15 have been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Rabkin et al. (US 20160181272 A1 – hereinafter Rabkin-272) in view of Rabkin et al. (US 9177966 B1 – hereinafter Rabkin-966) and Kim et al. (US 20220068954 A1 – hereinafter Kim).
Regarding independent claim 1, Rabkin-272 teaches:
(Currently Amended) A three-dimensional (3D) NAND memory
structure ([Title] – “Fabricating 3D NAND Memory Having Monolithic Crystalline Silicon Vertical NAND Channel” – hereinafter ‘MEM’) comprising:
a silicon substrate (201 – Fig. 8G – [0087] – “the silicon substrate 201”);
a plurality of alternating material layers (Fig. 4C annotated, see below –
hereinafter ‘VS’) arranged in a vertical stack on the silicon substrate (201), wherein a channel hole (C0 – Fig. 5A – [0049] – “column C0”) extends through the plurality of alternating material layers (VS) to the silicon substrate (201), and wherein the channel hole (C0) is perpendicular to the plurality of alternating material layers (VS – Fig. 4C shows this); and
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a channel (Fig. 5A annotated, see below – hereinafter ‘CH’) inside the channel hole (C0), wherein the channel comprises:
a tunneling layer (696 – Fig. 5A – [0062] – “layer 696 comprises a layer of Al.sub.2O.sub.3 and a layer of SiO.sub.2”) around an interior of the channel hole (C0 – Fig. 5A shows this), the tunneling layer (696) contacting the plurality of alternating material layers (VS – Fig. 5A shows this); and
a hollow epitaxial silicon core (699 – Fig. 5B – [0104] – “the mono-silicon crystalline vertical NAND channel 699 is formed using vapor phase epitaxial
growth to grow the mono-crystalline silicon from the bottom of the vertically-oriented channel upwards to the top of the vertically-oriented channel”) inside the tunneling layer (696), wherein the hollow epitaxial silicon core (699) contacts the silicon substrate (201 – Fig. 5C shows);
a core gap material ([0073] – “Step 710a is just one example of the initial filling of the memory holes” – hereinafter ‘CGM’) within the hollow epitaxial silicon core (699); and
a layer of epitaxial silicon that extends beyond the channel hole, wherein the layer of epitaxial silicon is between the silicon substrate and the plurality of alternating material layers, wherein an upper surface of the layer of epitaxial silicon is directly connected with the hollow epitaxial silicon core (699) and the core gap material (CGM).
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Rabkin-272 does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Rabkin-966 teaches
a hollow (1 – Fig. 1B – [38 = 7:3] – “the hollow channel 1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the hollow structure as taught by Rabkin-966 into Rabkin-272.
An ordinary artisan would have been motivated to use the known technique of Rabkin-966 in the manner set forth above to produce the predictable result of [1 – 50:55] – “a hollow semiconductor channel layer surrounding a middle region in the at least one opening, and forming at least one of an air gap or a low-k insulating material having a dielectric constant of less than 3.9 located in the middle region.” This hollow structure provides room for other materials if required.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Rabkin-272 and Rabkin-966 do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Kim teaches
a layer of epitaxial silicon (910 – Fig. 2B – [0051] – “memory-side substrate
semiconductor layer 910 can be an epitaxial silicon layer”) that extends beyond the channel hole (60 – Fig. 2 – [0052] – “vertical semiconductor channel 60” – this corresponds to a channel hole), wherein the layer of epitaxial silicon (910) is between the silicon substrate (908 – Fig. 2 – [0051] – “memory die 900 can include a memory-side substrate 908 that includes a memory-side substrate semiconductor layer 910”) and the plurality of alternating material layers (32 and 46 – Fig. 2 – [0083] – “the memory die 900 comprises: an alternating stack of insulating layers 32 and electrically conductive layers 46 located on a memory-side substrate 908”), wherein an upper surface of the layer of epitaxial silicon (910) is directly connected (kim (Fig. 2B shows direct contact) with the hollow epitaxial silicon core and the core gap material.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the epitaxial silicon structure as taught by Kim into Rabkin-272 and Rabkin-966.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable result of [0042] – “a three-dimensional memory device containing a logic (e.g., driver) circuit containing vertical field effect transistors and methods of manufacturing the same, the various aspects of which are described below. The vertical field effect transistors occupy less space over the substrate than lateral (i.e., horizontal) field effect transistor.”
Regarding claim 2, Rabkin-272 as modified by Rabkin-966 and Kim, teaches claim 1 from which claim 2 depends. Rabkin-272 further teaches
(Original) The 3D NAND memory structure of claim 1, wherein the
silicon substrate (201) comprises a single-crystal silicon from which the hollow (1) epitaxial silicon core (699) is grown through the channel hole ([0055] – “The mono-crystalline silicon channel 699 is in direct physical and direct electrical contact with the substrate 201, which may be formed from silicon”).
Rabkin-272 and Kim do not expressly disclose the other limitations of claim 2.
However, in an analogous art, Rabkin-966 teaches
a hollow (1 – Fig. 1B – [38 = 7:3] – “the hollow channel 1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the hollow structure as taught by Rabkin-966 into Rabkin-272 and Kim.
An ordinary artisan would have been motivated to use the known technique of Rabkin-966 in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 3, Rabkin-272 as modified by Rabkin-966 and Kim, teaches claim 1 from which claim 3 depends. Rabkin-272 further teaches
(Original) The 3D NAND memory structure of claim 1, wherein the
plurality of alternating material layers (VS) comprise alternating layers of an oxide material (D0-D8 – Fig. 8G – [0118] – “horizontal layers D0-D8 in the stack 1000 may be silicon oxide”) and a nitride material (SAC0-SAC7 – Fig. 8G – [0118] – “Horizontal layers SAC0-SAC7 may be silicon nitride”).
Regarding claim 4, Rabkin-272 as modified by Rabkin-966 and Kim, teaches claim 1 from which claim 4 depends. Rabkin-272 further teaches
(Original) The 3D NAND memory structure of claim 1, wherein the
plurality of alternating material layers (VS) comprise alternating layers of an oxide material (D0-D8) and a metal (WL0- WL6 – Fig. 3B – [0033] – “Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WL1, and control gate 106CG is connected to word line WL0”), wherein the metal forms a gate electrode (CG – Fig. 3B – [0033] – “Each of the transistors 100, 102, 104 and 106 has a control gate (CG)”) for individual memory cells ({[0033] – “For example, transistor 100 has control gate 100CG charge storage region 1600CSR. Transistor 102 includes control gate 102CG and a charge storage region 102CSR. Transistor 104 includes control gate 104CG and charge storage region 104CSR. Transistor 106 includes a control gate 106CG and a charge storage region 106CSR”, {[0034] – “Note that although FIG. 1 shows four memory cells in the NAND string, the use of four memory cells is only provided as an example. A NAND string can have fewer than four memory cells or more than four memory cells”} – each transistor in Fig. 1 represent an individual memory cell).
Regarding claim 5, Rabkin-272 as modified by Rabkin-966 and Kim, teaches claim 4 from which claim 5 depends. Rabkin-272 further teaches
epitaxial silicon core (699).
Rabkin-272 and Kim do not expressly disclose the other limitations of claim 5.
However, in an analogous art, Rabkin-966 teaches
(Original) The 3D NAND memory structure of claim 1, wherein the hollow (1)
epitaxial silicon core extends into the silicon substrate (100 – Fig. 2 – [5:10-11] – “substrate 100 can be any semiconducting substrate known in the art, such as monocrystalline silicon” – Fig. 2 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the hollow structure as taught by Rabkin-966 into Rabkin-272 and Kim.
An ordinary artisan would have been motivated to use the known technique of Rabkin-966 in the manner set forth above to produce the predictable result as stated above in claim 1.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Rabkin-272 in view of Rabkin-966, Kim, and Wu (US 20210225865 A1 – hereinafter Wu).
Regarding claim 6, Rabkin-272 as modified by Rabkin-966 and Kim, teaches claim 1 from which claim 6 depends. Rabkin-272 further teaches
epitaxial silicon core (699).
Rabkin-272 and Kim do not expressly disclose the other limitations of claim 6.
However, in an analogous art, Rabkin-966 teaches
a hollow (1 – Fig. 1B – [38 = 7:3] – “the hollow channel 1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the hollow structure as taught by Rabkin-966 into Rabkin-272 and Kim.
An ordinary artisan would have been motivated to use the known technique of Rabkin-966 in the manner set forth above to produce the predictable result as stated above in claim 1.
Rabkin-272, Kim, and Rabkin-966 do not expressly disclose the other limitations of claim 6.
Rabkin-272, Rabkin-966, and Kim do not expressly disclose the other limitations of claim 6.
However, in an analogous art, Wu teaches
(Currently Amended) The 3D NAND memory structure of claim 1,
wherein the layer of epitaxial silicon (184) connects the hollow epitaxial silicon core to a plurality of other channels (150 – Fig. 10 – [0031] – “channel holes 150”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the epitaxial silicon structure as taught by Wu into Rabkin-272, Rabkin-966, and Kim.
An ordinary artisan would have been motivated to use the known technique of Wu in the manner set forth above to produce the predictable result of [0004] – “a cavity is etched and selective epitaxial growth of single crystalline silicon and polysilicon is performed in the cavity.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 7, Rabkin-272 as modified by Rabkin-966, Kim, and Wu, teaches claim 6 from which claim 7 depends. Rabkin-272 further teaches
(Original) The 3D NAND memory structure of claim 6, further
comprising a support structure (NSA0 – NSA5 – Fig. 1 – {[0043] – “U-shaped NAND strings NSA0 to NSA5”}, {[0097] – “NAND strings in the memory holes serve as anchors which support the silicon oxide layers”}) that extends through the plurality of alternating material layers (VS) and the layer of epitaxial silicon (184), wherein the support structure (NSA0 – NSA5) extends into the silicon substrate.
Rabkin-272 and Kim do not expressly disclose the other limitations of claim 7.
However, in an analogous art, Rabkin-966 teaches
wherein the support structure extends (100 – Fig. 2 show this) into the silicon substrate (100).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the support structure as taught by Rabkin-966 into Rabkin-272 and Kim.
An ordinary artisan would have been motivated to use the known technique of Rabkin-966 in the manner set forth above to produce the predictable result providing more stable support to the alternating layers.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Rabkin-272, Kim, and Rabkin-966 do not expressly disclose the other limitations of claim 7.
However, in an analogous art, Wu teaches
layer of epitaxial silicon (184).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the epitaxial silicon structure as taught by Wu into Rabkin-272, Kim, and Rabkin-966.
An ordinary artisan would have been motivated to use the known technique of Wu in the manner set forth above to produce the predictable result of as stated above in claim 6.
Claims 8, 14-15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Rabkin-272 in view of Rabkin-966 and Yang (US 20210118901 A1 – hereinafter Yang).
Regarding independent claim 8, Rabkin-272 teaches:
(Currently Amended) A method of fabricating a three-dimensional
(3D) NAND memory structure ([Title] – “Fabricating 3D NAND Memory Having Monolithic Crystalline Silicon Vertical NAND Channel” – hereinafter ‘MEM’),
the method comprising:
forming a plurality of alternating material layers (Fig. 4C annotated, see below – hereinafter ‘VS’ – [0059] – “Step 602 is to form horizontal layers of material above a substrate”) arranged in a vertical stack on a substrate (201 – Fig. 8G – [0087] – “the silicon substrate 201”);
etching a channel hole (MH – Fig. 8C – [0069] – “etching memory holes (MH)”) through the plurality of alternating material layers (VS) to the substrate (201);
forming a tunneling layer (869 – Fig. 8C – [0076] – “Region 869 is a hollow cylinder”) around the channel hole (MH), the tunneling layer (696) contacting the plurality of alternating material layers (VS);
forming a channel liner (870 – Fig. 8E – [0078] – “protective layer 870”) along the tunneling layer (696 – Fig. 8E shows this);
forming a core gap material ([0073 – “Step 710a is just one example of the initial filling of the memory holes” – hereinafter ‘CGM’) within the channel liner (870);
removing ([0079] – “Step 714 is etching of the bottom of the memory holes with the protective layer 870 in place over the tunnel oxide on the vertical sidewalls. FIG. 8F shows results after step 714”) a portion of the tunneling layer (869 – Fig. 8F – [0078] – “the outermost portion of region 869 is the tunnel oxide”) and the channel liner (870 – Fig. 8F – [0079] – “etching has gone through the protective layer 870 at the bottom of the memory holes”) to form a gap beneath the core gap material (CGM);
removing, through the gap, the channel liner ([0079] – “Step 714 is etching of the bottom of the memory holes with the protective layer 870 in place over the tunnel oxide on the vertical sidewalls. FIG. 8F shows results after step 714”) from the channel hole (MH); and
epitaxially growing a hollow epitaxial silicon core (699 – Fig. 5B – [0104] – “the mono-silicon crystalline vertical NAND channel 699 is formed using vapor phase epitaxial growth to grow the mono-crystalline silicon from the bottom of the vertically-oriented channel upwards to the top of the vertically-oriented channel”) from the substrate (201) through the channel hole (MH), between the tunneling layer (696) and the core gap material (CGM).
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Rabkin-272 does not expressly disclose the other limitations of claim 8.
However, in an analogous art, Rabkin-966 teaches
a hollow (1 – Fig. 1B – [7:3] – “the hollow channel 1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the hollow structure as taught by Rabkin-966 into Rabkin-272.
An ordinary artisan would have been motivated to use the known technique of Rabkin-966 in the manner set forth above to produce the predictable result as stated above in claim 1.
Rabkin-272 and Rabkin-966 do not expressly disclose the other limitations of claim 8.
However, in an analogous art, Yang teaches
to form a gap (132 – Fig. 1B – [0026] – “The bottom surface of protection layer 130 is removed to expose part of selective epitaxial sacrificial layer 110. As shown in FIG. 1B, the fabrication process proceeds, such that selective epitaxial sacrificial layer 110 (as shown in FIG. 1A) is removed through slit 128 to form a cavity 132 exposing a portion of memory film 116”) beneath the core gap material;
removing, through the gap (132).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the gap structure as taught by Yang into Rabkin-272 and Rabkin-966.
An ordinary artisan would have been motivated to use the known technique of Yang in the manner set forth above to produce the predictable result of [0024] – “a semiconductor plug is selectively grown to surround the sidewalls of NAND memory strings. Compared with another type of semiconductor plug that is formed at the lower end of the NAND memory string, the formation of the sidewall semiconductor plug avoids the etching of the memory film and semiconductor channel at the bottom surface of channel holes, thereby increasing the process window, in particular when fabricating 3D NAND memory devices with advanced technologies, such as having 96 or more levels with a multi-deck architecture.”
Regarding claim 14, Rabkin-272 as modified by Rabkin-966 and Yang, teaches claim 8 from which claim 14 depends. Rabkin-272 further teaches
(Original) The method of claim 8, wherein removing the channel liner
([0079] – “Step 714 is etching of the bottom of the memory holes with the protective layer 870 in place over the tunnel oxide on the vertical sidewalls. FIG. 8F shows results after step 714”) from the channel hole (MH) comprises recessing a first portion of the channel liner (870 – Fig. 8E – [0078] – “protective layer 870”) from a lower section of the channel hole (MH), and wherein an epitaxial core layer (699) is epitaxially grown within the lower section of the channel hole (MH).
Regarding independent claim 15, Rabkin-272 teaches:
(Currently Amended) A method of fabricating a hollow epitaxial
silicon core (699 – Fig. 5B – [0104] – “the mono-silicon crystalline vertical NAND channel 699 is formed using vapor phase epitaxial growth to grow the mono-crystalline silicon from the bottom of the vertically-oriented channel upwards to the top of the vertically-oriented channel”) of a three-dimensional (3D) NAND memory structure ([Title] – “Fabricating 3D NAND Memory Having Monolithic Crystalline Silicon Vertical NAND Channel” – hereinafter ‘MEM’), the method comprising:
forming a plurality of alternating material layers (Fig. 4C annotated, see below – hereinafter ‘VS’ – [0059] – “Step 602 is to form horizontal layers of material above a substrate”) arranged in a vertical stack on a silicon substrate (201 – Fig. 8G – [0087] – “the silicon substrate 201”);
etching a channel hole (MH – Fig. 8C – [0069] – “etching memory holes (MH)”) through the plurality of alternating material layers (VS) to the silicon substrate (201);
forming a tunneling layer (869 – Fig. 8C – [0076] – “Region 869 is a hollow cylinder”) around the channel hole (MH), wherein the tunneling layer (696) contacting the plurality of alternating material layers (VS);
forming a channel liner (870 – Fig. 8E – [0078] – “protective layer 870”) around the tunneling layer (696 – Fig. 8E shows this);
forming a core gap material ([0073 – “Step 710a is just one example of the initial filling of the memory holes” – hereinafter ‘CGM’) within the channel liner (870);
removing ([0079] – “Step 714 is etching of the bottom of the memory holes with the protective layer 870 in place over the tunnel oxide on the vertical sidewalls. FIG. 8F shows results after step 714”) a portion of the tunneling layer (869 – Fig. 8F – [0078] – “the outermost portion of region 869 is the tunnel oxide”) and the channel liner (870 – Fig. 8F – [0079] – “etching has gone through the protective layer 870 at the bottom of the memory holes”) to form a gap beneath the core gap material (CGM);
removing, through the gap, the channel liner ([0079] – “Step 714 is etching of the bottom of the memory holes with the protective layer 870 in place over the tunnel oxide on the vertical sidewalls. FIG. 8F shows results after step 714”) from the channel hole (MH); and
epitaxially growing the hollow epitaxial silicon core (699) from the silicon substrate (201) through the channel hole (MH), between the tunneling layer (696) and the core gap material (CGM).
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Rabkin-272 does not expressly disclose the other limitations of claim 15.
However, in an analogous art, Rabkin-966 teaches
a hollow (1 – Fig. 1B – [38 = 7:3] – “the hollow channel 1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the hollow structure as taught by Rabkin-966 into Rabkin-272.
An ordinary artisan would have been motivated to use the known technique of Rabkin-966 in the manner set forth above to produce the predictable result as stated above in claim 1.
Rabkin-272 and Rabkin-966 do not expressly disclose the other limitations of claim 15.
However, in an analogous art, Yang teaches
to form a gap (132 – Fig. 1B – [0026] – “The bottom surface of protection layer 130 is removed to expose part of selective epitaxial sacrificial layer 110. As shown in FIG. 1B, the fabrication process proceeds, such that selective epitaxial sacrificial layer 110 (as shown in FIG. 1A) is removed through slit 128 to form a cavity 132 exposing a portion of memory film 116”) beneath the core gap material;
removing, through the gap (132).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the gap structure as taught by Yang into Rabkin-272 and Rabkin-966.
An ordinary artisan would have been motivated to use the known technique of Yang in the manner set forth above to produce the predictable result as stated above in claim 8.
Regarding claim 20, Rabkin-272 as modified by Rabkin-966 and Yang, teaches claim 15 from which claim 20 depends. Rabkin-272 further teaches
(Original) The method of claim 15, wherein removing the channel
liner ([0079] – “Step 714 is etching of the bottom of the memory holes with the protective layer 870 in place over the tunnel oxide on the vertical sidewalls. FIG. 8F shows results after step 714”) from the channel hole (MH) comprises recessing a first portion of the channel liner (870 – Fig. 8E – [0078] – “protective layer 870”) from a lower section of the channel hole (MH), and wherein an epitaxial core layer (699) is epitaxially grown within the lower section of the channel hole (MH).
Claims 9-11, 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Rabkin-272 in view of Rabkin-966, Yang, and Choi et al. (US 20200020713 A1 – hereinafter Choi).
Regarding claim 9, Rabkin-272 as modified by Rabkin-966 and Yang, teaches claim 8 from which claim 9 depends. Rabkin-272, Rabkin-966, and Yang do not expressly disclose the limitations of claim 9.
However, in an analogous art, Choi teaches
(Original) The method of claim 8, further comprising etching a slit (91 – Fig.
1 – [0016] – “isolation trench 91”) in the memory structure ([0015] – “semiconductor device according to an example embodiment may include a non-volatile memory, such as a vertical NAND (VNAND) device or a three-dimensional (3D) flash memory”), wherein the slit (91) extends through the plurality of alternating material layers (60 – Fig. 1 – [0017] – “lower stack structure 60 may include a plurality of lower insulating layers 61 and a plurality of lower conductive layers 95, which are stacked alternately and repetitively”) and into a sacrificial nitride layer (29 – Fig. 22 – {[0038] – “mold layer 29 may include an oxide, a nitride, a semiconductor, or a combination thereof”} , {[0073] – “The mold layer 29 may be removed to form a replacement conductive line 93”}), and wherein the sacrificial nitride layer (29) is above the substrate (21 – Fig. 1 – [0016] – “substrate 21”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the slit structure as taught by Choi into Rabkin-272, Rabkin-966, and Yang.
An ordinary artisan would have been motivated to use the known technique of Choi in the manner set forth above to produce the predictable result [0073] – “A trench buried layer 98 may be formed to fill the inside of the isolation trench 91 and be in contact with the impurity region 94” and also providing additional support to the alternating layers.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 10, Rabkin-272 as modified by Rabkin-966, Yang, and Choi, teaches claim 9 from which claim 10 depends. Rabkin-272, Rabkin-966, and Yang do not expressly disclose the limitations of claim 10.
However, in an analogous art, Choi teaches
(Original) The method of claim 9, further comprising selectively etching
([0038] – “support 50 may include a material having an etch selectivity with respect to the mold layer 29”) the sacrificial nitride layer (29) to expose a portion of the tunneling layer (83 – Fig. 38 – [0019] – “tunnel insulating layer 83”) and the channel liner (86 – Fig. 39 – [0019] – “channel pattern 86” – Fig. 39 sows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the etching structure as taught by Choi into Rabkin-272, Rabkin-966, and Yang.
An ordinary artisan would have been motivated to use the known technique of Choi in the manner set forth above to produce the predictable result of providing electrical contact between the separate channels.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 11, Rabkin-272 as modified by Rabkin-966, Yang, and Choi, teaches claim 10 from which claim 11 depends. Rabkin-272, Rabkin-966, and Yang do not expressly disclose the limitations of claim 11.
However, in an analogous art, Choi teaches
(Original) The method of claim 10, further comprising removing the portion
of the tunneling layer (83) and the channel liner (86 – Fig. 39 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the etching structure as taught by Choi into Rabkin-272, Rabkin-966, and Yang.
An ordinary artisan would have been motivated to use the known technique of Choi in the manner set forth above to produce the predictable result as stated above in claim 10.
Regarding claim 16, Rabkin-272 as modified by Rabkin-966 and Yang, teaches claim 15 from which claim 16 depends. Rabkin-272, Rabkin-966, and Yang do not expressly disclose the limitations of claim 16.
However, in an analogous art, Choi teaches
(Original) The method of claim 15, further comprising etching a slit (91 –
Fig. 1 – [0016] – “isolation trench 91”) in the memory structure ([0015] – “semiconductor device according to an example embodiment may include a non-volatile memory, such as a vertical NAND (VNAND) device or a three-dimensional (3D) flash memory”) through the plurality of alternating material layers (60 – Fig. 1 – [0017] – “lower stack structure 60 may include a plurality of lower insulating layers 61 and a plurality of lower conductive layers 95, which are stacked alternately and repetitively”), wherein the slit (91) extends into a sacrificial nitride layer (29 – Fig. 22 – {[0038] – “mold layer 29 may include an oxide, a nitride, a semiconductor, or a combination thereof”} , {[0073] – “The mold layer 29 may be removed to form a replacement conductive line 93”}), and wherein the sacrificial nitride layer (29) is above the silicon substrate (21 – Fig. 22 – [0037] – “substrate 21 may be a P-type single-crystalline silicon wafer”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the slit structure as taught by Choi into Rabkin-272, and Yang.
An ordinary artisan would have been motivated to use the known technique of Choi in the manner set forth above to produce the predictable result of providing electrical contact between the separate channels and additional support to the alternating layers
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 17, Rabkin-272 as modified by Rabkin-966, Yang, and Choi, teaches claim 6 from which claim 17 depends. Rabkin-272, Rabkin-966, and Yang do not expressly disclose the limitations of claim 17.
However, in an analogous art, Choi teaches
(Currently Amended) The method of claim 16further comprising removing
the portion of the tunneling layer (83) and the channel liner (86 – Fig. 39 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the etching structure as taught by Choi into Rabkin-272, Rabkin-966, and Yang.
An ordinary artisan would have been motivated to use the known technique of Choi in the manner set forth above to produce the predictable result as stated above in claim 10.
Claims 12, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Rabkin-272 in view of Rabkin-966, Yang, Choi, and Wu.
Regarding claim 12, Rabkin-272 as modified by Rabkin-966, Yang, and Choi, teaches claim 11 from which claim 12 depends. Rabkin-272 further teaches
(Original) The method of claim 10, further comprising epitaxially
growing ([0063] – “Step 606b comprises growing mono-crystalline silicon from the substrate (e.g., silicon substrate) upwards to the top of the vertically oriented channel”).
Rabkin-272, Rabkin-966, and Yang do not expressly disclose the other limitations of claim 12.
However, in an analogous art, Choi teaches
the portion of the tunneling layer (83) and the channel liner (86) are removed.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate removing the tunneling and the channel layer structure as taught by Choi into Rabkin-272, Rabkin-966, and Yang.
An ordinary artisan would have been motivated to use the known technique of Choi in the manner set forth above to produce the predictable result of providing an opening in the layer structure for the silicon to grow.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Rabkin-272, Rabkin-966, Yang, and Choi do not expressly disclose the other limitations of claim 12.
However, in an analogous art, Wu teaches
an epitaxial silicon layer (184 – Fig. 10 – [0046] – “The selective epitaxial
growth is performed to deposit a silicon layer 184 in the cavity 181”) above the substrate (110 – Fig. 10 – [0046] – “the substrate 110 is single crystalline silicon”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the epitaxial silicon structure as taught by Wu into Rabkin-272, Rabkin-966, Yang, and Choi.
An ordinary artisan would have been motivated to use the known technique of Wu in the manner set forth above to produce the predictable result of as stated above in claim 6.
Regarding claim 18, Rabkin-272 as modified by Rabkin-966, Yang, and Choi, teaches claim 17 from which claim 18 depends. Rabkin-272, Rabkin-966, and Yang do not expressly disclose the limitations of claim 18.
However, in an analogous art, Choi teaches
(Currently Amended) The method of claim 17, wherein
removing the portion of the tunneling layer (83) and the channel liner (86 – Fig. 39 shows this) further forms [[a]] the gap between the silicon substrate (21) and the channel liner (86).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate removing the tunneling and the channel layer structure as taught by Choi into Rabkin-272, Rabkin-966, and Yang.
An ordinary artisan would have been motivated to use the known technique of Choi in the manner set forth above to produce the predictable result of providing an opening in the layer structure for the silicon to grow.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Rabkin-272, Rabkin-966, Yang, and Choi do not expressly disclose the other limitations of claim 18.
However, in an analogous art, Wu teaches
further forms [[a]] the gap (wu (181 – [0044] – “Removal of the cover layer 120 creates a cavity 181 and exposes the top surface of the substrate 110 at the bottom of the cavity 181”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the gap structure as taught by Wu into Rabkin-272, Rabkin-966, Yang, and Choi.
An ordinary artisan would have been motivated to use the known technique of Wu in the manner set forth above to produce the predictable result of forming a space for the silicon to grow.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 19, Rabkin-272 as modified by Rabkin-966, Yang, Choi, and Wu, teaches claim 18 from which claim 19 depends. Rabkin-272 further teaches
(Original) The method of claim 18, further comprising epitaxially
growing ([0063] – “Step 606b comprises growing mono-crystalline silicon from the substrate (e.g., silicon substrate) upwards to the top of the vertically oriented channel”).
Rabkin-272, Rabkin-966, Yang, and Choi do not expressly disclose the other limitations of claim 19.
However, in an analogous art, Wu teaches
an epitaxial silicon layer (184 – Fig. 10 – [0046] – “The selective epitaxial
growth is performed to deposit a silicon layer 184 in the cavity 181”) from the silicon substrate (110 – Fig. 10 – [0046] – “the substrate 110 is single crystalline silicon”), wherein the epitaxial silicon layer (184) extends into the gap (181 – Fig. 10 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the epitaxial silicon layer structure as taught by Wu into Rabkin-272, Rabkin-966, Yang, and Choi.
An ordinary artisan would have been motivated to use the known technique of Wu in the manner set forth above to produce the predictable result of providing electrical connectivity between the channels.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Rabkin-272 in view of Rabkin-966, Yang, and Ishihara et al. (US 20200176474 A1 – hereinafter Ishihara).
Regarding claim 13, Rabkin-272 as modified by Rabkin-966 and Yang, teaches claim 8 from which claim 13 depends. Rabkin-272, Rabkin-966, and Yang do not expressly disclose the limitations of claim 13.
However, in an analogous art, Ishihara teaches
(Original) The method of claim 8, further comprising:
etching a second channel hole (ST – Fig. 7A – [0045] – “a slit ST”) through
the plurality of alternating material layers ([0045] – “The slit ST is formed, for example, by selectively removing the interlayer insulating films 13, 15 and the sacrificial films 33” – Fig. 7A shows this, hereinafter ‘AM’), wherein the second channel hole (ST) extends into the substrate (SL – Fig. 7A – [0045] – “The slit ST has a depth extending from the uppermost interlayer insulating film 15 to the source layer SL” – this is a substrate); and
filling the second channel hole (ST) with a gap fill material (LI – Fig. 9B – [0050] – “a lead layer LI is formed inside the slit ST”) to support the vertical stack.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second channel hole structure as taught by Ishihara into Rabkin-272, Rabkin-966, and Yang.
An ordinary artisan would have been motivated to use the known technique of Ishihara in the manner set forth above to produce the predictable result of providing support to the alternating layers.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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