DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Group I and Species (a), (claims 1-2 and 6-12), in the
reply filed on 04/27/2026 is acknowledged. Claims 3-5 and 13-20 directed to the non-elected invention II and Species (b), (c), (d) are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2,6 and 9-12 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Elsherbini et al. (US 20230197677 A1) in view of Yu et al. (US 20210091056 A1, hereinafter Yu).
Re: Independent Claim 1, Elsherbini discloses a semiconductor package (Fig. 2B) comprising:
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Elsherbini’s Figure 2B-Annotated.
a plurality of bridge dies (106, 204 bridge dies in [0078], Fig. 2B);
a plurality of conductive posts (210 through-dielectric vias in [0080], Fig. 2B); and
a plurality of semiconductor chips (102 a plurality IC dies in [0073], Fig. 2B), wherein
each of the plurality of bridge dies (106,204) includes connection pads (106-pad, 204-pad in [0078], Fig. 2B-Annotated) on an upper surface of the plurality of bridge dies (106,204).
Elsherbini does not expressly disclose a first redistribution layer; a plurality of bridge dies (106, 204) on an upper surface of the first redistribution layer; a second redistribution layer on the plurality of bridge dies and electrically connected to the plurality of bridge dies; a plurality of conductive posts (210) between the first redistribution layer and the second redistribution layer; and a plurality of semiconductor chips (102) on an upper surface of the second redistribution layer, and a pitch between first connection pads of a first bridge die among the plurality of bridge dies is smaller than a pitch between second connection pads of a second bridge die among the plurality of bridge dies and a distance between an upper surface of the first bridge die and a lower surface of the second redistribution layer is smaller than a distance between an upper surface of the second bridge die and the lower surface of the second redistribution layer.
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Yu’s Figure 25-Annotated.
However, in the same semiconductor device field of endeavor, Yu discloses a semiconductor package including a first redistribution layer (230 interconnect structure as redistribution layer in [0066], Fig. 25); a plurality of bridge dies (50-left, 50-right interconnect device in [0017], Fig. 25-Annotated) on an upper surface of the first redistribution layer (230); a second redistribution layer (210 interconnect structure as redistribution layer in [0057], Fig. 25) on the plurality of bridge dies (50-left, 50-right) and electrically connected to the plurality of bridge dies (50-left, 50-right); a plurality of conductive posts (206 through vias in [0056], Fig. 25) between the first redistribution layer (230) and the second redistribution layer (210); and a plurality of semiconductor chips (324,326,122 in [0079,0080], Fig. 25) on an upper surface of the second redistribution layer (210).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yu’s feature of a first redistribution layer and a second redistribution layer to Elsherbini’s device to have a first redistribution layer; a plurality of bridge dies on an upper surface of the first redistribution layer; a second redistribution layer on the plurality of bridge dies and electrically connected to the plurality of bridge dies; a plurality of conductive posts between the first redistribution layer and the second redistribution layer; and a plurality of semiconductor chips on an upper surface of the second redistribution layer to increase the electrical connection by using redistribution layer ([0066], Yu).
The combination of Elsherbini and Yu results in a distance between an upper surface of the first bridge die (204, Elsherbini) and a lower surface of the second redistribution layer (Yu’s 210 applied to Elsherbini) is smaller (Bridge die 204 may be wider and longer than adjacent bridge dies 106 in [0078], Elsherbini, due to 204 is wider than 106, the distance between Elsherbini’s 204 and Yu’s 210 is smaller than the distance between Elsherbini’s 106 and Yu’s 210) than a distance between an upper surface of the second bridge die (106, Elsherbini) and the lower surface of the second redistribution layer (Yu’s 210 applied to Elsherbini).
Still, Elsherbini modified by Yu does not expressly disclose a pitch between first connection pads of a first bridge die among the plurality of bridge dies is smaller than a pitch between second connection pads of a second bridge die among the plurality of bridge dies.
However, the Applicant has not presented persuasive evidence that the claimed
“pitch between first connection pads of a first bridge die among the plurality of bridge dies is smaller than a pitch between second connection pads of a second bridge die among the plurality of bridge dies” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed range of the pitch between first connection pads of a first bridge die among the plurality of bridge dies is smaller than a pitch between second connection pads of a second bridge die among the plurality of bridge dies). Also, the applicant has not shown that the claimed “difference of pitch between first connection pads of a first bridge die among the plurality of bridge dies is smaller than a pitch between second connection pads of a second bridge die among the plurality of bridge dies” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Elsherbini discloses “a pitch between first connection pads (204-pad in [0078], Fig. 2B-Annotated) of a first bridge die (204, bridge die in [0078], Fig. 2B) among the plurality of bridge dies (106,204) is bigger (Fig. 2B-Annotated) than a pitch between second connection pads (106-pad in [0078], Fig. 2B-Annotated) of a second bridge die (106, bridge die in [0078], Fig. 2B) among the plurality of bridge dies (106,204)”, therefore, the pitch is a result effective variable. It has been held that is not inventive to discover the optimum pitch between first connection pads of a first bridge die smaller than a pitch between second connection pads of a second bridge die by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the pitch between first connection pads of a first bridge die among the plurality of bridge dies is smaller than a pitch between second connection pads of a second bridge die among the plurality of bridge dies to the rest of the claimed invention for modular die interoperability in semiconductor integrated circuit (IC) packaging ([0001], Elsherbini).
Re: Claim 2, Elsherbini modified by Yu discloses the semiconductor package of claim 1, wherein a thickness of the first bridge die (204, Elsherbini) is larger in a vertical direction (in [0078], Elsherbini) than a thickness of the second bridge die (106, Elsherbini).
Re: Claim 6, Elsherbini modified by Yu discloses the semiconductor package of claim 1,
Elsherbini modified by Yu does not expressly disclose further comprising: first conductive pillars; and second conductive pillars, wherein the first connection pads of the first bridge die are electrically connected to the second redistribution layer through the first conductive pillars, and the second connection pads of the second bridge die are electrically connected to the second redistribution layer through the second conductive pillars.
However, in the same semiconductor device field of endeavor, Yu discloses a semiconductor package including first conductive pillars (76-left metal pillars in [0023], Figs. 1, 25-Annotated); and second conductive pillars (76-right metal pillars in [0023], Figs. 1, 25-Annotated), wherein the first connection pads (72-left metal pillars in [0022], Figs. 1, 25-Annotated) of the first bridge die (50-left in [0022], Figs. 1, 25-Annotated) are electrically connected to the second redistribution layer (210 interconnect structure as redistribution layer in [0057], Fig. 25) through the first conductive pillars (76-left), and the second connection pads (72-right metal pillars in [0022], Figs. 1, 25-Annotated) of the second bridge die (50-right in [0022], Figs. 1, 25-Annotated) are electrically connected to the second redistribution layer (210) through the second conductive pillars (76-right).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yu’s feature of first conductive pillars; and second conductive pillars, wherein the first connection pads of the first bridge die are electrically connected to the second redistribution layer through the first conductive pillars, and the second connection pads of the second bridge die are electrically connected to the second redistribution layer through the second conductive pillars to Elsherbini’s device to increase the electrical connection by using redistribution layer ([0066], Yu).
Re: Claim 9, Elsherbini modified by Yu discloses the semiconductor package of claim 1, wherein the plurality of semiconductor chips include a first semiconductor chip (102-left in [0073], Fig. 2B-Annotated, Elsherbini), a second semiconductor chip (102-middle in [0073], Fig. 2B-Annotated, Elsherbini), and a third semiconductor chip (102-right in [0073], Fig. 2B-Annotated, Elsherbini); the first bridge die (204, Fig. 2B-Annotated, Elsherbini) electrically connects the first semiconductor chip (102-left, Elsherbini) to the second semiconductor chip (102-middle, Elsherbini); and the second bridge die (106, Fig. 2B-Annotated, Elsherbini) electrically connects the second semiconductor chip (102-middle, Elsherbini) to the third semiconductor chip (102-right, Elsherbini).
Re: Claim 10, Elsherbini modified by Yu discloses the semiconductor package of claim 9, wherein the first semiconductor chip (102-left, Elsherbini) and the second semiconductor chip (102-middle, Elsherbini) are logic chips (logic monolithic dies in [0073], Elsherbini), and the third semiconductor chip (102-right, Elsherbini) is a memory chip (stack of IC dies e.g., high-bandwidth memory in [0073], Elsherbini).
Re: Claim 11, Elsherbini modified by Yu discloses the semiconductor package of claim 10, wherein the third semiconductor chip (102-right, Elsherbini) is a memory chip stack (stack of IC dies e.g., high-bandwidth memory in [0073], Elsherbini).
Re: Claim 12, Elsherbini modified by Yu discloses the semiconductor package of claim 9, wherein the first bridge die (204, Elsherbini) partially overlaps both the first semiconductor chip (102-left, Elsherbini) and the second semiconductor chip (102-middle, Elsherbini) in a plan view (Figs 2A-2B, Elsherbini), and the second bridge die (106, Elsherbini) partially overlaps both the second semiconductor chip (102-middle, Elsherbini) and the third semiconductor chip (102-right, Elsherbini) in the plan view (Figs 2A-2B, Elsherbini).
Claim(s) 7-8 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Elsherbini in view of Yu and further in view of Han et al. (US 20210366860 A1, hereinafter Han).
Re: Claim 7, Elsherbini modified by Yu discloses the semiconductor package of claim 6,
Elsherbini modified by Yu does not expressly disclose wherein a pitch between the first conductive pillars is less than a pitch between the second conductive pillars, and a thickness of the first conductive pillars is less than a thickness of the second conductive pillars.
However, in the same semiconductor device field of endeavor, Han discloses a pitch (Figs. 3B-3C) between the first conductive pillars (303-right in [0034], Fig. 3B-Annotated) is less than a pitch (Figs. 3B-3C) between the second conductive pillars (303-left in [0034], Fig. 3B-Annotated).
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Han’s Figure 3B-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yu’s feature of a pitch between the first conductive pillars is less than a pitch between the second conductive pillars to the combination of Elsherbini and Yu to provide an electrical connection between package side pads ([0034], Han).
Still, Elsherbini modified by Yu and Han does not expressly disclose a thickness of the first conductive pillars is less than a thickness of the second conductive pillars.
However, the Applicant has not presented persuasive evidence that the claimed
“thickness of the first conductive pillars is less than a thickness of the second conductive pillars” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed range of a thickness of the first conductive pillars is less than a thickness of the second conductive pillars). Also, the applicant has not shown that the claimed “difference of a thickness of the first conductive pillars is less than a thickness of the second conductive pillars” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Han discloses “a thickness of the second conductive pillars (303-left) less than a thickness of the second conductive pillars (303-right)”, therefore, the thickness is a result effective variable. It has been held that is not inventive to discover the optimum thickness of the first conductive pillars and the second conductive pillars by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a thickness of the first conductive pillars is less than a thickness of the second conductive pillars to the rest of the claimed invention to provide an electrical connection between package side pads ([0034], Han).
Re: Claim 8, Elsherbini modified by Yu and Han discloses the semiconductor package of claim 7,
Elsherbini modified by Yu and Han does not expressly disclose wherein the first bridge die includes a first connection layer and a first silicon layer, the first connection layer includes the first connection pads and a first connection pattern connecting the first connection pads, and a lower surface of the first silicon layer is on the upper surface of the first redistribution layer; and the second bridge die includes a second connection layer and a second silicon layer, the second connection layer includes the second connection pads and a second connection pattern connecting the second connection pads, and a lower surface of the second silicon layer is on the upper surface of the first redistribution layer.
However, in the same semiconductor device field of endeavor, Yu discloses a semiconductor package wherein the first bridge die (50-left in [0022], Figs. 1, 25-Annotated) includes a first connection layer (60,74-left in [0018-0022], Figs. 1, 25-Annotated) and a first silicon layer (52-left in [0018], Figs. 1, 25-Annotated), the first connection layer (60,74) includes the first connection pads (72-left metal pillars in [0022], Figs. 1, 25-Annotated) and a first connection pattern (62-left in [0019], Figs. 1, 25-Annotated) connecting the first connection pads (72-left), and a lower surface of the first silicon layer (52-left) is on the upper surface of the first redistribution layer (230 in [0057], Fig. 25); and the second bridge die (50-right in [0022], Figs. 1, 25-Annotated) includes a second connection layer (60,74-right in [0018-0022], Figs. 1, 25-Annotated) and a second silicon layer (52-right in [0018], Figs. 1, 25-Annotated), the second connection layer (50-right in [0022], Figs. 1, 25-Annotated) includes the second connection pads (72-right in [0022], Figs. 1, 25-Annotated) and a second connection pattern (62-right in [0019], Figs. 1, 25-Annotated) connecting the second connection pads (72-right), and a lower surface of the second silicon layer (52- right) is on the upper surface of the first redistribution layer (230 in [0057], Fig. 25).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yu’s feature of wherein the first bridge die includes a first connection layer and a first silicon layer, the first connection layer includes the first connection pads and a first connection pattern connecting the first connection pads, and a lower surface of the first silicon layer is on the upper surface of the first redistribution layer; and the second bridge die includes a second connection layer and a second silicon layer, the second connection layer includes the second connection pads and a second connection pattern connecting the second connection pads, and a lower surface of the second silicon layer is on the upper surface of the first redistribution layer to Elsherbini’s device to increase the electrical connection by using redistribution layer ([0066], Yu).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lau et al. (US 11410933 B2) teaches “PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF”. This document is related to a package structure, including a bridge, an interposer, a first redistribution structure layer, a second redistribution structure layer, and multiple chips, is provided. The bridge includes a silicon substrate, a redistribution layer, and multiple bridge pads. The interposer includes an intermediate layer, multiple conductive vias, multiple first pads, and multiple second pads. The bridge is embedded in the intermediate layer. The bridge pads are aligned with the upper surface. The first redistribution structure layer is disposed on the upper surface of the interposer and is electrically connected to the first pads and the bridge pads. The second redistribution structure layer is disposed on the lower surface of the interposer and is electrically connected to the second pads. The chips are disposed on the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The chips are electrically connected to each other through the bridge.
Ting et al. (US 10867954 B2) teaches “INTERCONNECT CHIPS”. This document is related to an interconnect die including a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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