DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5, 8, 10, 12, 14, and 18 are rejected under U.S.C. 103 as being unpatentable over Jeong et al.; US 2023/0282631 A1; 01/2023 in view of Kang et al.; US 2022/0208747 A1; 12/2021 and Li et al.; US 2020/0403026 A1; 06/2020
Claim 1: Jeong discloses a display panel ( Fig. 9 display apparatus #10D ) comprising: a substrate ( Fig. 9 substrate #111’ ); a lighting-emitting diode (LED) layer ( Fig. 9 LED cells #110’ ) disposed on the substrate ( Fig. 9 substrate #111’ ) and comprising a first epitaxial layer ( Fig. 9 #116) , a second epitaxial layer ( Fig. 9 #114 ), and a third epitaxial layer ( Fig. 9 #112 ) disposed in stack ( [0113] the stack structure of the first conductivity-type semiconductor layer 112, the active layer 114, the second conductivity-type semiconductor layer 116, and the contact layer 155, the LED cells 110 may be formed ); a thin film transistor (TFT) device layer ( Fig. 3 driving elements #220; [0032] driving elements #220 including TFT cells formed on the semiconductor substrate; [0104] Fig. 9 is a schematic cross-sectional view of a display apparatus according to an example embodiment, and may be understood as a cross-section corresponding to the cross-section corresponding to FIG. 3 ) disposed on the LED layer ( Fig. 3 #100 ), wherein the TFT device layer ( Fig. 3 #220 ) and the LED layer ( Fig. 3 #100 ) form a longitudinal integrated structure ( [0034] The source region 205 of the TFT cells may be electrically connected to one electrode of LED cells 110 through the interconnections 230 ); and a metal wiring layer ( Fig. 3 #230 ) disposed on the TFT device layer ( Fig. 3 #220 ) and configured to provide a driving signal for the display panel ( [0034] The source region 205 of the TFT cells may be electrically connected to one electrode of LED cells 110 through the interconnections 230 );
Jeong does not appear to disclose the LED layer is located between the substrate and the TFT device layer in a thickness direction of the display panel; a first bonding layer, a first filter layer, and a first transparent conductive layer are sequentially disposed between the first epitaxial layer and the second epitaxial layer, and the first bonding layer is in contact with a surface of the first epitaxial layer facing the second epitaxial layer; and wherein a second bonding layer a second filter layer, and a second transparent conductive layer are sequentially disposed between the second epitaxial layer and the third epitaxial layer, and the second bonding layer is in contact with a surface of the second epitaxial layer facing the third epitaxial layer.
Kang discloses the LED layer ( Fig. 3 multiple micro LEDs 51, 52, 53 ) is located between the substrate ( [0073] Referring to Fig. 3, the polarizing member 90 may be formed roughly in a plate form, and may include a transparent glass substrate 91 and a circular polarizing layer 93 stacked at one surface of the glass substrate 91 ) and the TFT device layer ( Fig. 3 TFT substrate 20 ) in a thickness direction of the display panel ( as shown in Fig. 3 ).
Kang does not appear to disclose a first bonding layer, a first filter layer, and a first transparent conductive layer are sequentially disposed between the first epitaxial layer and the second epitaxial layer, and the first bonding layer is in contact with a surface of the first epitaxial layer facing the second epitaxial layer; and wherein a second bonding layer a second filter layer, and a second transparent conductive layer are sequentially disposed between the second epitaxial layer and the third epitaxial layer, and the second bonding layer is in contact with a surface of the second epitaxial layer facing the third epitaxial layer.
However, Li teaches a first bonding layer ( Fig. 2B: Transparent Bonding Layer 216 ), a first filter layer ( Fig. 2B: Reflection Layer 214 ), and a first transparent conductive layer ( [0075] In some embodiments, conductive transparent layers are formed between the LED epitaxial layers to improve conductivity and transparency ) are sequentially disposed between the first epitaxial layer ( Fig. 2B: Epitaxial Layer 210 ) and the second epitaxial layer ( Fig. 2B: Epitaxial Layer 220 ), and the first bonding layer is in contact with a surface of the first epitaxial layer facing the second epitaxial layer ( [0086] In some embodiments, a second epitaxial layer 220 is bonded on top of the first epitaxial layer 210 through the transparent bonding layer 216 ); and wherein a second bonding layer ( Fig. 2B #226 ), a second filter layer ( Fig. 2B third reflection layer 224 ), and a second transparent conductive layer ( Fig. 2B ITO layer 228) are sequentially disposed between the second epitaxial layer ( Fig. 2B #220 ) and the third epitaxial layer ( Fig. 2B #230 ), and the second bonding layer is in contact with a surface of the second epitaxial layer facing the third epitaxial layer ( [0094] In some embodiments, a third epitaxial layer 230 is bonded on top of the second epitaxial layer 220 through the transparent bonding layer 226 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Li with Jeong and Kang to implement the LED layer is located between the substrate and the TFT device layer in a thickness direction of the display panel; a first bonding layer, a first filter layer, and a first transparent conductive layer are sequentially disposed between the first epitaxial layer and the second epitaxial layer, and the first bonding layer is in contact with a surface of the first epitaxial layer facing the second epitaxial layer; and wherein a second bonding layer a second filter layer, and a second transparent conductive layer are sequentially disposed between the second epitaxial layer and the third epitaxial layer, and the second bonding layer is in contact with a surface of the second epitaxial layer facing the third epitaxial layer because the LED layer between the substrate and the TFT device layer serves as the light source for the entire display to ensure uniform brightness, high contrast, and full-color reproduction in TFT LCD displays.
Claim 3: Jeong, Kang, and Li disclose the display panel of claim 1 ( as discussed above).
Jeong teaches a reflective layer ( Fig. 9 partition reflective layer #170 ) is disposed on the third epitaxial layer ( Fig. 9 #112 ).
Claim 5: Jeong, Kang, and Li disclose the display panel of claim 1 ( as discussed above).
Jeong teaches a plurality of micro light-emitting diode (Micro LED) display units ( [0037] The plurality of LED cells 110 may respectively be a micro LED ) arranged in an array ( as shown in Fig. 2) , wherein each of the plurality of Micro LED display units comprises a first pixel ( Fig. 2: SP1 ), a second pixel ( Fig. 2: SP2 ), and a third pixel ( Fig. 2: SP3 ); wherein the TFT device layer comprises a first TFT ( Fig. 3 #220 connected to SP1), a second TFT ( Fig. 3 #220 connected to SP2 ), and a third TFT ( Fig. 3 #220 connected to SP3 ) disposed corresponding to the first pixel ( Fig. 3: SP1 ), the second pixel ( Fig. 3: SP2 ), and the third pixel ( Fig. 3: SP3 ), respectively.
Claim 8: Jeong, Kang, and Li disclose the display panel of claim 1 ( as discussed above).
Jeong teaches a first step portion ( Fig. 3 #240 ) and a second step portion ( Fig. 3 #150 ) are formed by the TFT device layer ( Fig. 3 #220 ) and the LED layer ( Fig. 3 #100 ).
Claim 10: Jeong, Kang, and Li disclose the display panel of claim 8 ( as discussed above).
Neither Jeong nor Kang appear to disclose the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are in a stepped shape as a whole, a third step portion is formed by a part of the second epitaxial layer and the third epitaxial layer, and a fourth step portion is formed by a part of the first epitaxial layer and the second epitaxial layer; and wherein the part of the second epitaxial layer is not covered by the third epitaxial layer, and the part of the first epitaxial layer is not covered by the second epitaxial layer.
However, Li teaches the first epitaxial layer ( Fig. 2B: Epitaxial Layer 210 ), the second epitaxial layer ( Fig. 2B: Epitaxial Layer 220 ), and the third epitaxial layer ( Fig. 2B: Epitaxial Layer 230 ) are in a stepped shape as a whole ( as shown in Fig. 2B ), a third step portion ( Fig. 2B: area where cathode metal pad 258 attaches ) is formed by a part of the second epitaxial layer ( Fig. 2B #220 ) and the third epitaxial layer ( Fig. 2B #230 ), and a fourth step portion ( Fig. 2B: area where cathode metal pad 256 attaches ) is formed by a part of the first epitaxial layer ( Fig. 2B #210 ) and the second epitaxial layer and wherein the part of the second epitaxial layer ( Fig. 2B #220 ) is not covered ( as shown in Fig. 2B the widths narrow as they go up ) by the third epitaxial layer ( Fig. 2B #230 ), and the part of the first epitaxial layer ( Fig. 2B #210 ) is not covered ( as shown in Fig. 2B the widths narrow as they go up ) by the second epitaxial layer ( Fig. 2B #220 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Li with Jeong and Kang to implement the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are in a stepped shape as a whole, a third step portion is formed by a part of the second epitaxial layer and the third epitaxial layer, and a fourth step portion is formed by a part of the first epitaxial layer and the second epitaxial layer and wherein the part of the second epitaxial layer is not covered by the third epitaxial layer, and the part of the first epitaxial layer is not covered by the second epitaxial layer because this facilitates independent electrical contacts for each layer within a confined, high-density, or vertically stacked device.
Claim 12: Jeong, Kang, and Li disclose the display panel of claim 10 ( as discussed above).
Neither Jeong nor Kang appear to disclose edges of two sides of the second epitaxial layer are located within edges of two sides of the first epitaxial layer, respectively, and a fifth step portion and a sixth step portion are formed by the second epitaxial layer and the first epitaxial layer.
However, Li teaches edges of two sides ( as shown in Fig. 2B ) of the second epitaxial layer ( Fig. 2B #220 ) are located within edges of two sides ( as shown in Fig. 2B ) of the first epitaxial layer ( Fig. 2B #210 ) , respectively, and a fifth step portion ( left side of Fig. 2B #210 ) and a sixth step portion ( bottom left side of Fig. 2B #220 ) are formed by the second epitaxial layer ( Fig. 2B #220 ) and the first epitaxial layer ( Fig. 2B #210 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Li with Jeong and Kang to implement edges of two sides of the second epitaxial layer are located within edges of two sides of the first epitaxial layer, respectively, and a fifth step portion and a sixth step portion are formed by the second epitaxial layer and the first epitaxial layer because this is a design technique used to create isolated mesas, expose underlying layers for electrodes, and manage strain/defect density.
Claim 14: Jeong, Kang, and Li disclose the display panel of claim 12 ( as discussed above).
Jeong discloses the TFT device layer comprises a TFT in a convex shape ( Fig. 9 #220 ), and a tenth step portion ( Fig. 9 left side of #220 ) and an eleventh step portion ( Fig. 9 right side of #220 ) are formed by a part of the TFT with a smaller thickness ( Fig. 9 thickness of #205 ) and a part of the TFT with a larger thickness in a cross-sectional view ( Fig. 9. central portion of #220 ).
Neither Jeong nor Kang appear to disclose a seventh step portion is formed by a part of the second epitaxial layer and the third epitaxial layer, wherein the part of the second epitaxial layer is not covered by the third epitaxial layer; edges of two sides of the TFT device layer are located within edges of two sides of the third epitaxial layer, respectively, and an eighth step portion and a ninth step portion are formed by the TFT device layer and the third epitaxial layer.
However, Li teaches a seventh step portion ( Fig. 2B top left side of #220 ) is formed by a part of the second epitaxial layer ( Fig. 2B #220 ) and the third epitaxial layer ( Fig. 2B #230 ), wherein the part of the second epitaxial layer ( Fig. 2B #220 ) is not covered ( as shown in Fig. 2B the layers get smaller as they go up ) by the third epitaxial layer ( Fig. 2B #230 ); edges of two sides of the TFT device layer ( [0021] In some embodiments, the pixel driver comprises a thin-film transistor pixel driver or a silicon CMOS pixel driver ) are located within edges ( as shown in Fig. 2B ) of two sides of the third epitaxial layer ( Fig. 2B #230 ), respectively, and an eighth step portion ( Fig. 2B anode metal pad connects from the pixel driver layer to #230 ) and a ninth step portion ( Fig. 2B cathode metal pad connection connects from the pixel driver layer to #230 ) are formed by the TFT device layer ( as shown in Fig. 2B ) and the third epitaxial layer ( Fig. 2B #230 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Li with Jeong and Kang to implement a seventh step portion is formed by a part of the second epitaxial layer and the third epitaxial layer, wherein the part of the second epitaxial layer is not covered by the third epitaxial layer; edges of two sides of the TFT device layer are located within edges of two sides of the third epitaxial layer, respectively, and an eighth step portion and a ninth step portion are formed by the TFT device layer and the third epitaxial layer because this approach is designed to optimized electrode connectivity, reduce parasitic capacitance, and accommodate the high density integration of transistors on a single pixel.
Claim 18: Jeong, Kang, and Li disclose the display panel of claim 1 ( as discussed above).
Neither Jeong nor Kang appear to disclose a width of the first epitaxial layer, a width of the second epitaxial layer, and a width of the third epitaxial layer in a cross-sectional view are different.
However, Li teaches a width of the first epitaxial layer ( Fig. 2B #210 ), a width of the second epitaxial layer ( Fig. 2B #220), and a width of the third epitaxial layer ( Fig. 2B #230 ) in a cross-sectional view are different ( [0100] Each layer has a narrower width or smaller area compared to a layer beneath it ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Li with Jeong and Kang to implement a width of the first epitaxial layer, a width of the second epitaxial layer, and a width of the third epitaxial layer in a cross-sectional view are different because the mesa-etching process often creates tapered, sloped, or non-vertical sidewalls rather than perfectly vertical ones.
Claims 4 and 6 are rejected under U.S.C. 103 as being unpatentable over Jeong et al.; US 2023/0282631 A1; 01/2023 in view of Kang et al.; US 2022/0208747 A1; 12/2021 and Li et al.; US 2020/0403026 A1; 06/2020 as it relates to claim 1 above and further in view of Lee et al.; US 12,550,512 B2; 12/2021
Claim 4: Jeong, Kang, and Li discloses the display panel of claim 1 ( as discussed above ).
Neither Jeong nor Kang nor Li appear to disclose a surface passivation layer covering a side wall of the TFT device layer and a side wall of the LED layer; and an inline wiring disposed on the surface passivation layer; wherein the surface passivation layer is provided with a via hole, and the inline wiring is connected to the TFT device layer and the LED layer through the via hole.
However, Lee teaches a surface passivation layer ( Fig. 3: PAS1 ) covering a side wall of the TFT device layer ( Fig. 3: TFT; Col. 11 lines 37 – 38 The first passivation layer PAS1 may protect the thin-film transistors TFT ) and a side wall of the LED layer ( Fig. 3 display layer DPL ); and an inline wiring ( Fig. 3: first electrodes CNE1 ) disposed on the surface passivation layer ( Fig. 3: PAS1 ); wherein the surface passivation layer ( Fig. 3: PAS1 ) is provided with a via hole ( Col. 11 lines 38-40 The first passivation layer PAS1 may include contact holes that are penetrated by the first electrodes RME1 ), and the inline wiring ( Fig. 3: CNE1 ) is connected to the TFT device layer ( Fig. 3: TFT ) and the LED layer ( Fig. 3: DPL ) through the via hole ( as discussed above ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Jeong, Kang, and Li to implement a surface passivation layer covering a side wall of the TFT device layer and a side wall of the LED layer; and an inline wiring disposed on the surface passivation layer; wherein the surface passivation layer is provided with a via hole, and the inline wiring is connected to the TFT device layer and the LED layer through the via hole because this improved efficiency in small pixels and also protects against environmental degradation.
Claim 6: Jeong, Kang, Li, and Lee disclose the display panel of claim 4 ( as discussed above).
Neither Jeong nor Kang nor Li appear to disclose a planarization layer disposed on the TFT device layer and covering the surface passivation layer and the inline wiring located on the TFT device layer and the LED layer; and the metal wiring layer disposed on the planarization layer; wherein the TFT device layer comprises a first TFT, a second TFT, and a third TFT, and the metal wiring layer comprises a first data line, a second data line, and a third data line arranged at intervals, and disposed corresponding to the first TFT, the second TFT, and the third TFT, respectively.
However, Lee teaches a planarization layer ( Fig. 3: OC1 ) disposed on the TFT device layer ( Fig. 3: TFT ) and covering the surface passivation layer ( Fig. 3: PAS1 ) and the inline wiring ( Fig. 3: CNE1 ) located on the TFT device layer ( Fig. 3: TFT ) and the LED layer ( Fig. 3: DPL ); and the metal wiring layer ( Fig. 3: RME1 ) disposed on the planarization layer ( Fig. 3: OC1 ) ; wherein the TFT device layer comprises a first TFT, a second TFT, and a third TFT ( Col. 10 lines 22-23 The thin-film transistors TFT may be disposed on the buffer layer BF and may form the pixel circuits of pixels ) , and the metal wiring layer comprises a first data line, a second data line, and a third data line arranged at intervals, and disposed corresponding to the first TFT, the second TFT, and the third TFT, respectively ( Col. 10 lines 65 – 67 The first connecting electrodes CNE1 may electrically connect data lines or power lines to the source electrodes SE of the thin-film transistors TFT )
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Jeong, Kang, and Li to implement a planarization layer disposed on the TFT device layer and covering the surface passivation layer and the inline wiring located on the TFT device layer and the LED layer; and the metal wiring layer disposed on the planarization layer; wherein the TFT device layer comprises a first TFT, a second TFT, and a third TFT, and the metal wiring layer comprises a first data line, a second data line, and a third data line arranged at intervals, and disposed corresponding to the first TFT, the second TFT, and the third TFT, respectively because this approach is designed to solve critical integration challenges with high-resolution, active-matrix driving pixel circuits.
Claim 7 is rejected under U.S.C. 103 as being unpatentable over Jeong et al.; US 2023/0282631 A1; 01/2023 in view of Kang et al.; US 2022/0208747 A1; 12/2021 and Li et al.; US 2020/0403026 A1; 06/2020 as it relates to claim 1 above and further in view of Fan et al.; US 2009/0078955 A1; 09/2008
Claim 7: Jeong, Kang, and Li disclose the display panel of claim 1 ( as discussed above),
Neither Jeong nor Kang nor Li appear to disclose colors of emitted light of the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are different.
However, Fan teaches colors of emitted light of the first epitaxial layer ( Fig. 2A #206; [0047] a first InGaN/GaN multi-quantum well (MQW) active region 208 with indium concentration corresponding to blue emission ), the second epitaxial layer ( Fig. 2A #214; [0047] a second InGaN/GaN MQW region 216 with suitable indium concentration for green emission ), and the third epitaxial layer are different ( Fig. 2A #218; [0047]; a third InGaN/GaN MQW region 220 with suitable indium concentration for red emission ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Fan with Jeong, Kang, and Li to implement colors of emitted light of the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are different because this allows for the creation full color RGB pixels from a single micro-chip.
Claim 9 is rejected under U.S.C. 103 as being unpatentable over Jeong et al.; US 2023/0282631 A1; 01/2023 in view of Kang et al.; US 2022/0208747 A1; 12/2021 and Li et al.; US 2020/0403026 A1; 06/2020 as it relates to claim 8 above and further in view of Li et al.; US 2025/0386635 A1; PCT filed 08/2022
Claim 9: Jeong, Kang, and Li (‘026) disclose the display panel of claim 8 ( as discussed above).
Neither Jeong nor Kang nor Li (‘026) appear to disclose the metal wiring layer comprises a first power line and a second power line arranged at intervals, wherein the first power line is disposed corresponding to the second step portion, and the second power line is disposed corresponding to the first step portion.
However, Li (‘635) teaches the metal wiring layer ( Fig. 7 ) comprises a first power line ( Fig. 7: VDD ) and a second power line ( Fig. 7: VSS ) arranged at intervals ( as shown in Fig. 7 ), wherein the first power line ( Fig. 7: VDD ) is disposed corresponding to the second step portion ( Fig. 9 SE1; [0076] The first source electrode SE1 is electrically connected to the first power line VDD ), and the second power line ( Fig. 7: VSS ) is disposed corresponding to the first step portion ( Fig. 9 #1615; [0074] Referring to FIG. 9, the light-emitting device 161 further includes a second pin 1615 electrically connected to the second power line VSS ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Li (‘635) with Jeong and Kang and Li (‘026) to implement the metal wiring layer comprises a first power line and a second power line arranged at intervals, wherein the first power line is disposed corresponding to the second step portion, and the second power line is disposed corresponding to the first step portion because this improves step coverage and electrical connectivity.
Claims 19 and 20 are rejected under U.S.C. 103 as being unpatentable over Jeong et al.; US 2023/0282631 A1; 01/2023 in view of Chae et al.; US 2019/0189681 A1; 12/2018, Kang et al.; US 2022/0208747 A1; 12/2021 and Li et al.; US 2020/0403026 A1; 06/2020
Claim 19: Jeong discloses a method for preparing a display panel ( Fig. 9 #10D), comprising: providing a substrate ( Fig. 9 upper layer 111’); providing three types of epitaxial wafers ( Fig. 9 #116, #114, and #112 ) with different colors of emitted light ( Fig. 2: RGB colors ) and forming at least one epitaxial layer ( Fig. 9 #112 ) on the substrate ( [0107] In an example embodiment, the upper layer 111’ may be a substrate for growing epitaxial layers 112, 114, and 116 of LED cells 110’ ); bonding the at least one epitaxial layer ( Fig. 9 #112 is bonded to the other layers ) and forming a stacked epitaxial layer ( [0113] the stack structure of the first conductivity-type semiconductor layer 112, the active layer 114, the second conductivity-type semiconductor layer 116, and the contact layer 155, the LED cells 110 may be formed ); forming a thin film transistor (TFT) device layer ( Fig. 3 driving elements #220; [0032] driving elements #220 including TFT cells formed on the semiconductor substrate ) on the stacked epitaxial layer ( as shown in Fig. 9 ); processing the stacked epitaxial layer and the TFT device layer to form a plurality of independent lighting-emitting diode (LED) units ( Fig. 2 RGB pixels ) and a plurality of independent TFT units ( as shown in Fig. 5 ), and etching each of the independent LED units to form a N region ( [0012] The first conductivity-type semiconductor layer 112 may be an n-type nitride semiconductor layer such as n-type GaN ) and a P region ( [0112] the second conductivity-type semiconductor layer 116 may be a p-type nitride semiconductor layer such as p-type GaN/p-type AlGaN ), and a co-N structure or a co-P structure ( [0043] each of the first conductivity-type semiconductor layer 112 and the second conductivity-type semiconductor layer 116 may also include a plurality of layers having different properties such as doping concentration and composition ); forming a planarization layer ( Fig. 3 planarization layer 184 ) on the TFT device layer ( Fig. 3 #220 ), forming a via hole ( Fig. 11F: OT ) on the planarization layer ( Fig. 3 #184 ), and forming a metal wiring layer ( Fig. 11F #199 ) on the planarization layer ( Fig. 3 #184 ); and forming a surface insulation layer ( Fig. 3 encapsulation layer 182 ) on the metal wiring layer ( Fig. 11F #199 ).
Jeong does not appear to disclose each of the independent LED units comprises a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer disposed in a stack, and each of the independent LED units is located between the substrate and one of the TFT units in a thickness direction of the display panel; wherein a first bonding layer, a first filter layer, and a first transparent conductive layer are sequentially disposed between the first epitaxial layer and the second epitaxial layer, and the first bonding layer is in contact with a surface of the first epitaxial layer facing the second epitaxial layer; and wherein a second bonding layer, a second filter layer, and a second transparent conductive layer are sequentially disposed between the second epitaxial layer and the third epitaxial layer, and the second bonding layer is in contact with a surface of the second epitaxial layer facing the third epitaxial layer.
Chae discloses each of the independent LED units ( Fig. 2A 20, 30, and 40 ) comprises a first epitaxial layer ( Fig. 2A 20 ), a second epitaxial layer ( Fig. 2A 30 ), and a third epitaxial layer ( Fig. 20 40 ) disposed in a stack ( as shown in Fig. 2A ).
Chae does not appear to disclose each of the independent LED units is located between the substrate and one of the TFT units in a thickness direction of the display panel; wherein a first bonding layer, a first filter layer, and a first transparent conductive layer are sequentially disposed between the first epitaxial layer and the second epitaxial layer, and the first bonding layer is in contact with a surface of the first epitaxial layer facing the second epitaxial layer; and wherein a second bonding layer, a second filter layer, and a second transparent conductive layer are sequentially disposed between the second epitaxial layer and the third epitaxial layer, and the second bonding layer is in contact with a surface of the second epitaxial layer facing the third epitaxial layer.
Kang discloses each of the independent LED units ( Fig. 3 multiple micro LEDs 51, 52, 53 ) is located between the substrate ( [0073] Referring to Fig. 3, the polarizing member 90 may be formed roughly in a plate form, and may include a transparent glass substrate 91 and a circular polarizing layer 93 stacked at one surface of the glass substrate 91 ) and one of the TFT units ( Fig. 3 TFT substrate 20 ) in a thickness direction of the display panel ( as shown in Fig. 3 ).
Kang does not appear to disclose a first bonding layer, a first filter layer, and a first transparent conductive layer are sequentially disposed between the first epitaxial layer and the second epitaxial layer, and the first bonding layer is in contact with a surface of the first epitaxial layer facing the second epitaxial layer; and wherein a second bonding layer, a second filter layer, and a second transparent conductive layer are sequentially disposed between the second epitaxial layer and the third epitaxial layer, and the second bonding layer is in contact with a surface of the second epitaxial layer facing the third epitaxial layer.
However, Li teaches a first bonding layer ( Fig. 2B: Transparent Bonding Layer 216 ), a first filter layer ( Fig. 2B: Reflection Layer 214 ), and a first transparent conductive layer ( [0075] In some embodiments, conductive transparent layers are formed between the LED epitaxial layers to improve conductivity and transparency ) are sequentially disposed between the first epitaxial layer ( Fig. 2B: Epitaxial Layer 210 ) and the second epitaxial layer ( Fig. 2B: Epitaxial Layer 220 ), and the first bonding layer is in contact with a surface of the first epitaxial layer facing the second epitaxial layer ( [0086] In some embodiments, a second epitaxial layer 220 is bonded on top of the first epitaxial layer 210 through the transparent bonding layer 216 ); and wherein a second bonding layer ( Fig. 2B #226 ), a second filter layer ( Fig. 2B third reflection layer 224 ), and a second transparent conductive layer ( Fig. 2B ITO layer 228) are sequentially disposed between the second epitaxial layer ( Fig. 2B #220 ) and the third epitaxial layer ( Fig. 2B #230 ), and the second bonding layer is in contact with a surface of the second epitaxial layer facing the third epitaxial layer ( [0094] In some embodiments, a third epitaxial layer 230 is bonded on top of the second epitaxial layer 220 through the transparent bonding layer 226 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Li with Jeong, Chae, and Kang to implement each of the independent LED units comprises a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer disposed in a stack, and each of the independent LED units is located between the substrate and one of the TFT units in a thickness direction of the display panel; wherein a first bonding layer, a first filter layer, and a first transparent conductive layer are sequentially disposed between the first epitaxial layer and the second epitaxial layer, and the first bonding layer is in contact with a surface of the first epitaxial layer facing the second epitaxial layer; and wherein a second bonding layer, a second filter layer, and a second transparent conductive layer are sequentially disposed between the second epitaxial layer and the third epitaxial layer, and the second bonding layer is in contact with a surface of the second epitaxial layer facing the third epitaxial layer because this approach provides a defect-minimized, crystalline foundation, and enables controlled electrical and optical properties essential for light emission.
Claim 20: Jeong, Chae, Kang, and Li disclose the method for preparing the display panel of claim 19 ( as discussed above).
Jeong teaches the step of forming at least one epitaxial layer comprises: enabling the three types of epitaxial wafers to grow individually, to form the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer, respectively; or, enabling any two epitaxial wafers among the three types of epitaxial wafers to grow together to form the first epitaxial layer, and enabling another epitaxial wafer among the three types of epitaxial wafers to grow individually to form the second epitaxial layer; or, enabling the three types of epitaxial wafers to grow together to form an epitaxial layer ( [0036] The pixel array 100 may include a semiconductor stack SL. In the present example embodiment, the semiconductor stack SL may be understood as an epitaxial layer continuously grown on one growth substrate; [0045] As described above, the upper semiconductor layer 111 may include a nitride epitaxial layer continuously grown with the first conductivity-type semiconductor layer 112, the active layer 114, and the second conductivity-type semiconductor layer 116 ).
Claim 21 is rejected under U.S.C. 103 as being unpatentable over Jeong et al.; US 2023/0282631 A1; 01/2023 in view of Kang et al.; US 2022/0208747 A1; 12/2021 and Li et al.; US 2020/0403026 A1; 06/2020 as it relates to claim 1 above and further in view of Lei et al.; US 2023/0335518 A1; 04/2022
Claim 21: Jeong, Kang, and Li disclose the display panel of claim 1 ( as discussed above).
Neither Jeong nor Kang appear to disclose a material of the first bonding layer and a material of the second bonding layer each comprise at least one of indium (In) and tin (Sn); and wherein a material of the first transparent conductive layer and a material of the second transparent conductive layer each comprise indium tin oxide (ITO).
However, Lei teaches a material of the first bonding layer ( [0113] In some embodiments, first wafer 802 may also include a bonding layer. Bonding layer 812 may include various materials, such as a metal, an oxide, a dielectric, CuSn, AuTi, or the like.) and a material of the second bonding layer ( [0114] Bonding layer 812 and bonding layer 813 may be made of the same material or different materials ) each comprise at least one of indium (In) and tin (Sn) ( as discussed above); and wherein a material of the first transparent conductive layer ( [0099] Conductive layer 760 may include, for example, an indium tin oxide (ITO) or Al/Ni/Au film. In one example, conductive layer 760 may include a transparent ITO layer ) and a material of the second transparent conductive layer ( [0106] an additional conductive layer (not shown) may be included as an intermediate conductive layer between the electrical contacts 765 and 785 and the semiconductor layers ) each comprise indium tin oxide (ITO) ( as discussed above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lei with Jeong, Kang, and Li to implement a material of the first bonding layer and a material of the second bonding layer each comprise at least one of indium (In) and tin (Sn); and wherein a material of the first transparent conductive layer and a material of the second transparent conductive layer each comprise indium tin oxide (ITO) because this approach ensures strong, transparent adhesion between display and cover substrates.
Response to Amendments / Arguments
Applicant’s arguments, see page 9-10 of remarks, filed 05/18/2026, with respect to Drawings have been fully considered and are persuasive. The objection of 03/04/2026 has been withdrawn.
Applicant’s arguments, see page 10 of remarks, filed 05/18/2026, with respect to Drawings have been fully considered and are persuasive. The objection of 03/04/2026 has been withdrawn.
Applicant’s arguments, see page 10 of remarks, filed 05/18/2026, with respect to the rejection of claims 10 and 14 under 35 U.S.C. 112 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
Applicant’s arguments, see pages 11-12 of remarks, filed 05/18/2026, with respect to the rejection of claims 1, 3, 5, 8, 19, and 20 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Li for claims 1,3,5, and 8 and in view of Chae and Li for claims 19 and 20.
Applicant’s arguments, see pages 1, filed 05/18/2026, with respect to the rejection of claims 2, 10, 12, 14, and 18 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Li for claims 1 and in view of Li. Claim 2 was canceled.
Applicant's arguments, see page 15 of remarks, filed 05/18/2026, with respect to the rejection of claims 4, 6-7, 9-16, and 18 under 35 U.S.C. 103 have been fully considered but they are not persuasive. As discussed above, the rejection of claim 1 is maintained in view of Li so the rejection of the dependent claims is maintained.
Allowable Subject Matter
Claim 22 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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