DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CN202310301692.2, filed on 03/13/2023.
Drawings
The drawings are not of sufficient quality to permit examination. Accordingly, replacement drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to this Office action. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action.
Applicant is given a shortened statutory period of TWO (2) MONTHS to submit new drawings in compliance with 37 CFR 1.81. Extensions of time may be obtained under the provisions of 37 CFR 1.136(a) but in no case can any extension carry the date for reply to this letter beyond the maximum period of SIX MONTHS set by statute (35 U.S.C. 133). Failure to timely submit replacement drawing sheets will result in ABANDONMENT of the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claim language that is not clear is “by the third epitaxial layer and the third epitaxial layer” and “by the second epitaxial layer and the second epitaxial layer.”
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claim language that is not clear is “by the third epitaxial layer and the third epitaxial layer”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 5, 8, 19, and 20 are rejected under 35 U.S.C. 102 as being anticipated by Jeong et al. ( US 2023/0282631 A1; hereinafter Jeong )
Regarding claim 1, Jeong teaches a display panel ( Fig. 9 display apparatus #10D ) comprising: a substrate ( Fig. 9 substrate #111’ ); a lighting-emitting diode (LED) layer ( Fig. 9 LED cells #110’ ) disposed on the substrate ( Fig. 9 substrate #111’ ) and comprising a first epitaxial layer ( Fig. 9 #116) , a second epitaxial layer ( Fig. 9 #114 ), and a third epitaxial layer ( Fig. 9 #112 ) disposed in stack ( [0113] the stack structure of the first conductivity-type semiconductor layer 112, the active layer 114, the second conductivity-type semiconductor layer 116, and the contact layer 155, the LED cells 110 may be formed ); a thin film transistor (TFT) device layer ( Fig. 3 driving elements #220; [0032] driving elements #220 including TFT cells formed on the semiconductor substrate; [0104] Fig. 9 is a schematic cross-sectional view of a display apparatus according to an example embodiment, and may be understood as a cross-section corresponding to the cross-section corresponding to FIG. 3 ) disposed on the LED layer ( Fig. 3 #100 ), wherein the TFT device layer ( Fig. 3 #220 ) and the LED layer ( Fig. 3 #100 ) form a longitudinal integrated structure ( [0034] The source region 205 of the TFT cells may be electrically connected to one electrode of LED cells 110 through the interconnections 230 ); and a metal wiring layer ( Fig. 3 #230 ) disposed on the TFT device layer ( Fig. 3 #220 ) and configured to provide a driving signal for the display panel ( [0034] The source region 205 of the TFT cells may be electrically connected to one electrode of LED cells 110 through the interconnections 230 ).
Regarding claim 3, Jeong teaches the display panel of claim 1 ( as discussed above), wherein a reflective layer ( Fig. 9 partition reflective layer #170 ) is disposed on the third epitaxial layer ( Fig. 9 #112 ).
Regarding claim 5, Jeong teaches the display panel of claim 1 ( as discussed above), comprising a plurality of micro light-emitting diode (Micro LED) display units ( [0037] The plurality of LED cells 110 may respectively be a micro LED ) arranged in an array ( as shown in Fig. 2) , wherein each of the plurality of Micro LED display units comprises a first pixel ( Fig. 2: SP1 ), a second pixel ( Fig. 2: SP2 ), and a third pixel ( Fig. 2: SP3 ); wherein the TFT device layer comprises a first TFT ( Fig. 3 #220 connected to SP1), a second TFT ( Fig. 3 #220 connected to SP2 ), and a third TFT ( Fig. 3 #220 connected to SP3 ) disposed corresponding to the first pixel ( Fig. 3: SP1 ), the second pixel ( Fig. 3: SP2 ), and the third pixel ( Fig. 3: SP3 ), respectively.
Regarding claim 8, Jeong teaches the display panel of claim 1 ( as discussed above), wherein a first step portion ( Fig. 3 #240 ) and a second step portion ( Fig. 3 #150 ) are formed by the TFT device layer ( Fig. 3 #220 ) and the LED layer ( Fig. 3 #100 ).
Regarding claim 19, Jeong teaches a method for preparing a display panel ( Fig. 9 #10D), comprising: providing three types of epitaxial wafers ( Fig. 9 #116, #114, and #112 ) with different colors of emitted light ( Fig. 2: RGB colors ) and forming at least one epitaxial layer ( Fig. 9 #112 ); bonding the at least one epitaxial layer ( Fig. 9 #112 is bonded to the other layers ) and forming a stacked epitaxial layer ( [0113] the stack structure of the first conductivity-type semiconductor layer 112, the active layer 114, the second conductivity-type semiconductor layer 116, and the contact layer 155, the LED cells 110 may be formed ); forming a thin film transistor (TFT) device layer ( Fig. 3 driving elements #220; [0032] driving elements #220 including TFT cells formed on the semiconductor substrate ) on the stacked epitaxial layer ( as shown in Fig. 9 ); processing the stacked epitaxial layer and the TFT device layer to form a plurality of independent lighting-emitting diode (LED) units ( Fig. 2 RGB pixels ) and a plurality of independent TFT units ( as shown in Fig. 5 ), and etching each of the independent LED units to form a N region ( [0012] The first conductivity-type semiconductor layer 112 may be an n-type nitride semiconductor layer such as n-type GaN ) and a P region ( [0112] the second conductivity-type semiconductor layer 116 may be a p-type nitride semiconductor layer such as p-type GaN/p-type AlGaN ), and a co-N structure or a co-P structure ( [0043] each of the first conductivity-type semiconductor layer 112 and the second conductivity-type semiconductor layer 116 may also include a plurality of layers having different properties such as doping concentration and composition ); forming a planarization layer ( Fig. 3 planarization layer 184 ) on the TFT device layer ( Fig. 3 #220 ), forming a via hole ( Fig. 11F: OT ) on the planarization layer ( Fig. 3 #184 ), and forming a metal wiring layer ( Fig. 11F #199 ) on the planarization layer ( Fig. 3 #184 ); and forming a surface insulation layer ( Fig. 3 encapsulation layer 182 ) on the metal wiring layer ( Fig. 11F #199 ).
Regarding claim 20, Jeong teaches the method for preparing the display panel of claim 19 ( as discussed above), wherein the step of forming at least one epitaxial layer comprises: enabling the three types of epitaxial wafers to grow individually, to form a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, respectively; or, enabling any two epitaxial wafers among the three types of epitaxial wafers to grow together to form a first epitaxial layer, and enabling another epitaxial wafer among the three types of epitaxial wafers to grow individually to form a second epitaxial layer; or, enabling the three types of epitaxial wafers to grow together to form an epitaxial layer ( [0036] The pixel array 100 may include a semiconductor stack SL. In the present example embodiment, the semiconductor stack SL may be understood as an epitaxial layer continuously grown on one growth substrate; [0045] As described above, the upper semiconductor layer 111 may include a nitride epitaxial layer continuously grown with the first conductivity-type semiconductor layer 112, the active layer 114, and the second conductivity-type semiconductor layer 116 ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under U.S.C. 103 as being unpatentable over Jeong et al.; US 2023/0282631 A1; 01/2023 in view of Li et al.; US 2020/0403026 A1; 06/2020
Claim 2: Jeong discloses the display panel of claim 1 ( as discussed above).
Jeong does not appear to disclose a first bonding layer, a first filter layer, and a first transparent conductive layer are sequentially disposed between the first epitaxial layer and the second epitaxial layer; and a second bonding layer, a second filter layer, and a second transparent metal layer are sequentially disposed between the second epitaxial layer and the third epitaxial layer.
However, Li teaches a first bonding layer ( Fig. 2B: Transparent Bonding Layer 216 ), a first filter layer ( Fig. 2B: Reflection Layer 214 ), and a first transparent conductive layer ( [0075] In some embodiments, conductive transparent layers are formed between the LED epitaxial layers to improve conductivity and transparency ) are sequentially disposed between the first epitaxial layer ( Fig. 2B: Epitaxial Layer 210 ) and the second epitaxial layer ( Fig. 2B: Epitaxial Layer 220 ); and a second bonding layer ( Fig. 2B: Transparent Bonding Layer 226 ), a second filter layer ( Fig. 2B: Reflection Layer 224 ), and a second transparent metal layer ( [0075] In some embodiments, conductive transparent layers are formed between the LED epitaxial layers to improve conductivity and transparency ) are sequentially disposed between the second epitaxial layer ( Fig. 2B #220 ) and the third epitaxial layer ( Fig. 2B: Epitaxial Layer 230 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Li with Jeong to implement a first bonding layer, a first filter layer, and a first transparent conductive layer are sequentially disposed between the first epitaxial layer and the second epitaxial layer; and a second bonding layer, a second filter layer, and a second transparent metal layer are sequentially disposed between the second epitaxial layer and the third epitaxial layer because this controls crosstalk and improves overall performance.
Claims 4 and 6 are rejected under U.S.C. 103 as being unpatentable over Jeong et al.; US 2023/0282631 A1; 01/2023 in view of Lee et al.; US 12,550,512 B2; 12/2021
Claim 4: Jeong discloses the display panel of claim 1 ( as discussed above ).
Jeong does not appear to disclose a surface passivation layer covering a side wall of the TFT device layer and a side wall of the LED layer; and an inline wiring disposed on the surface passivation layer; wherein the surface passivation layer is provided with a via hole, and the inline wiring is connected to the TFT device layer and the LED layer through the via hole.
Lee teaches a surface passivation layer ( Fig. 3: PAS1 ) covering a side wall of the TFT device layer ( Fig. 3: TFT; Col. 11 lines 37 – 38 The first passivation layer PAS1 may protect the thin-film transistors TFT ) and a side wall of the LED layer ( Fig. 3 display layer DPL ); and an inline wiring ( Fig. 3: first electrodes CNE1 ) disposed on the surface passivation layer ( Fig. 3: PAS1 ); wherein the surface passivation layer ( Fig. 3: PAS1 ) is provided with a via hole ( Col. 11 lines 38-40 The first passivation layer PAS1 may include contact holes that are penetrated by the first electrodes RME1 ), and the inline wiring ( Fig. 3: CNE1 ) is connected to the TFT device layer ( Fig. 3: TFT ) and the LED layer ( Fig. 3: DPL ) through the via hole ( as discussed above ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Jeong to implement a surface passivation layer covering a side wall of the TFT device layer and a side wall of the LED layer; and an inline wiring disposed on the surface passivation layer; wherein the surface passivation layer is provided with a via hole, and the inline wiring is connected to the TFT device layer and the LED layer through the via hole because this improved efficiency in small pixels and also protects against environmental degradation.
Claim 6: Jeong and Lee disclose the display panel of claim 4 ( as discussed above).
Jeong does not appear to disclose a planarization layer disposed on the TFT device layer and covering the surface passivation layer and the inline wiring located on the TFT device layer and the LED layer; and the metal wiring layer disposed on the planarization layer; wherein the TFT device layer comprises a first TFT, a second TFT, and a third TFT, and the metal wiring layer comprises a first data line, a second data line, and a third data line arranged at intervals, and disposed corresponding to the first TFT, the second TFT, and the third TFT, respectively.
Lee teaches a planarization layer ( Fig. 3: OC1 ) disposed on the TFT device layer ( Fig. 3: TFT ) and covering the surface passivation layer ( Fig. 3: PAS1 ) and the inline wiring ( Fig. 3: CNE1 ) located on the TFT device layer ( Fig. 3: TFT ) and the LED layer ( Fig. 3: DPL ); and the metal wiring layer ( Fig. 3: RME1 ) disposed on the planarization layer ( Fig. 3: OC1 ) ; wherein the TFT device layer comprises a first TFT, a second TFT, and a third TFT ( Col. 10 lines 22-23 The thin-film transistors TFT may be disposed on the buffer layer BF and may form the pixel circuits of pixels ) , and the metal wiring layer comprises a first data line, a second data line, and a third data line arranged at intervals, and disposed corresponding to the first TFT, the second TFT, and the third TFT, respectively ( Col. 10 lines 65 – 67 The first connecting electrodes CNE1 may electrically connect data lines or power lines to the source electrodes SE of the thin-film transistors TFT )
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Jeong to implement a planarization layer disposed on the TFT device layer and covering the surface passivation layer and the inline wiring located on the TFT device layer and the LED layer; and the metal wiring layer disposed on the planarization layer; wherein the TFT device layer comprises a first TFT, a second TFT, and a third TFT, and the metal wiring layer comprises a first data line, a second data line, and a third data line arranged at intervals, and disposed corresponding to the first TFT, the second TFT, and the third TFT, respectively because this approach is designed to solve critical integration challenges with high-resolution, active-matrix driving pixel circuits.
Claim 7 is rejected under U.S.C. 103 as being unpatentable over Jeong et al.; US 2023/0282631 A1; 01/2023 in view of Fan et al.; US 2009/0078955 A1; 09/2008
Claim 7: Jeong discloses the display panel of claim 1 ( as discussed above),
Jeong does not appear to disclose colors of emitted light of the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are different.
However, Fan teaches colors of emitted light of the first epitaxial layer ( Fig. 2A #206; [0047] a first InGaN/GaN multi-quantum well (MQW) active region 208 with indium concentration corresponding to blue emission ), the second epitaxial layer ( Fig. 2A #214; [0047] a second InGaN/GaN MQW region 216 with suitable indium concentration for green emission ), and the third epitaxial layer are different ( Fig. 2A #218; [0047]; a third InGaN/GaN MQW region 220 with suitable indium concentration for red emission ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Fan with Jeong to implement colors of emitted light of the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are different because this allows for the creation full color RGB pixels from a single micro-chip.
Claim 9 is rejected under U.S.C. 103 as being unpatentable over Jeong et al.; US 2023/0282631 A1; 01/2023 in view of Li et al.; US 2025/0386635 A1; PCT filed 08/2022
Claim 9: Jeong discloses the display panel of claim 8 ( as discussed above).
Jeong does not appear to disclose the metal wiring layer comprises a first power line and a second power line arranged at intervals, wherein the first power line is disposed corresponding to the second step portion, and the second power line is disposed corresponding to the first step portion.
However, Li (‘635) teaches the metal wiring layer ( Fig. 7 ) comprises a first power line ( Fig. 7: VDD ) and a second power line ( Fig. 7: VSS ) arranged at intervals ( as shown in Fig. 7 ), wherein the first power line ( Fig. 7: VDD ) is disposed corresponding to the second step portion ( Fig. 9 SE1; [0076] The first source electrode SE1 is electrically connected to the first power line VDD ), and the second power line ( Fig. 7: VSS ) is disposed corresponding to the first step portion ( Fig. 9 #1615; [0074] Referring to FIG. 9, the light-emitting device 161 further includes a second pin 1615 electrically connected to the second power line VSS ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Li (‘635) with Jeong to implement the metal wiring layer comprises a first power line and a second power line arranged at intervals, wherein the first power line is disposed corresponding to the second step portion, and the second power line is disposed corresponding to the first step portion because this improves step coverage and electrical connectivity.
Claims 10, 12, 14, and 18 are rejected under U.S.C. 103 as being unpatentable over Jeong et al.; US 2023/0282631 A1; 01/2023 in view of Li et al.; US 2020/0403026 A1; 06/2020
Claim 10: Jeong discloses the display panel of claim 8 ( as discussed above).
Jeong does not appear to disclose the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are in a stepped shape as a whole, a third step portion is formed by a part of the second epitaxial layer not covered by the third epitaxial layer and the third epitaxial layer, and a fourth step portion is formed by a part of the first epitaxial layer not covered by the second epitaxial layer and the second epitaxial layer.
However, Li (‘026) teaches the first epitaxial layer ( Fig. 2B: Epitaxial Layer 210 ), the second epitaxial layer ( Fig. 2B: Epitaxial Layer 220 ), and the third epitaxial layer ( Fig. 2B: Epitaxial Layer 230 ) are in a stepped shape as a whole ( as shown in Fig. 2B ), a third step portion ( Fig. 2B: area where cathode metal pad 258 attaches ) is formed by a part of the second epitaxial layer ( Fig. 2B #220 ) not covered by the third epitaxial layer ( Fig. 2B #230 ) and the third epitaxial layer ( Fig. 2B #230 ), and a fourth step portion ( Fig. 2B: area where cathode metal pad 256 attaches ) is formed by a part of the first epitaxial layer ( Fig. 2B #210 ) not covered by the second epitaxial layer ( Fig. 2B #220 ) and the second epitaxial layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Li (‘026) with Jeong to implement the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are in a stepped shape as a whole, a third step portion is formed by a part of the second epitaxial layer not covered by the third epitaxial layer and the third epitaxial layer, and a fourth step portion is formed by a part of the first epitaxial layer not covered by the second epitaxial layer and the second epitaxial layer because this facilitates independent electrical contacts for each layer within a confined, high-density, or vertically stacked device.
Claim 12: Jeong and Li (‘026 ) disclose the display panel of claim 10 ( as discussed above).
Jeong does not appear to disclose edges of two sides of the second epitaxial layer are located within edges of two sides of the first epitaxial layer, respectively, and a fifth step portion and a sixth step portion are formed by the second epitaxial layer and the first epitaxial layer.
However, Li (‘026) teaches edges of two sides ( as shown in Fig. 2B ) of the second epitaxial layer ( Fig. 2B #220 ) are located within edges of two sides ( as shown in Fig. 2B ) of the first epitaxial layer ( Fig. 2B #210 ) , respectively, and a fifth step portion ( left side of Fig. 2B #210 ) and a sixth step portion ( bottom left side of Fig. 2B #220 ) are formed by the second epitaxial layer ( Fig. 2B #220 ) and the first epitaxial layer ( Fig. 2B #210 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Li (‘026) with Jeong to implement edges of two sides of the second epitaxial layer are located within edges of two sides of the first epitaxial layer, respectively, and a fifth step portion and a sixth step portion are formed by the second epitaxial layer and the first epitaxial layer because this is a design technique used to create isolated mesas, expose underlying layers for electrodes, and manage strain/defect density.
Claim 14: Jeong and Li (‘026) disclose the display panel of claim 12 ( as discussed above).
Jeong discloses the TFT device layer comprises a TFT in a convex shape ( Fig. 9 #220 ), and a tenth step portion ( Fig. 9 left side of #220 ) and an eleventh step portion ( Fig. 9 right side of #220 ) are formed by a part of the TFT with a smaller thickness ( Fig. 9 thickness of #205 ) and a part of the TFT with a larger thickness in a cross-sectional view ( Fig. 9. central portion of #220 ).
Jeong does not appear to disclose a seventh step portion is formed by a part of the second epitaxial layer not covered by the third epitaxial layer and the third epitaxial layer; edges of two sides of the TFT device layer are located within edges of two sides of the third epitaxial layer, respectively, and an eighth step portion and a ninth step portion are formed by the TFT device layer and the third epitaxial layer.
However, Li (‘026) teaches a seventh step portion ( Fig. 2B top left side of #220 ) is formed by a part of the second epitaxial layer ( Fig. 2B #220 ) not covered by the third epitaxial layer ( Fig. 2B #230 ) and the third epitaxial layer ( Fig. 2B #230 ); edges of two sides of the TFT device layer ( [0021] In some embodiments, the pixel driver comprises a thin-film transistor pixel driver or a silicon CMOS pixel driver ) are located within edges ( as shown in Fig. 2B ) of two sides of the third epitaxial layer ( Fig. 2B #230 ), respectively, and an eighth step portion ( Fig. 2B anode metal pad connects from the pixel driver layer to #230 ) and a ninth step portion ( Fig. 2B cathode metal pad connection connects from the pixel driver layer to #230 ) are formed by the TFT device layer ( as shown in Fig. 2B ) and the third epitaxial layer ( Fig. 2B #230 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Li (‘026) with Jeong to implement a seventh step portion is formed by a part of the second epitaxial layer not covered by the third epitaxial layer and the third epitaxial layer; edges of two sides of the TFT device layer are located within edges of two sides of the third epitaxial layer, respectively, and an eighth step portion and a ninth step portion are formed by the TFT device layer and the third epitaxial layer because this approach is designed to optimized electrode connectivity, reduce parasitic capacitance, and accommodate the high density integration of transistors on a single pixel.
Claim 18: Jeong discloses the display panel of claim 1 ( as discussed above).
Jeong does not appear to disclose a width of the first epitaxial layer, a width of the second epitaxial layer, and a width of the third epitaxial layer in a cross-sectional view are different.
However, Li (‘026) teaches a width of the first epitaxial layer ( Fig. 2B #210 ), a width of the second epitaxial layer ( Fig. 2B #220), and a width of the third epitaxial layer ( Fig. 2B #230 ) in a cross-sectional view are different ( [0100] Each layer has a narrower width or smaller area compared to a layer beneath it ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Li (‘026) with Jeong to implement a width of the first epitaxial layer, a width of the second epitaxial layer, and a width of the third epitaxial layer in a cross-sectional view are different because the mesa-etching process often creates tapered, sloped, or non-vertical sidewalls rather than perfectly vertical ones.
Claims 11, 13, and 15-17 are rejected under U.S.C. 103 as being unpatentable over Jeong et al.; US 2023/0282631 A1; 01/2023 in view of Li et al.; US 2020/0403026 A1; 06/2020 and further in view of Lee et al.; US 12,550,512 B2; 12/2021
Claim 11: Jeong and Li (‘026) disclose the display panel of claim 10 ( as discussed above).
Neither Jeong nor Li (‘026) appear to disclose a surface passivation layer and an inline wiring disposed on the surface passivation layer; wherein the surface passivation layer covers a side wall of the TFT device layer and a side wall of the LED layer; and wherein the inline wiring comprises a first inline wiring and a second inline wiring, parts of the surface passivation layer located on the third step portion and the fourth step portion are provided with a first via hole and a second via hole, respectively; and the first inline wiring is connected to the LED layer through the first via hole, and the second inline wiring is connected to the LED layer through the second via hole.
However, Lee teaches a surface passivation layer ( Fig. 3: PAS1 ) and an inline wiring ( Fig. 3: CNE1 ) disposed on the surface passivation layer ( Fig. 3: PAS1 ); wherein the surface passivation layer ( Fig. 3: PAS1 ) covers a side wall of the TFT device layer ( Fig. 3: TFT; Col. 11 lines 37 – 38 The first passivation layer PAS1 may protect the thin-film transistors TFT ) and a side wall of the LED layer ( Fig. 3 display layer DPL ); and wherein the inline wiring ( Fig. 3: CNE1 ) comprises a first inline wiring ( Fig. 3: CNE1 in area LA1 ) and a second inline wiring ( Fig. 3: CNE1 in area LA2 ) , parts of the surface passivation layer ( Fig. 3: PAS1 ) located on the third step portion ( Fig. 3: CNE2 in area LA1 ) and the fourth step portion ( Fig. 3: CNE2 in area LA2 ) are provided with a first via hole ( Col. 11 lines 38-40 The first passivation layer PAS1 may include contact holes that are penetrated by the first electrodes RME1 ) and a second via hole ( as discussed above ), respectively; and the first inline wiring ( Fig. 3: CNE1 ) is connected to the LED layer ( Fig. 3 display layer DPL ) through the first via hole ( as shown in Fig. 3 ), and the second inline wiring ( Fig. 3: CNE1 in area LA2 ) is connected to the LED layer ( Fig. 3: display layer DPL ) through the second via hole ( Fig. 3: in area LA2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Jeong and Li (‘026) to implement a surface passivation layer and an inline wiring disposed on the surface passivation layer; wherein the surface passivation layer covers a side wall of the TFT device layer and a side wall of the LED layer; and wherein the inline wiring comprises a first inline wiring and a second inline wiring, parts of the surface passivation layer located on the third step portion and the fourth step portion are provided with a first via hole and a second via hole, respectively; and the first inline wiring is connected to the LED layer through the first via hole, and the second inline wiring is connected to the LED layer through the second via hole because this approach allows for sidewall passivation and defect mitigation as device sizes shrink.
Claim 13: Jeong and Li (‘026) disclose the display panel of claim 12 ( as discussed above).
Neither Jeong nor Li (‘026) appear to disclose a surface passivation layer and an inline wiring disposed on the surface passivation layer; wherein the surface passivation layer covers a side wall of the TFT device layer and a side wall of the LED layer; and wherein the inline wiring comprises a third inline wiring and a fourth inline wiring, parts of the surface passivation layer located on the fifth step portion and the sixth step portion are provided with a third via hole and a fourth via hole, respectively; and the third inline wiring is connected to the LED layer through the third via hole, and the fourth inline wiring is connected to the LED layer through the fourth via hole.
However, Lee teaches a surface passivation layer ( Fig. 20: PAS1 ) and an inline wiring ( Fig. 20: RME1 ) disposed on the surface passivation layer ( Fig. 20 : PAS1 ); wherein the surface passivation layer ( Fig. 20: PAS1 ) covers a side wall of the TFT device layer ( Fig. 20: TFT; Col. 11 lines 37 – 38 The first passivation layer PAS1 may protect the thin-film transistors TFT ) and a side wall of the LED layer ( Fig. 20 display layer DPL ); and wherein the inline wiring ( Fig. 20: RME1 ) comprises a third inline wiring ( Fig. 20 RME1 in area CF1 ) and a fourth inline wiring ( Fig. 20: CF2 on 10-2 side ), parts of the surface passivation layer ( Fig. 20: PAS1 ) located on the fifth step portion ( Fig. 20 CNE2 in area CF1 ) and the sixth step portion ( Fig. 20 CNE2 in area CF2 of 10-2 ) are provided with a third via hole ( Col. 11 lines 38-40 The first passivation layer PAS1 may include contact holes that are penetrated by the first electrodes RME1 ) and a fourth via hole ( as discussed above ), respectively; and the third inline wiring ( Fig. 20: RME1 in area CF1 ) is connected to the LED layer ( Fig. 20: display layer DPL ) through the third via hole ( as shown in Fig. 20 ), and the fourth inline wiring ( Fig. 20: CF2 on 10-2 side ) is connected to the LED layer ( Fig. 20: DPL ) through the fourth via hole ( as shown in Fig. 20 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Jeong and Li (‘026) to implement a surface passivation layer and an inline wiring disposed on the surface passivation layer; wherein the surface passivation layer covers a side wall of the TFT device layer and a side wall of the LED layer; and wherein the inline wiring comprises a third inline wiring and a fourth inline wiring, parts of the surface passivation layer located on the fifth step portion and the sixth step portion are provided with a third via hole and a fourth via hole, respectively; and the third inline wiring is connected to the LED layer through the third via hole, and the fourth inline wiring is connected to the LED layer through the fourth via hole because sidewall passivation allows for leakage reduction and improved structural integrity and step coverage.
Claim 15: Jeong and Li (‘026) disclose the display panel of claim 14 ( as discussed above).
Neither Jeong nor Li (‘026) appear to disclose a surface passivation layer and an inline wiring located on the surface passivation layer; wherein the surface passivation layer covers a side wall of the TFT device layer and a side wall of the LED layer; and wherein the inline wiring comprises a third inline wiring and a fourth inline wiring, parts of the surface passivation layer located on the seventh step portion, the eighth step portion, the tenth step portion, and the eleventh step portion are provided with a fifth via hole, a sixth via hole, a seventh via hole, and an eighth via hole, respectively; and the third inline wiring is connected to the TFT device layer and the LED layer through the fifth via hole, the sixth via hole, and the seventh via hole, and the fourth inline wiring is connected to the TFT device layer and the LED layer through the eighth via hole.
However, Lee teaches a surface passivation layer ( Fig. 20: PAS1 ) and an inline wiring ( Fig. 20: CNE1 ) disposed on the surface passivation layer ( Fig. 20 : PAS1 ); wherein the surface passivation layer ( Fig. 20: PAS1 ) covers a side wall of the TFT device layer ( Fig. 20: TFT; Col. 11 lines 37 – 38 The first passivation layer PAS1 may protect the thin-film transistors TFT ) and a side wall of the LED layer ( Fig. 20 display layer DPL ); a and wherein the inline wiring ( Fig. 20: RME1 ) comprises a third inline wiring ( Fig. 20 CNE1 in area CF1 ) and a fourth inline wiring ( Fig. 20: CNE1 in CF2 on 10-2 side ), parts of the surface passivation layer ( Fig. 20: PAS1 ) located on the seventh step portion ( Fig. 20: right side of PAS1 that steps up to CWL2 ), the eighth step portion ( Fig. 20: left side of PAS1 that steps down from CWL2 ), the tenth step portion ( Fig. 20 left side of PAS1 that steps up to CNE2 ), and the eleventh step portion ( Fig. 20: right side of PAS1 that steps down from CNE1 ) are provided with a fifth via hole ( Col. 11 lines 38-40 The first passivation layer PAS1 may include contact holes that are penetrated by the first electrodes RME1 ), a sixth via hole ( as discussed above ), a seventh via hole ( as discussed above ), and an eighth via hole ( as discussed above ), respectively; and the third inline wiring ( Fig. 20: CNE1 in area CF1 ) is connected to the TFT device layer ( Fig. 20: TFT ) and the LED layer ( Fig. 20: DPL ) through the fifth via hole( Fig. 20: RME1 for CF1 in 10-2 ), the sixth via hole ( Fig. 20: RME1 for CF2 for CF2 in 10-2 ), and the seventh via hole ( as discussed above ), and the fourth inline wiring ( Fig. 20 CNE1 in area CF2 for 10-2 ) is connected to the TFT device layer ( Col. 11 lines 4-6 The second connecting electrodes CNE may electrically connect the drain electrodes DE of the thin-film transistors TFT to first electrodes RME1 ) and the LED layer ( Fig. 20: DPL ) through the eighth via hole ( as discussed above ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Jeong and Li (‘026) to implement a surface passivation layer and an inline wiring located on the surface passivation layer; wherein the surface passivation layer covers a side wall of the TFT device layer and a side wall of the LED layer; and wherein the inline wiring comprises a third inline wiring and a fourth inline wiring, parts of the surface passivation layer located on the seventh step portion, the eighth step portion, the tenth step portion, and the eleventh step portion are provided with a fifth via hole, a sixth via hole, a seventh via hole, and an eighth via hole, respectively; and the third inline wiring is connected to the TFT device layer and the LED layer through the fifth via hole, the sixth via hole, and the seventh via hole, and the fourth inline wiring is connected to the TFT device layer and the LED layer through the eighth via hole because this approach enhances optoelectronic performance, improves reliability, and enables reliable electrical connectivity to individual sub-pixels in high-density devices.
Claim 16: Jeong discloses the display panel of claim 1 ( as discussed above).
Jeong does not appear to disclose a reflective layer disposed between the third epitaxial layer and the TFT device layer; a buffer layer disposed between the reflective layer and the TFT device layer; a surface passivation layer covering a side wall of the TFT device layer and a side wall of the LED layer; an inline wiring disposed on the surface passivation layer; and a planarization layer disposed on the TFT device layer and covering the surface passivation layer and the inline wiring on the TFT device layer and the LED layer, wherein the metal wiring layer ( Fig. 20: RME1 ) is disposed on the planarization layer ( Fig. 20: OC1 ).
However, Li discloses a reflective layer ( Fig. 2B: Reflection Layer 214 ) disposed between the third epitaxial layer ( Fig. 2B #230 ) and the TFT device layer ( Fig. 2B: pixel driver ); a buffer layer ( Fig. 2B: 206 ) disposed between the reflective layer ( Fig. 2B #214 ) and the TFT device layer ( Fig. 2B: pixel driver);
Li does not appear to disclose a surface passivation layer covering a side wall of the TFT device layer and a side wall of the LED layer; an inline wiring disposed on the surface passivation layer; and a planarization layer disposed on the TFT device layer and covering the surface passivation layer and the inline wiring on the TFT device layer and the LED layer, wherein the metal wiring layer is disposed on the planarization layer.
However, Lee teaches a surface passivation layer ( Fig. 20: PAS1 ) covering a side wall of the TFT device layer ( Fig. 20: TFT; Col. 11 lines 37 – 38 The first passivation layer PAS1 may protect the thin-film transistors TFT ) and a side wall of the LED layer ( Fig. 20 display layer DPL ); an inline wiring ( Fig. 20: CNE1 ) disposed on the surface passivation layer ( Fig. 20: PAS1 ); and a planarization layer ( Fig. 20: OC1 ) disposed on the TFT device layer ( Fig. 20: TFT ) and covering the surface passivation layer ( Fig. 20: PSA1 ) and the inline wiring ( Fig. 20: CNE1 ) on the TFT device layer ( Fig. 20: TFT ) and the LED layer ( Fig. 20: DPL ), wherein the metal wiring layer ( Fig. 20: RME1 ) is disposed on the planarization layer ( Fig. 20: OC1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Jeong and Li (‘026) to implement a surface passivation layer covering a side wall of the TFT device layer and a side wall of the LED layer; an inline wiring disposed on the surface passivation layer; and a planarization layer disposed on the TFT device layer and covering the surface passivation layer and the inline wiring on the TFT device layer and the LED layer, wherein the metal wiring layer is disposed on the planarization layer because this approach is used to solve performance and integration challenges that arise when shrinking LEDs to microscopic scales.
Claim 17: Jeong, Li (‘026), and Lee disclose the display panel of claim 16 ( as discussed above).
Neither Jeong nor Lee appear to disclose a first bonding layer, a first filter layer, and a first transparent conductive layer are sequentially disposed between the first epitaxial layer and the second epitaxial layer; and a second bonding layer, a second filter layer, and a second transparent metal layer are sequentially disposed between the second epitaxial layer and the third epitaxial layer.
However, Li (‘026) teaches a first bonding layer ( Fig. 2B #216 ), a first filter layer ( Fig. 2B #214 ), and a first transparent conductive layer ( [0075] In some embodiments, conductive transparent layers are formed between the LED epitaxial layers to improve conductivity and transparency ) are sequentially disposed between the first epitaxial layer ( Fig. 2B #210 )and the second epitaxial layer ( Fig. 2B #220 ); and a second bonding layer ( Fig. 2B #226 ), a second filter layer ( Fig. 2B #224 ), and a second transparent metal layer ( [0075] In some embodiments, conductive transparent layers are formed between the LED epitaxial layers to improve conductivity and transparency ) are sequentially disposed between the second epitaxial layer ( Fig. 2B #220) and the third epitaxial layer ( Fig. 2B #230 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Li (‘026) with Jeong and Lee to implement a first bonding layer, a first filter layer, and a first transparent conductive layer are sequentially disposed between the first epitaxial layer and the second epitaxial layer; and a second bonding layer, a second filter layer, and a second transparent metal layer are sequentially disposed between the second epitaxial layer and the third epitaxial layer because this would enable high-resolution, full-color displays with independent pixel control and three-dimensional integration of red, green, and blue epitaxial layers.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817