DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 3, Figure 47, corresponding to claims 1-5 and 8-11, in the reply filed on 05/27/2026, is acknowledged.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 2 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the other side of the second insulator”. There is insufficient antecedent basis for this limitation. For the purpose of examination, the limitation of claim 1 will be interpreted as: “another side of the second insulator”.
Claim 2 recites the limitations: “on the one side of the first conductor and the first insulator” and “a surface on the one side of the second conductor in the first direction is in contact with a surface on the other of the third conductor in the first direction”. There is insufficient antecedent basis for these limitation. For the purpose of examination, the limitation of claim 2 will be interpreted as: The semiconductor memory device according to claim 1, further comprising: a third conductor provided on side of the third conductor in the first direction.
Claim Rejections - 35 USC § 112(a)
Claim 10 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 10 requires the first insulator, the second insulator, the third insulator, and the fourth insulator include a silicon oxide. The written specification describe the first insulator, element #34, the second insulator, element #82, the third insulator, element #81, as including silicon oxide (see paragraph [0070], [0126] and 0131]). However, the fourth insulator, element #40 includes a metal oxide, for example, aluminum oxide (paragraph [0230]). Furthermore, no other parts of the specification appear to teach or suggests that the fourth insulator includes a silicon oxide. Therefore, a person skilled in the art, at the time the application was filed, would have not recognized that the inventor was in possession of the invention as claimed, in view of the disclosure of the application as filed. For the purpose of examination claim 10 will be interpreted as: The semiconductor memory device according to claim 4, wherein the first insulator, the second insulator, the third insulator, and the fourth insulator include an
Claim Rejections - 35 USC § 102(b)
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 8 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cui et al., (United States Patent Number, US 11,114,462 B1), hereinafter referenced as Cui.
Regarding claim 1, Cui teaches a semiconductor memory device, comprising: a first conductor (Fig.10C, element #46B) and a first insulator (Fig.10C, first element #32 located right below element #46B) arranged in a first direction (Fig.10C, they are arranged in the vertical direction); a second conductor extending in the first direction so as to penetrate the first conductor and the first insulator (Fig.10C, element #602, column 17, rows 40-48 conducts electricity); a memory pillar extending in the first direction so as to penetrate the first conductor and the first insulator (Fig.11A shows memory pillars on the right side of the figure, extending vertically) and including a semiconductor (Fig.11A, memory pillars include element #601); a second insulator provided between the first conductor and the second conductor (Fig.10C, element #53, the first on the left side of element #46B); and a third insulator including a first portion provided between the second insulator and the first conductor (Fig.10C, element #52 has a vertical portion between element #46B and element #53 adjacent to it), a portion provided on a surface on one side of the second insulator in the first direction (Fig.10C, element #52 has a horizontal portion on the bottom side of element #53), and a portion provided on a surface on another side of the second insulator in the first direction (Fig.10C, element #52 has a horizontal portion on the top side of element #53), wherein the third insulator offers an etching rate smaller than an etching rate of the second insulator (Fig.5F and 5G,column 52, rows 10-20).
Regarding claim 2, Cui teaches the semiconductor memory device of claim 1 as set forth in the anticipation rejection. Cui further teaches the semiconductor memory device according to claim 1, further comprising: a third conductor provided onon side of the third conductor in the first direction (Fig.10C, bottom side of element #602 is in contact with the top side of element #11).
Regarding claim 3, Cui teaches the semiconductor memory device of claim 1 as set forth in the anticipation rejection. Cui further teaches the semiconductor memory device according to claim 1, wherein the third insulator (Fig.10C, element #52) further includes a second portion provided between the first insulator and the second conductor (Fig.10C, vertical portion on the left side of the first insulator element #32, located below element #46B, and at the same height as element #32), and a distance between the first portion and the second conductor in a direction intersecting the first direction is greater than a distance between the second portion and the second conductor in the direction intersecting the first direction (Fig.10C, the distance between the first portion and the second conductor in the horizontal direction is equal to the sum of the width of elements #53, #54, #56 and #601 in the horizontal direction, the distance between the second portion and the second conductor in the horizontal direction is equal to the sum of the width of elements #54, #56 and #601 in the horizontal direction).
Regarding claim 4, Cui teaches the semiconductor memory device of claim 1 as set forth in the anticipation rejection. Cui further teaches the semiconductor memory device according to claim 1, further comprising: a fourth insulator extending in the first direction so as to penetrate the first conductor and the first insulator (Fig.10C, element #44), wherein the third insulator further includes a third portion provided between the fourth insulator and the second conductor so as to be in contact with the fourth insulator (Fig.10C, horizontal portion of element #52, right above element #46B is located between element #44 and element #602), and a portion provided between the second insulator and the fourth insulator (Fig.10C, vertical portion of element #52, at the same height as element #46B is located between element #53 and element #44), and a distance between the first portion and the second conductor in a direction intersecting the first direction is greater than a distance between the third portion and the second conductor in the direction intersecting the first direction (Fig.10C, the distance between the first portion and the second conductor in the horizontal direction is equal to the sum of the width of elements #53, #54, #56 and #601 in the horizontal direction, the distance between the third portion and the second conductor in the horizontal direction is equal to the sum of the width of elements #54, #56 and #601 in the horizontal direction).
Regarding claim 5, Cui teaches the semiconductor memory device of claims 1 and 3 as set forth in the anticipation rejection. Cui further teaches the semiconductor memory device according to claim 3, wherein a surface at which the second portion faces the second conductor is located on an extension of a surface at which the second insulator faces the second conductor (Fig.5G, the left surface of element #53 and #52 on the right side of the figure, are coplanar).
Regarding claim 8, Cui teaches the semiconductor memory device of claims 1 and 4 as set forth in the anticipation rejection. Cui further teaches the semiconductor memory device according to claim 4, wherein the second insulator is not provided between the third portion and the second conductor (Fig.10C, element #53 is not provided between the third portion as defined above, in the rejection of claim 4, and element #602).
Regarding claim 9, Cui teaches the semiconductor memory device of claims 1, 4 and 8 as set forth in the anticipation rejection. Cui further teaches the semiconductor memory device according to claim 8, wherein the second insulator is not provided in a second layer including the first insulator (fig.10C, element #53 is not provided in layers that include element #32).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Cui in view of Sun et al., (United States Patent Publication Application Number, US 2021/0391354 A1) hereinafter referenced as Sun, in view of Lee et al., (Thermal Atomic Layer Etching of Al2O3, HfO2, and ZrO2 Using Sequential Hydrogen Fluoride and Dimethylaluminum Chloride Exposures, Journal of Physical Chemistry, C, 2019, 123, 18455-18466), hereinafter referenced as Lee.
Regarding claim 10, Cui teaches the semiconductor memory device of claim 1 as set forth in the anticipation rejection. Cui further teaches the semiconductor memory device according to claim 4, wherein the first insulator, the second insulator, the third insulator, and the fourth insulator include an insulator includes an oxide (element #122 has the same role as element #53 of Cui and includes an HfO2 paragraph [0039], rows 10-14). Furthermore, Lee teaches HfO2 has a higher etch rate than Al2O3 (Table 1) which is the material of the third insulator layer of Cui (element #52, column 13, row 51), thus satisfying the limitation of claim 1. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to choose the second insulator to include an oxide from of the list of materials disclosed by Sun. Both materials, aluminum nitride and hafnium oxide (both listed by Sun) are used for the same purpose, to provide a charge storage layer, and can be implemented with a reasonable chance of success.
Regarding claim 11, Cui teaches the semiconductor memory device of claim 1 as set forth in the anticipation rejection. Cui further teaches the second insulator is aluminum nitride (element #53 column 15, rows 42-43) and the third insulator is aluminum oxide (third insulator, element #52, column 13, row 51) and wherein the third insulator offers an etching rate smaller than an etching rate of the second insulator (Fig.5F and 5G, column 52, rows 10-20). Cui does not teach the semiconductor memory device according to claim 1, wherein the etching rate is an etching rate for hydrogen fluoride. As noted in the obviousness rejection of claim 10, Sun teaches the second insulator can be replaced with HfO2 (element #122 has the same role as element #53 of Cui and includes an HfO2 paragraph [0039], rows 10-14) and Lee teaches HfO2 has a higher etch rate than Al2O3 (Table 1), which is the material of the third insulator layer of Cui (element #52, column 13, row 51), when hydrogen fluoride is used for etching. Therefore, the combination of Cui Sun and Lee teaches the etching rate is an etching rate for hydrogen fluoride. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Sun and Lee and disclose the etching rate is an etching rate for hydrogen fluoride. As disclosed by Lee, hydrogen fluoride can be used for self-limiting etch reactions, which prevent damage produced by other type of etches such as ion or atom bombardment.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRISTIAN A TIVARUS whose telephone number is (703)756-4688. The examiner can normally be reached Monday- Friday 8:00 AM -5:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights