Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 7-10 are rejected under 35 U.S.C. 102(a)(1) as being fully anticipated by Kim 20100009273
Kim 20100009273 in the background second describes figure 2A, a photomask for a semiconductor device having a main pattern (A) with dummy patterns surrounding it (above, below, areas B and C) to reduce flare noise including a spacing of H between A and dummy areas B and C [0005-0006]. Figure 4A is similar, but adds a fine dummy patterns (d1 and d2) which is formed in the spaces between the main pattern and the dummy pattern regions B and C which have a size below the resolution limit of the exposure. The fine dummy pattern may have square, rectangular or circular cross sections [0024-0029]. In figure 5A, the fine dummy pattern is a series of lines [0030-0031]. The exposure used to form the mask covers a metal bilayer with a resist, which is then exposed with the main pattern (A), the first dummy pattern (B), the second dummy pattern (C ) and the fine dummy patterns (d1,d2). The resist is then developed, used to mask the etching of the metal bilayer and then the resist is stripped. [0032- 0037]. The use of masks in the exposure of resist during the manufacture of semiconductor devices is disclosed [0002-0003].
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The area occupied by the larger dummy patterns which includes B and C is greater than that occupied by the finer dummy patterns (d1,d2), which are later formed as the space (H) between A and B (or C) must be refined for their placement.
Claims 1 and 7-10 are rejected under 35 U.S.C. 102(a)(1) as being fully anticipated by Jeong et al. 20070059610.
Jeong et al. 20070059610 in figure 3 illustrates a dummy dot pattern (60/61) which may be circular or rectangular and arranged in an array. This is overlayed with the layout of the design pattern (51) for the photomask to determine which dummy patterns need to be removed
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Other dummy regions (65) are then identified and additional dummy features (71,72/91) are added as illustrated in figures 7 and/or 9.
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The dummy pattern (91) can be the same size, shapes and spacing of those of the first dummy pattern (61) or other dummy dot/pattern rules may be used [0042-0065, particularly 0061-0065]. Trenches may be formed in the upper interlayer dielectric 85. In particular, the third layout 50'' of FIG. 7 may be used to form a photomask. The photomask may be used to form a photoresist pattern on the substrate 81 having the upper interlayer dielectric 85. The upper interlayer dielectric 85 may be anisotropic ally etched using the photoresist pattern as an etch mask. Consequently, trenches may be formed in the upper interlayer dielectric 85 [0076].
The original dummy area is the entire surface, which is modified to provide the original dummy pattern (61) only where it does not conflict with the design/circuit pattern and then smaller areas (65) are defined for the later placement of the dummy features (71,72,91), which are different and/or shifted form the dummy patterns in the original array.
Claims 1 and 7-10 are rejected under 35 U.S.C. 102(a)(1) as being fully anticipated by Lee et al. 20080282218.
Lee et al. 20080282218 teaches with respect to figure 1c, an array of dummy patterns (122,132), which are then overlaid with the main pattern (300/310) in the layout to determine where the dummy patterns (150a) have to be removed [0019-0035].
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Figurers 2E to 3A shows a similar process [0042-0069].
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The original dummy area is the entire surface, which is modified to provide the original dummy pattern (150) only where it does not conflict with the design/circuit pattern and then smaller areas are defined for the later placement of the dummy features (230), which are different and/or shifted form the dummy patterns in the original array.
Claims 1,7-10 are rejected under 35 U.S.C. 102(a)(1) as being fully anticipated by Kuroda et al. 20020061608.
Kuroda et al. 20020061608 in the flow chart of figure 5 describes a process which includes a process for determining prohibition of the placement of first dummy pattern and second dummy patterns due to the main/desired pattern, placing the first dummy patterns in the dummy regions. Searching for prohibited placement of the second dummy pattern, placing the second dummy pattern [0067-0071]. Increase of mask data can be controlled when the first dummy patterns DP.sub.1 occupy the relatively wide region among the dummy region FA (abstract)
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In figure 23, there are three dummy patterns uses the process of figure 5, extended to accommodate a third dummy pattern. The third dummy pattern (DP3, rectangular) is formed firs over a large area, then the first dummy pattern (PD1, squares at bottom) and then the second dump pattern (DP2, smaller, dark squares), which allows the degree of freedom in the placement of the dummy pattern is increased and the effects of increased mask data can be controlled by providing the third dummy patterns DP3 over a relatively large area. [0104-0114].
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The original dummy area is the entire surface, which is modified to provide the original dummy pattern (DP3) only where it does not conflict with the design/circuit pattern and then smaller areas are defined for the later placement of the dummy features (DP1 and DP2), which are different and/or shifted form the dummy patterns in the original array.
Claims 1-6, 9,11-16 and 18 are rejected under 35 U.S.C. 102(a)(1) as being fully anticipated by Tsutsumi JP 2002110809.
Tsutsumi JP 2002110809 (machine translation attached) teaches with respect to figure 2, the drawing area with circuit patterns (6), where the pattern area not occupied by the enlarged circuit pattern is first divided into four areas (7) as illustrated in figure 2A. The areas (7) which conflict/include circuit patterns are further divided into four sub-areas (8) as illustrated in figure 2B. The sub-areas (8) which include/conflict with the circuit pattern are then divided into four parts (9) (2C and 3A). This is repeated until a minimum sized (open) area is reached. The dummy patterns are then formed on the mask. It is created as shown in FIG. Then, as shown in FIG. 4 (b), using this mask, a mask pattern is projected onto the semiconductor substrate 1 and photolithography and etching techniques are used to form a trench 4 in which a dummy pattern 5 is provided on the semiconductor substrate 1. To form Normally, when forming a trench in the semiconductor substrate 1, a silicon nitride film serving as a CMP polishing stopper is formed in advance, and then an insulating film is embedded after pattern formation. Next, after polishing and flattening by CMP, the silicon nitride film serving as a stopper is removed to form a trench isolation. FIG. 4B is a cross-sectional view after removing the nitride film. Therefore, the element isolation insulating film 2 can be satisfactorily buried in the trench 4 using the CMP method, and the element isolation insulating film 2 after the burying can be formed flat. A semiconductor device can be manufactured [0025-0031]. To provide a design method of a dummy pattern for forming the dummy pattern faster in a limited memory area in a computer and for improving productivity even if the dummy pattern is scaled down. SOLUTION: A first division area 7 is formed when a drawing area 20 is divided into four areas. Then, a division process and a comparison process for comparing the divided area and an expansion circuit pattern are repeated until a minimum zone set beforehand is generated. Then, only a third division area 9 overlapped with the expansion circuit pattern 6 is removed from the dummy pattern formation area. A dummy pattern 5 is provided to the first, second, and third division areas remained without removing (abstract). A mask using this pattern layout is created, and a trench provided with a dummy pattern is formed on the semiconductor substrate using the mask by photolithography and etching techniques. Therefore, a good embedding can be performed inside the trench by using the CMP method, and a good semiconductor device having an element isolation structure by the STI method can be manufactured [0045].
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Tsutsumi JP 2002110809 meets the recited limitation of the body of the claims, where each field (7) is ¼ of the size of layout, the sub-field (8) is ¼ the size of the field (7) and the smaller sub-field (9) is ¼ the size of the sub-field (8), 1/16 of the size of field (7) and 1/64 the size of the layout. The steps recited do not recite the formation of a photomask ands have been read to embrace the formation of a layout design suitable for forming a photomask.
Claims 1-6, 9,11-16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over
Tsutsumi JP 2002110809.
Tsutsumi JP 2002110809 does not exemplify the formation of a photomask using the disclosed process.
It would have been obvious to modify the process of Tsutsumi JP 2002110809 which results in a circuit layout by using this layout formation process which reduces the amount of memory required to facilitate the placement of the dummy features to form a photomask as discussed at [0045] so that multiple devices can be formed by repeatedly using the photomask.
Claims 1-16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over
Tsutsumi JP 2002110809, in view of Jeong et al. 20070059610.
Tsutsumi JP 2002110809 does not describe the shifting of the positions of the dummy patterns to avoid conflict with the circuit pattern.
It would have been obvious to modify the process of forming the masks taught by Tsutsumi JP 2002110809 by shifting the positions where dummy features can be formed as taught by Jeong et al. 20070059610 to accommodate a wider variety of desired circuit patterns with a reasonable expectation of forming a useful photomask.
Claims 1-6, 9,11-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tsutsumi JP 2002110809, in view of Mori JP H09135004.
Mori JP H09135004 (machine translation attached) teaches the use of electron beam direct write or photomask exposure processes to form DRAM memory chips [0015]. Figure 1 illustrates the top view of the devices which includes bit lines (4), word lines (2a) and dummy word lines (2b) [0026]. DESCRIPTION OF SYMBOLS 1 Element active area 2a Word line 2b Dummy word line 3 Opening part connecting bit line and element active area 4 Bit line 5 Opening part connecting node electrode and element active area 6 Cell transistor 7 Cell capacitor 8 Sense amplifier Reference Signs List 9 P .sup.- type semiconductor substrate 10 Field oxide film 11 Gate oxide film 12 First interlayer insulating film 13 First buried conductive layer 14 Second interlayer insulating film 16 Capacitive insulating film 17 Plate electrode 18 Memory cell region 19 Dead region 20 Bit line turn-back part 21 Corner part 22 Partial batch exposure part 23 Variable shaping exposure part (page 5). Figure 2 illustrates the connection of these in a circuit including a capacitor (8)
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Tsutsumi JP 2002110809 does not describe the formation of memory devices having word lines. bit lines and capacitors
It would have been obvious to modify the processes exemplified or rendered obvious by the teachings of Tsutsumi JP 2002110809 to apply the processes to the formation of other semiconductor devices, such as the DRAM devices of Mori JP H09135004 which include dummy features to glean the benefit of the reduction in the memory/computational requirements for the placement of the dummy features described in Tsutsumi JP 2002110809
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Tsutsumi JP 2002110809, in view of Lee et al. 20130009250
Lee et al. 20130009250 teaches that dummy patterns 520 may be formed at the two ends of the CMOS transistors (including PMOS transistor 432a and the NMOS transistor 432b) in a direction of the device width W of the PMOS transistors. The dummy patterns 520 may be a sacrificial layer that may prevent or reduce erosion portions from forming on the metal gate electrodes 430a and 430b of the transistors 432a and 432b near the center of the array of CMOS transistors 506. In an embodiment, the dummy patterns 520 may comprise polysilicon or metal. The dummy patterns 520 may have a top leveled with a top of the CMOS transistors 506. The dummy patterns 520 may be extended and have a length which is substantially equal to the length of the diffusion area 502 and/or the length of the dummy diffusion area 510 along the first direction. In an embodiment, the dummy patterns 520 may be formed simultaneously with the dummy diffusion areas 510. Thus, no extra photomasks are needed for forming the dummy patterns 420.
Tsutsumi JP 2002110809 does not describe the formation of transistors with gate electrodes
It would have been obvious to modify the processes exemplified or rendered obvious by the teachings of Tsutsumi JP 2002110809 to apply the processes to the formation of other semiconductor devices, such as the transistor devices of Lee et al. 20130009250 which include dummy features to glean the benefit of the reduction in the memory/computational requirements for the placement of the dummy features described in Tsutsumi JP 2002110809
Claims 1-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tsutsumi JP 2002110809, in view of Mori JP H09135004, further in view of Jeong et al. 20070059610.
The combination of Tsutsumi JP 2002110809 and Mori JP H09135004 does not describe the formation of memory devices having word lines. bit lines and capacitors
It would have been obvious to modify the processes exemplified or rendered obvious by the teachings of Tsutsumi JP 2002110809 and Mori JP H09135004 by shifting the positions where dummy features can be formed as taught by Jeong et al. 20070059610 to accommodate a wider variety of desired circuit patterns with a reasonable expectation of forming a useful photomask.
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Tsutsumi JP 2002110809, in view of Lee et al. 20130009250
The combination of Tsutsumi JP 2002110809 and Lee et al. 20130009250 does not describe the formation of transistors with gate electrodes
It would have been obvious to modify the processes exemplified or rendered obvious by the teachings of Tsutsumi JP 2002110809 and Lee et al. 20130009250 by shifting the positions where dummy features can be formed as taught by Jeong et al. 20070059610 to accommodate a wider variety of desired circuit patterns with a reasonable expectation of forming a useful photomask.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tsai et al. 20120295187 illustrates in figure 1, the formation of a layout pattern for a device which includes inserting a first dummy pattern (120), inserting a second dummy pattern (130) having the same density as the first dummy pattern, inserting a dummy pattern with a second density, dividing the layout into sub-regions, adjusting the sizes of the third dummy patterns (140) in these sub-regions to match the second density and writing the layout pattern including the first, second and (modified/resized) third dummy patterns onto a photomask.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to Martin J Angebranndt whose telephone number is (571)272-1378. The examiner can normally be reached 7-3:30 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ching-Yu (Coris) Fung can be reached at 571-270-5713. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARTIN J. ANGEBRANNDT
Primary Examiner
Art Unit 1737
/MARTIN J ANGEBRANNDT/Primary Examiner, Art Unit 1737 July 22, 2026
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