DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Foreign priority is not claimed for this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/01/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 10 is objected to because of the following informalities:
“to fourth size of the fourth transistor” should read “to THE fourth size of the fourth transistor.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 13, it’s not clear how the base-emitter voltages of the BJTs are different. Base-emitter voltage is based on the type of semiconductor (For example, the BE voltage of silicon is 0.7V), so it’s not clear how the BE voltages are different here. Due to this, proper examination is not possible. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 14-16 and 18-19 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by “An Automotive Low-Power EMC Robust Brokaw Bandgap Voltage Reference” by Krolak et al.
Regarding claim 14, Krolak teaches a voltage reference circuit (Fig. 4, 17), comprising:
a bandgap core circuit that includes a plurality of bipolar devices (Q1, Q2, Q3), wherein the bandgap core circuit is configured to:
provide a first voltage level to a first circuit node (NB) using a reference voltage (Vref); and
provide a second voltage level to a second circuit node (NA) using the reference voltage (Vref); and
an amplifier circuit (Fig. 4 “A”, Fig. 9) that includes a first input terminal coupled to the first circuit node (INP) and a second input terminal coupled to the second circuit node (INN), wherein a first input impedance of the first input terminal is different from a second input impedance of the second input terminal (Process variations can account for different input impedances in the transistors. Fig. 4, and 17 also show different resistor and capacitor values connected to the positive and negative inputs of the differential amplifier and this difference in values means different impedances for the two input transistors), and wherein the amplifier circuit is configured to generate the reference voltage (Vref, OUT) using the first voltage level of the first circuit node (NA) and the second voltage level of the second circuit node (NB).
Regarding claim 15, Krolak teaches the voltage reference circuit of claim 14, wherein the amplifier circuit includes:
a first transistor (fig. 9 M3) with a first control terminal coupled to the first input terminal (INP); and
a second transistor (M4) with a second control terminal coupled to the second input terminal (INN), wherein a first size of the first transistor is different from a second size of the second transistor (Process variations account for the different impedances and transistor sizes of the input transistors).
Regarding claim 16, Krolak teaches the voltage reference circuit of claim 15, wherein to generate the reference voltage, the amplifier circuit (Fig. 9) is further configured to:
generate, using the first transistor (M3) and the first voltage level of the first circuit node, a first amplified signal (output of M3); and
generate, using the second transistor (M4) and the second voltage level of the second circuit node, a second amplified signal (output of M4).
Regarding claim 18, Krolak teaches the voltage reference circuit of claim 14, wherein a first collector terminal of a first bipolar device (Fig. 4, 17 Q2) of the plurality of bipolar devices is coupled to the first circuit node (connected to the + input terminal of amplifier A), wherein a second collector terminal of a second bipolar device (Q1) of the plurality of bipolar devices is coupled to the second circuit node (connected to – input terminal of amplifier A), wherein a first base terminal of the first bipolar device and a second base terminal of the second bipolar device are coupled to the reference voltage (Vss through R3 and R4), and wherein a first emitter area of the first bipolar device is different from a second emitter area of the second bipolar device (Q1 has an area of 2AE and Q2 has an area of AE).
Regarding claim 19, Krolak teaches the voltage reference circuit of claim 18, wherein the bandgap core circuit includes:
a first resistor network (Fig. 4, 17 R2) configured to couple the first circuit node (+ input) to a power supply node (Vdd); and
a second resistor network (R1) configured to couple the second circuit node (- input)to the power supply node (Vdd).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over “An Automotive Low-Power EMC Robust Brokaw Bandgap Voltage Reference” by Krolak et al. as applied to claims 14-16 and 18-19 above.
Regarding claim 17, Krolak teaches the voltage reference circuit of claim 16, wherein the amplifier circuit (Fig. 9) further includes a current-mirror circuit that includes a third transistor (M5) and a fourth transistor (M6), wherein the current-mirror circuit is configured to generate the reference voltage (OOUT) using the first amplified signal (output of M3) and the second amplified signal (output of M4), and wherein a first ratio of the first size of the first transistor to the second size of the second transistor is the same as a second ratio of a third size of the third transistor to a fourth size of the fourth transistor (Different transistor sizes are very well known in the art, as shown in par. 44 of US 20250286524 by Kawahara et al. and the ratio of the sizes can be adjusted based on circuit needs).
Claim(s) 1-2, 5-8, and 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over “An Automotive Low-Power EMC Robust Brokaw Bandgap Voltage Reference” by Krolak et al.
Regarding claim 1, Krolak teaches an apparatus, comprising:
an input-stage circuit (Fig. 9) that includes a first terminal (INP) with a first input impedance and a second terminal (INN) with a second input impedance different than the first input impedance (Process variations can account for different input impedances in the transistors. Fig. 4, and 17 also show different resistor and capacitor values connected to the positive and negative inputs of the differential amplifier and this difference in values means different impedances for the two input transistors), where the input-stage circuit is configured to:
receive a first input signal via the first input terminal (INP);
receive a second input signal via the second input terminal (INN); and
generate a first amplified signal and a second amplified signal using the first input signal and the second input signal (transistors M3 and M4 amplify the input signals and pass on the amplified signals to the next stage), respectively; and
an output-stage circuit (see annotated figure) configured to asymmetrically combine the first amplified signal and the second amplified signal to generate an output signal (OUT).
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Krolak is silent on the asymmetrical combination at the output stage. However, different impedances and asymmetrical signal combination can be a result of different transistor sizes, which is well known in the art as shown in par. 44 of US 20250286524 by Kawahara et al. and can be used to offset the asymmetry that is present in the input transistors due to process variations and/or other factors.
Regarding claim 2, Krolak teaches the apparatus of claim 1, wherein the input-stage circuit (Fig. 9) includes:
a first transistor (M3) with a first control terminal coupled to the first input terminal (INP); and
a second transistor (M4) with a second control terminal coupled to the second input terminal (INN), wherein a first size of the first transistor is different than a second size of the second transistor (Process variations account for the different impedances and transistor sizes of the input transistors).
Regarding claim 5, Krolak teaches the apparatus of claim 2, wherein the output-stage circuit includes a current-mirror circuit that includes a third transistor (M5) and a fourth transistor (M6).
Krolak is silent on asymmetrically combining the first amplified signal and the second amplified signal, the output-stage circuit is further configured to generate, using the current-mirror circuit, a first current and a second current whose values are based on respective sizes of the third transistor and the fourth transistor.
However, different transistor sizes are very well known in the art, as shown in par. 44 of US 20250286524 by Kawahara et al.
Regarding claim 6, Krolak teaches the apparatus of claim 5, wherein the output-stage circuit further includes a bias circuit configured to bias the current-mirror circuit using a bias signal (Fig. 9 transistors MB, MC, MD, and ME make up the bias circuit).
Regarding claim 7, Krolak teaches a method comprising:
receiving, by a first input terminal of an amplifier circuit, a first input signal (Fig. 9 INP);
receiving, by a second input terminal of the amplifier circuit, a second input signal (INN), wherein a first input impedance of the first input terminal is different from a second input impedance of the second input terminal (Process variations can account for different input impedances in the transistors. Fig. 4, and 17 also show different resistor and capacitor values connected to the positive and negative inputs of the differential amplifier and this difference in values means different impedances for the two input transistors);
generating, by the amplifier circuit, a first amplified signal and a second amplified signal using the first input signal and the second input signal (transistors M3 and M4 amplify the input signals and pass on the amplified signals to the next stage); and
asymmetrically combining, by the amplifier circuit, the first amplified signal and the second amplified signal to generate an output signal (OUT).
Krolak is silent on the asymmetrical combination at the output stage. However, different impedances and asymmetrical signal combination can be a result of different transistor sizes, which is well known in the art as shown in par. 44 of US 20250286524 by Kawahara et al. and can be used to offset the asymmetry that is present in the input transistors due to process variations and/or other factors.
Regarding claim 8, Krolak teaches the method of claim 7, wherein the amplifier circuit includes an input-stage circuit and an output-stage circuit (see annotated figure), and wherein generating the first amplified signal and the second amplified signal includes:
generating, using a first transistor (M3) included in the input-stage circuit, the first amplified signal using the first input signal (INP); and
generating, using a second transistor (M4) included in the input-stage circuit, the second amplified signal using the second input signal (INN), wherein a first size of the first transistor is different from a second size of the second transistor (Process variations account for the different impedances and transistor sizes of the input transistors).
Regarding claim 11, Krolak teaches the method of claim 7, further comprising:
generating, by a core circuit, the first input signal (Fig. 4, 17 input to differential amplifier A) using the output signal (output of differential amplifier A, wherein the core circuit includes a plurality of bipolar devices (Q1-Q3); and
generating, by the core circuit, the second input signal using the output signal (input to differential amplifier A).
Regarding claim 12, Krolak teaches the method of claim 11, wherein generating the first input signal includes sinking, by a first bipolar device (Fig. 4, 17 Q2) using the output signal, a first current (Ic2) from a first circuit node coupled to the first input terminal of the amplifier circuit (+ input terminal of amplifier A), and wherein generating the second input signal includes sinking, by a second bipolar device (Q1) using the output signal, a second current (Ic1) from a second circuit node coupled to the second input terminal of the amplifier circuit (- input terminal of amplifier A), wherein a first emitter area of the first bipolar device is different than a second emitter area of the second bipolar device (Q1 has an area of 2AE and Q2 has an area of AE).
Allowable Subject Matter
Claims 3-4 and 9-10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art fails to teach a third and fourth transistor included in the input stage coupled between the input transistors and the output stage.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20260118400 by Frolov et al. teaches a circuit with different impedance levels based on transistor size.
US 5355333 by Pascucci teaches a sense amplifier with a pair of asymmetric transistors that are different sizes.
US 20250337379 by Karanjkar et al. teaches a PGA circuit with different transistor sizes that affect impedance.
US 20250219586 by Kato teaches a Doherty amplifier system with the larger size transistors having lower gate impedance.
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/NAREH SHAMIRYAN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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