DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 1, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on March 18, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 7, 10, 12, 13, 16, 18, 21, 23, 25, 28, 30, 31, and 33 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Farooq et al (US Pub 2021/0175084).
In re claim 1, Farooq et al discloses (i.e. see at least Figures 13A, 13B) a device comprising: a die comprising: a plurality of pillar bumps configured to electrically connect the die to a substrate, the plurality of pillar bumps including: at least one first pillar bump having a first total pillar bump height, the at least one first pillar bump comprising: a first pillar (i.e. 1104A/1104B) having a first pillar height (i.e. H3, see Figure 11B); and a first solder cap (i.e. 1204A/1204B) having a first solder cap height; and at least one second pillar bump having a second pillar height substantially equal to the first total pillar bump height (i.e. see at least Figures 12A, 12B, 13A, 13B: showing both bumps have the same height), the at least one second pillar bump comprising: a second pillar (i.e. 1106A/1106B) having a second pillar height (i.e. H4, see Figure 11B), wherein the second pillar height is greater than the first pillar height (i.e. H4 > H3; see at least paragraphs 0069 and 0070); and a second solder cap (i.e. 1206A/1206B) having a second solder cap height, wherein the second solder cap height is less than the first solder cap height (i.e. see at least Figures 12 and 13).
In re claim 2, Farooq et al wherein at least one pillar bump of the plurality of pillar bumps comprises a barrier layer (i.e. 1201A/1201B) between a pillar of the at least one pillar bump and a solder cap of the at least one pillar bump.
In re claim 5, Farooq et al discloses wherein the plurality of pillar bumps comprises a plurality of first pillar bumps and a plurality of second pillar bumps (i.e. see at least Figures 6 and 7).
In re claim 7, Farooq et al discloses wherein the plurality of first pillar bumps are disposed at first locations and the plurality of second pillar bumps are disposed at second locations (i.e. finer C4 connections are provided in regions of tighter pitch, see at least paragraph 0032), and wherein the first locations are associated with higher chip-package interaction (CPI) stresses than the second locations (i.e. it is implicit/inherent that CPI stress is higher in these regions).
In re claim 10, Farooq et al discloses wherein the at least one first pillar bump has a first characteristic dimension along a direction orthogonal to the first pillar height and the at least one second pillar bump has a second characteristic dimension along the direction, and wherein the first characteristic dimension is greater than the second characteristic dimension (i.e. see at least Figures 11-13).
In re claim 12, Farooq et al discloses an integrated device comprising: a substrate (i.e. 1504) comprising a plurality of contacts (i.e. 1506); a die comprising integrated circuitry electrically connected to the plurality of contacts via a plurality of pillar bumps (i.e. see at least Figure 15), the plurality of pillar bumps comprising: at least one first pillar bump including: a first pillar (i.e. 1104A/1104B) having a first pillar height (i.e. H3, see Figure 11B); and a first solder cap (i.e. 1204A/1204B) having a first solder cap height; and at least one second pillar bump including: a second pillar (i.e. 1106A/1106B) having a second pillar height (i.e. H4, see Figure 11B), wherein the second pillar height is greater than the first pillar height (i.e. H4 > H3, see at least paragraphs 0069 and 0070); and a second solder cap (i.e. 1206A/1206B) having a second solder cap height, wherein the second solder cap height is less than the first solder cap height (i.e. see at least Figures 12 and 13).
In re claim 13, Farooq et al wherein at least one pillar bump of the plurality of pillar bumps comprises a barrier layer (i.e. 1201A/1201B) between a pillar of the at least one pillar bump and a solder cap of the at least one pillar bump.
In re claim 16, Farooq et al discloses wherein the plurality of pillar bumps comprises a plurality of first pillar bumps and a plurality of second pillar bumps (i.e. see at least Figures 6 and 7).
In re claim 18, Farooq et al discloses wherein the plurality of first pillar bumps are disposed at first locations and the plurality of second pillar bumps are disposed at second locations (i.e. finer C4 connections are provided in regions of tighter pitch, see at least paragraph 0032), and wherein the first locations are associated with higher chip-package interaction (CPI) stresses than the second locations (i.e. it is implicit/inherent that CPI stress is higher in these regions).
In re claim 21, Farooq et al discloses wherein the at least one first pillar bump has a first characteristic dimension along a direction orthogonal to the first pillar height and the at least one second pillar bump has a second characteristic dimension along the direction, and wherein the first characteristic dimension is greater than the second characteristic dimension (i.e. see at least Figures 11-13).
In re claim 23, Farooq et al discloses a method for fabricating an integrated device, the method comprising: electrically connecting at least one first pillar bump of a die to a first contact (i.e. 1506) of a substrate (i.e. 1504), wherein the first pillar bump includes a first pillar (i.e. 1104A/1104B) having a first pillar height (i.e. H3, see Figure 11B) and a first solder cap (i.e. 1204A/1204B) having a first solder cap height; and electrically connecting at least one second pillar bump of the die to a second contact (i.e. 1506) of the substrate (i.e. 1054), wherein the second pillar bump includes a second pillar (i.e. 1106A/1106B) having a second pillar height and a second solder cap (i.e. 1206A/1206B) having a second solder cap height (i.e. H4, see Figure 11B), and wherein the second pillar height is greater than the first pillar height (i.e. H4 > H3, see at least paragraphs 0069 and 0070) and the second solder cap height is less than the first solder cap height (i.e. see at least Figures 12 and 13).
In re claim 25, Farooq et al discloses wherein electrically connecting the at least one first pillar bump of the die to the first contact of the substrate includes electrically connecting a plurality of first pillar bumps to a respective plurality of first contacts of the substrate, wherein electrically connecting the at least one second pillar bump of the die to the second contact of the substrate includes electrically connecting a plurality of second pillar bumps to a respective plurality of second contacts of the substrate (i.e. see at least Figure 15), and wherein the first contacts are at locations associated with higher chip-package interaction (CPI) stresses than the second contacts (i.e. finer C4 connections are provided in regions of tighter pitch, see at least paragraph 0032; it is implicit/inherent that CPI stress is higher in these regions).
In re claim 28, Farooq et al discloses wherein the at least one first pillar bump has a first characteristic dimension along a direction orthogonal to the first pillar height and the at least one second pillar bump has a second characteristic dimension along the direction, and wherein the first characteristic dimension is greater than the second characteristic dimension (i.e. see at least Figures 11-13).
In re claim 30, Farooq et al discloses a method for fabricating an integrated device, the method comprising: forming, on a first contact of a die, a first pillar (i.e. 1104A/1104B) having a first pillar height (i.e. H3, see Figure 11B); forming, on the first pillar, a first solder cap (i.e. 1204A/1204B) having a first solder cap height; forming, on a second contact of the die, a second pillar (i.e. 1106A/1106B) having a second pillar height (i.e. H4, see Figure 11B), wherein the second pillar height is greater than the first pillar height (i.e. H4 > H3, see at least paragraphs 0069 and 0070); and forming, on the second pillar, a second solder cap (i.e. 1206A/1206B) having a second solder cap height, wherein the second solder cap height is less than the first solder cap height (i.e. see at least Figures 12 and 13).
In re claim 31, Farooq et al discloses before forming the first solder cap, forming a first barrier layer (i.e. 1201A/1201B) on the first pillar; and before forming the second solder cap, forming a second barrier layer (i.e. 1201A/1201B) on the second pillar.
In re claim 33, Farooq et al discloses wherein the at least one first pillar bump has a first characteristic dimension along a direction orthogonal to the first pillar height and the at least one second pillar bump has a second characteristic dimension along the direction, and wherein the first characteristic dimension is greater than the second characteristic dimension (i.e. see at least Figures 11-13).
Allowable Subject Matter
Claims 3, 4, 6, 8, 9, 11, 14, 15, 17, 19, 20, 22, 24, 26, 27, 29, 32, and 34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANTHONY HO/Primary Examiner, Art Unit 2817