Prosecution Insights
Last updated: May 29, 2026
Application No. 18/526,239

FAN-OUT WAFER-LEVEL PACKAGES AND ASSOCIATED PRODUCTION METHODS

Non-Final OA §102§103
Filed
Dec 01, 2023
Priority
Dec 12, 2022 — DE 102022132967.4
Examiner
HENRY, CALEB E
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies AG
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
1068 granted / 1233 resolved
+18.6% vs TC avg
Moderate +6% lift
Without
With
+6.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
29 currently pending
Career history
1277
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
73.0%
+33.0% vs TC avg
§102
21.7%
-18.3% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1233 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-18 in the reply filed on 3/11/2026 is acknowledged. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3, 9-11 and 16-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hoegerl (20210088600). PNG media_image1.png 249 500 media_image1.png Greyscale Regarding claim 1, Hoegerl teaches a fan-out wafer-level package, comprising: a magnetic field sensor chip (fig. 10: 10; par. 30 teaches this chip being a magnetic field sensor chip); an encapsulation material (fig. 10: 18; par. 35 teaches 18 being encapsulate material) which at least partly encapsulates the magnetic field sensor chip; an external electrical contact element formed by a planar solderable metal coating (fig. 10: 38; par. 53 teaches 38 being a solder connection); and an electrical redistribution layer (fig. 10: 32; par. 54 teaches conductor paths 34 of the rewiring layer 32 can provide the function of a rewiring or redistribution in order to electrically couple connections of the sensor chip 10 to external connections of the sensor package 28) arranged over the encapsulation material and electrically interconnecting the magnetic field sensor chip and the external electrical contact element (as seen in fig. 10, 32 electrically connects 10 and 38). Regarding claim 2, Hoegerl teaches a fan-out wafer-level package as claimed in claim 1, wherein the magnetic field sensor chip comprises at least one TMR sensor element (par. 30). Regarding claim 3, Hoegerl teaches a fan-out wafer-level package as claimed in claim 1, wherein the planar solderable metal coating is fabricated from a nonferromagnetic material (please note that common solder compositions are non-magnetic). Regarding claim 9, Hoegerl teaches a fan-out wafer-level package as claimed in claim 1, wherein at least one part of the electrical redistribution layer is arranged directly on the encapsulation material (please see figure above). Regarding claim 10, Hoegerl teaches a fan-out wafer-level package as claimed in claim 1, wherein edges of the magnetic field sensor chip facing the electrical redistribution layer are enclosed by the encapsulation material (please see figure above). Regarding claim 11, Hoegerl teaches a fan-out wafer-level package as claimed in claim 1, further comprising: a plastics layer (fig. 10: 30; par. 53) arranged between a front side of the magnetic field sensor chip and the electrical redistribution layer and at least partially encapsulated by the encapsulation material, wherein the electrical redistribution layer is arranged directly on the plastics layer and wherein the plastics layer comprises at least one of a polyimide, an epoxy, or a photo resist (par. 53). Regarding claim 16, Hoegerl teaches a fan-out wafer-level package as claimed in claim 1, further comprising: a chip back side protection layer (fig. 10: 30) arranged on a back side of the magnetic field sensor chip and at least partially encapsulated by the encapsulation material (please see figure above). Regarding claim 17, Hoegerl doesn’t explicitly teach a fan-out wafer-level package as claimed in claim 1, wherein dimensions of the fan-out wafer-level package are configured to integrate the fan-out wafer-level package in a camera module of a smartphone. However, this limitation amounts to a “recitation with respect to the manner in which a claimed device is intended to be employed” and it has been held that in these situations, the limitation do not differentiate the claimed device from a prior art device if the prior art device teaches all the structural limitations of the claim (please see reject of claim 1 which shows structural limitations of the device being covered). Regarding claim 18, Hoegerl doesn’t explicitly teach a fan-out wafer-level package as claimed in claim 1, wherein the magnetic field sensor chip is configured to be used in at least one of an optical image stabilization application, an autofocus application, or an optical zoom application of the camera module. However, this limitation amounts to a “recitation with respect to the manner in which a claimed device is intended to be employed” and it has been held that in these situations, the limitation do not differentiate the claimed device from a prior art device if the prior art device teaches all the structural limitations of the claim (please see reject of claim 1 which shows structural limitations of the device being covered). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hoegerl as applied to claim 1 above, and further in view of Vadhavkar (20130049039). Regarding claim 4, 14 and 15, Hoegerl teaches a fan-out wafer-level package as claimed in claim 1. Hoegerl fails to teach: the planar solderable metal coating comprises a layer stack with a first layer made of copper and a second layer made of at least one of tin or silver a solder mask which is fabricated based on atomic layer deposition, wherein the solder mask is arranged on the electrical redistribution layer and open at positions of the planar solderable metal coating the solder mask comprises at least one of silicon nitride or aluminum oxide Vadhavkar teaches a package using solder as connection elements wherein the planar solderable metal coating comprises a layer stack with a first layer made of copper and a second layer made of at least one of tin or silver (par. 28 teaches solder connections comprising a layer of Cu and ITO), a solder mask which is fabricated based on atomic layer deposition (par. 44 teaches a solder mark being deposited by ALD), wherein the solder mask is arranged on the electrical redistribution layer and open at positions of the planar solderable metal coating (fig. 10) and the solder mask comprises at least one of silicon nitride or aluminum oxide (par. 26). The use of copper and tin in a combined solder alloy has been known in the art because each metal brings complementary properties (e.g. tin’s enhanced wetting and copper’s enhanced electrical conductivity) that make the joint stronger, more reliable, and better suited for modern electronics. Further, the use of SiN has been known since it provides mechanical stability and prevents movement of the solder. It would have been obvious to use these teachings of Vadhavkar in the primary reference, as it would yield aforementioned predictable improvements in the primary art. Thus, it would have been obvious to a PHOSITA, at the time of filing, to utilize aforementioned teachings of the prior art(s) in the primary prior art(s) due to aforementioned reason(s). Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hoegerl as applied to claim 1 above, and further in view of SUNAMOTO (20190393173). Regarding claim 5, SUNAMOTO teaches a fan-out wafer-level package as claimed in claim 1. SUNAMOTO fails to teach: the planar solderable metal coating comprises a layer stack with a first layer made of nickel-phosphorus and a second layer made of at least one of palladium or gold SUNAMOTO teaches providing semiconductor devices wherein a layer made of nickel-phosphorus (par. 12) and a layer made of at least one of Au (par. 12) wherein it is taught that these layers allows for enhance joining of the solder to the semiconductor devices surface. The use of the teachings in primary reference would yield aforementioned predictable improvements in the primary art. Thus, it would have been obvious to a PHOSITA, at the time of filing, to utilize aforementioned teachings of the prior art(s) in the primary prior art(s) due to aforementioned reason(s). Allowable Subject Matter Claim 6, dependent on claim 5, is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CALEB E HENRY/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Dec 01, 2023
Application Filed
May 12, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
93%
With Interview (+6.1%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1233 resolved cases by this examiner. Grant probability derived from career allowance rate.

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