DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement(s) (IDS), Form PTO-1449, filed 18 February 2025. The information therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 11, 13-14 and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2023/0067140) (hereinafter, “Chen”).
Re: independent claim 11, Chen discloses in figs. 2-3 and 4A-4B a memory device, comprising: a memory cell comprising: a programming transistor (310); and a first reading transistor (312) in electrical connection with the programming transistor in series and in electrical connection with a bit line (BL); wherein the memory cell is formed in one of a plurality of first metallization layers (fig. 4A, [0056]) formed over a first surface of a substrate; and wherein the bit line (BL) is formed in one of a plurality of second metallization layers (fig. 4B) formed over a second surface of the substrate opposite to the first surface.
Re: claim 13, Chen discloses figs. 2-3 and 4A-4B the memory device of claim 11, wherein each of the programming transistor and the first reading transistor has a semiconductive-behaving material as a channel thereof [0061].
Re: claim 14, Chen discloses figs. 2-3 and 4A-4B the memory device of claim 11, wherein the memory cell further comprises a second reading transistor (322) in electrical connection with the programming transistor (310) and the first reading transistor (312) in series.
Re: claim 16, Chen discloses figs. 2-3 and 4A-4B the memory device of claim 14, wherein the second reading transistor (322) is electrically connected between the first reading transistor (312) and the programming transistor (310).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2023/0067140) (hereinafter, “Chen”) in view of Wu et al. (US 2020/0075610) (hereinafter, “Wu”).
Re: claim 15, Chen discloses the memory device of claim 14.
Chen does not disclose wherein the programming transistor is electrically connected between the first reading transistor and the second reading transistor.
Wu discloses in figs. 1A-1C a programming transistor (MNP0) the is electrically connected between a first reading transistor (MNR0) and a second reading transistor (MNR1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to electrically connect the programming transistor between the first reading transistor and the second reading transistor since it is well within the abilities of one of ordinary skill in the art to determine the relative electrical connections for the programming transistor, the first reading transistor and the second reading transistor for the desired functionality and/or manufacturing method.
Allowable Subject Matter
Claims 1-10 and 17-20 are allowed.
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to teach the claimed limitations in combination namely, as recited in independent claim 1, a memory device, comprising: a plurality of peripheral transistors formed along a first surface of a substrate; a plurality of memory cells formed in one or more of a plurality of first metallization layers disposed over the first surface, each of the plurality of memory cells being operatively coupled to a subset of the peripheral transistors and comprising a programming transistor and at least a first reading transistor; and a plurality of second metallization layers disposed over a second surface of the substrate opposite to the first surface; wherein a first source/drain terminal of the programming transistor is in electrical connection with a first source/drain terminal of the first reading transistor, and a second source/drain terminal of the first reading transistor is in electrical connection with a bit line formed in a corresponding one of the second metallization layers; and as recited in independent claim 17, a method for forming memory devices, comprising: forming a plurality of peripheral transistors along a first surface of a substrate; forming a plurality of first metallization layers disposed over the first surface; forming a plurality of memory cells in one or more of the plurality of first metallization layers, wherein each of the plurality of memory cells is operatively coupled to a subset of the peripheral transistors and comprises a programming transistor and at least a reading transistor; forming a plurality of second metallization layers disposed over a second surface of the substrate opposite to the first surface; and coupling a source/drain terminal of the reading transistor of each of the memory cells to a bit line formed in a corresponding one of the second metallization layers.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chang et al. US 2023/0064751 teach a programming transistor electrically connected between a first reading transistor and a second reading transistor.
Chang et al. US 12,075,614 teach a MIM memory cell including a backside bit line.
Yang et al. US 2025/0070018 teach anti-fuse cells with backside power rails.
Chen et al. US 2025/0070053 teach one-time-programmable memory devices with backside interconnect structures.
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 1/26/2026