Prosecution Insights
Last updated: July 17, 2026
Application No. 18/526,331

SEMICONDUCTOR STRUCTURES INCLUDING WIRE-BOND PADS AND FLIP-CHIP BUMPS AND METHOD OF MAKING THE SAME

Non-Final OA §112
Filed
Dec 01, 2023
Examiner
HSIEH, HSIN YI
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
51%
Grant Probability
Moderate
1-2
OA Rounds
1y 3m
Est. Remaining
56%
With Interview

Examiner Intelligence

Grants 51% of resolved cases
51%
Career Allowance Rate
326 granted / 638 resolved
-16.9% vs TC avg
Moderate +5% lift
Without
With
+5.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 11m
Avg Prosecution
28 currently pending
Career history
693
Total Applications
across all art units

Statute-Specific Performance

§103
35.8%
-4.2% vs TC avg
§102
5.9%
-34.1% vs TC avg
§112
57.1%
+17.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 638 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group III in the reply filed on 02/26/2026 is acknowledged. Drawings The drawings are objected to because many numerals in Figs. 3K and 2L are pointed to wrong regions. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 29 and 34 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 29 recites the limitation "the patterned photosensitive polymer layer" in the first line of the claim. There is insufficient antecedent basis for this limitation in the claim. Claim 34 recites the limitation "the photosensitive polymer layer" in the second line of the claim. There is insufficient antecedent basis for this limitation in the claim. Allowable Subject Matter Claims 15-28 and 30-33 are allowed. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or suggest, singularly or in combination, at least the limitations of "forming a polymer layer over the wire-bond pad and the flip-chip bond pad; etching the polymer layer to expose a first electrically conducting surface of the wire-bond pad and an intermediate electrically conducting surface of the flip-chip bond pad; forming a patterned mask that masks the first electrically conducting surface of the wire-bond pad and exposes the intermediate electrically conducting surface of the flip-chip bond pad; depositing a first electrically conducting material over the patterned mask to thereby form a flip-chip bump over the intermediate electrically conducting surface of the flip-chip bond pad such that the flip-chip bump comprises a second electrically conducting surface; and removing the patterned mask" as recited in claim 15, "forming a polymer layer over the second passivation layer; etching the polymer layer to expose the first electrically conducting surface and the intermediate electrically conducting surface; forming a patterned mask that masks the first electrically conducting surface and exposes the intermediate electrically conducting surface; and depositing an electrically conducting material over the patterned mask to form a flip-chip bump over the intermediate electrically conducting surface, the flip-chip bump comprising a second electrically conducting surface" as recited in claim 21, "forming a polymer layer over the wire-bond pad and the flip-chip bond pad; lithographically patterning the polymer layer to form openings exposing a first electrically conducting surface of the wire-bond pad and an intermediate electrically conducting surface of the flip-chip bond pad; curing the patterned polymer layer; depositing an under-bump metallurgy layer over the patterned polymer layer, the first electrically conducting surface, and the intermediate electrically conducting surface; forming a patterned photoresist over the under-bump metallurgy layer that masks the first electrically conducting surface and exposes the intermediate electrically conducting surface; depositing a conductive material over the patterned photoresist to form a flip-chip bump over the intermediate electrically conducting surface, the flip-chip bump comprising a second electrically conducting surface; removing the patterned photoresist; and etching exposed portions of the under-bump metallurgy layer" as recited in claim 28. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Niwa et al. (US 2023/0411269 A1) teach a wiring board 20 having the flip chip pads 21a and 21d and the wiring bonding pad 21e. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HSIN YI HSIEH whose telephone number is (571)270-3043. The examiner can normally be reached 8:30 - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra V Smith can be reached on 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HSIN YI HSIEH/Primary Examiner, Art Unit 2899 6/16/2026
Read full office action

Prosecution Timeline

Dec 01, 2023
Application Filed
Jun 30, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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LIGHT EMITTING ELEMENT AND METHOD OF MANUFACTURING LIGHT EMITTING ELEMENT
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Patent 12666723
THREE-DIMENSIONAL INTEGRATED CIRCUIT HAVING ESD PROTECTION CIRCUIT
5y 3m to grant Granted Jun 23, 2026
Patent 12652828
STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH EPITAXIAL STRUCTURES
4y 5m to grant Granted Jun 09, 2026
Patent 12635291
METHOD FOR LOCAL REMOVAL OF SEMICONDUCTOR WIRES
4y 5m to grant Granted May 19, 2026
Patent 12622100
LIGHT EMITTING ELEMENT AND DISPLAY DEVICE INCLUDING THE SAME
3y 6m to grant Granted May 05, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
51%
Grant Probability
56%
With Interview (+5.4%)
3y 11m (~1y 3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 638 resolved cases by this examiner. Grant probability derived from career allowance rate.

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