DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 12-13, and18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20210399029 A1 Ohura et al hereafter “Ohura”.
Claim 12 Ohura teaches an image sensor [illustrated fig. 2 disclosed paragraph 0105] comprising:
a substrate (70 fig. 3) having a first surface [see annotation below] and a second surface [see annotation below] opposite to each other and including a first photoelectric conversion region [one of the plurality of 50a fig. 4 comprising 71, 72, 84, 77, 81, 78 fig. 3, ]; and
an isolation region (comprising 82 fig. 3 and fig. 4) in the substrate that extends vertically from the first surface [sufficiently illustrated fig. 3] and defines the first photoelectric conversion region [sufficiently illustrated fig. 3 and fig. 4 it defines the boundaries of the photelectric conversion region], wherein the isolation region comprises:
a trench [see annotation below], a first semiconductor pattern (83 fig. 3) conformally covering an inner wall of the trench [sufficiently illustrated fig. 3], an insulating film (85 fig. 3) conformally covering an inner wall of the first semiconductor pattern [sufficiently illustrated fig. 3], and a second semiconductor pattern (86 fig. 3, met under broadest reasonable interpretation as “polysilicon” is a semiconductor material, disclosed paragraph 136) covering at least a portion of an inner wall of the insulating film and configured to receive a negative bias voltage [explicitly disclosed paragraph 0138 “application of a negative bias to the DTI 82 allows enhancing of the pinning on the side wall of the DTI 82” wherein 82 comprises 86 fig. 3], wherein a vertical distance from the first surface to an uppermost surface of the first semiconductor pattern is substantially the same as a vertical distance from the first surface to an uppermost surface of the second semiconductor pattern [sufficiently illustrated fig. 3 the uppermost surface the first semiconductor pattern and the uppermost surface of the second semiconductor pattern are flush with the first surface of the photoelectric conversion region this meets the limitation as written under broadest reasonable interpretation a measurable vertical distance of “zero” and the applicant does not currently explicitly claim and/or imply the distance is greater than zero as limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).].
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Annotated fig. 3: highlighting the Trench, the first surface, and the second surface viewed form a perspective wherein the first surface is the front and/or top.
Claim 13 Ohura teaches as shown above the image sensor of claim 12, further comprising:
a second photoelectric conversion region [see annotation below] spaced apart in a first direction parallel to the second surface [sufficiently illustrated fig. 4, note X-X’ is represented within fig. 3];
a third photoelectric conversion region [see annotation below] spaced apart in a diagonal direction with respect to the first direction [sufficiently illustrated fig. 4]; and
an insulating layer (a segment of 85 comprised within 82 sufficiently illustrated fig. 3) between the first photoelectric conversion region and the second photoelectric conversion region [sufficiently illustrated fig. 4 wherein the X-X’ illustrated within fig. 3 is indicative of the structures of the plurality of 50a regions and segments of 82 ] and including silicon oxide or silicon nitride [“Silicon oxide” disclosed paragraph 0136].
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Annotated fig. 4: highlighting a first photoelectric conversion regions, a second photoelectric conversion region, and a third photoelectric conversion region
Claim 18 Ohura teaches the image sensor of claim 12, wherein the first semiconductor pattern comprises p-type impurities [sufficiently disclosed paragraph 0130 “P-type solid phase diffusion layer”].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Ohura as applied to the claims above, and further in view of US 20220223635 A1 Kao et al hereafter “Kao”.
Claim 14 Ohura teaches as shown above the image sensor of claim 13,
a conductive layer (a segment of 86 of 82 illustrated figs. 3 and 4, met under broadest reasonable interpretation) between the first photoelectric conversion region and the third photoelectric conversion region [sufficiently illustrated between figs. 3 and 4 wherein fig. 3 is indicative of the structure of fig. 4 ]and including doped polysilicon [sufficiently disclosed paragraph 0138].
Ohura does not teach the conductive layer including undoped polysilicon.
Kao teaches as similar image sensor comprising a similar isolation region (IS2 fig. 2F) comprising a first semiconductor pattern (102B fig. 2F), an insulating layer (comprising 116 and 117 fig. 2F), a conductive layer (P1a/b of 120a/b Paragraph 0025 explicitly discloses as a “conductive structure”) and that undoped polysilicon is a known alternative to doped polysilicon [sufficiently disclosed Paragraph 0061].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to take the conductive layer as Ohura teaches and select undoped polysilicon as Kao teaches such that conductive layer includes undoped polysilicon as selection of a known material based on its suitability for its intended use is prima facie type obviousness [See MPEP 2144.06].
Examiners interpretation regarding claim 14: The examiner notes that within the art there is typically a mutually exclusive distinction that is made between conductive (metals) and semiconductive (semimetals such as polysilicon) in the field of semiconductor technology which has not been made within the claims. Typically, a polysilicon layer would be viewed as semiconductive not conductive, even if it is materially accurate under broadest reasonable interpretation to call polysilicon conductive as it is at least partially- and/or Semi- conductive and/or has a reasonably conductive property. Thus, for the purpose of examination the examiner has included “semiconductive” (semimetals) within the scope of “conductive” (metals) and no objections or 112 rejections have been raised.
Claim 15 Ohura in view of Koa teaches the image sensor of claim 14, wherein the insulating film of the isolation region comprises:
a third region [see annotation below] in contact with at least a portion of the conductive layer [sufficiently illustrated between fig. 3 and 4 wherein fig. 3 is indicative of the structure of fig. 4 and under broadest reasonable interpretation wherein the conductive layer is a segment of and/or part of the second semiconductor pattern]; and a fourth region [see annotation below] in contact with at least a portion of the second semiconductor pattern [sufficiently illustrated fig. 3 in view of fig. 4].
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Annotated fig. 4: highlighting segments of the isolation region
Claim 16 Ohura in view of Kao teaches the image sensor of claim 15, wherein, when viewed from a direction perpendicular to the second surface, the third region corresponds to a corner portion of the insulating film of the isolation region [sufficiently illustrated as a corner portion of the insulating film in fig. 4 wherein fig. 3 is indicative of the structure, as it is in and/or part of a corner].
Claim 17 Ohura in view of Kao teaches the image sensor of claim 14, wherein the conductive layer is electrically connected to the second semiconductor pattern [met under broadest reasonable interpretation is part of and/or a segment of the second semiconductor pattern between the first photoelectric conversion region and the third photoelectric conversion region].
Allowable Subject Matter
Claim 1-11, and 19-20 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 1 recites the limitation “a second semiconductor pattern conformally covering an inner wall of a lower portion of the insulating film, and a conductive pattern covering an inner wall of an upper portion of the insulating film and an uppermost surface and an inner wall of the second semiconductor pattern”
Claim 19 recites “a second semiconductor pattern covering an inner wall of a lower portion of the insulating film” and “a conductive pattern… covering an inner wall of an upper portion of the insulating film and an uppermost and an inner wall of the second semiconductor pattern”
As shown above for the rejection of claim 12 while the examiner found art similar art similar to what is claimed the examiner did not find prior art the teaches the claimed limitation in view of the rest of the claimed limitations nor reason to modify prior art such that the device of would include all the claimed limitations as claimed. Claims 2-11 and 20 have been considered allowed as they are dependent upon claims 1 and 19
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893