DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I drawn to claims 1-13 and 18-20 in the reply filed on March 13, 2026 is acknowledged. No claims have been amended. New claims 21-24 have been added and read on the elected invention Group I. Claims 14-17 have been canceled. Currently claims 1-13 and 21-24 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/18/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 18-19 and 21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by CHONG JONG WHA (KR 20150058687 A) “CHONG et al.”
Regarding Independent Claim 1, CHONG et al. Fig. 1-2 discloses a semiconductor device comprising: a first logic die (“Die1” ¶ [0017]) comprising:
a clock source configured to generate a clock signal (“a clock signal may be provided from the clock source” ¶ [0017]); and
a first clock mesh for receiving the clock signal from the clock source (“A clock signal may be provided to the sinks from the clock source via a top-level tree, a mesh driver, and a leaf-level clock mesh.” ¶ [0019]);
a second logic die (“Die2” ¶ [0017]) stacked over the first logic die (“Die1” ¶ [0017]), the second logic die comprising:
a second clock mesh (“Each die comprises a plurality of mesh grids.” ¶ [0018]) for receiving the clock signal from the clock source (“A clock signal may be provided to the sinks from the clock source via a top-level tree, a mesh driver, and a leaf-level clock mesh.” ¶ [0019]); and
a plurality of conductive connections (“Each die is formed with a mesh structure consisting of a vertical connection line and a horizontal connection line, i. E. Each die comprises a plurality of mesh grids.”; “Each of the connecting lines may be a metal wire” ¶ [0018]) between the first clock mesh and the second clock mesh to transmit the clock signal from the first clock mesh to the second clock mesh (“a clock signal may be provided from the clock source to the first die Die1 and to the second die Die2 via the TSV.” ¶ [0017]).
Regarding Claim 2, CHONG et al. discloses the limitations of claim 1. CHONG et al. further discloses, wherein the plurality of conductive connections comprises conductive vias electrically connecting the first clock mesh to the second clock mesh (“clock signal may be provided from the clock source to the first die Die1 and to the second die Die2 via the TSV.” ¶ [0017]).
Regarding Independent Claim 18, CHONG et al. Fig. 1-2 discloses a method of fabricating a semiconductor device, the method comprising:
stacking and bonding a first logic die (“Die1” ¶ [0017]) including a clock source (“a clock signal may be provided from the clock source” ¶ [0017]) and a first clock mesh with a second logic die (“Die2” ¶ [0017]) including a second clock mesh; and
electrically coupling the first clock mesh to the second clock mesh with a plurality of conductive connections (“Each die is formed with a mesh structure consisting of a vertical connection line and a horizontal connection line, i. E. Each die comprises a plurality of mesh grids.”; “Each of the connecting lines may be a metal wire” ¶ [0018]) to transmit a clock signal from the clock source and first clock mesh to the second clock mesh (“a clock signal may be provided from the clock source to the first die Die1 and to the second die Die2 via the TSV.” ¶ [0017]).
Regarding Claim 19, CHONG et al. discloses the limitations of claim 18. CHONG et al. further discloses, wherein electrically coupling the first clock mesh to the second clock mesh with the plurality of conductive connections comprises electrically shorting the first clock mesh to the second clock mesh with an array of conductive connections (“clock signal may be provided from the clock source to the first die Die1 and to the second die Die2 via the TSV.” ¶ [0017]).
Regarding Independent Claim 21, CHONG et al. Fig. 1-2 discloses a semiconductor device comprising:
a first die (“Die1” ¶ [0017]) comprising a clock source configured to generate a clock signal (“a clock signal may be provided from the clock source” ¶ [0017]);
a second die (“Die2” ¶ [0017]); and
a plurality of conductive connections (“Each die is formed with a mesh structure consisting of a vertical connection line and a horizontal connection line, i. E. Each die comprises a plurality of mesh grids.”; “Each of the connecting lines may be a metal wire” ¶ [0018]) between the first die and the second die configured to transmit the clock signal from the first die to the second die (“a clock signal may be provided from the clock source to the first die Die1 and to the second die Die2 via the TSV.” ¶ [0017]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
Claims 3-5 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over CHONG JONG WHA (KR 20150058687 A) “CHONG et al.” in view of DeLaCruz; Javier (US 20180350775 A1) “DeLaCruz et al.”.
Regarding Claim 3, CHONG et al. discloses the limitations of claim 2. CHONG et al. further discloses, wherein the conductive vias are positioned in and pass through at least a portion of the first logic die (“inserts the TSV into the dies to connect the dies (S402).” ¶ [0031]).
However, CHONG et al. does not explicitly show wherein the conductive vias pass through at least a portion of the first logic die.
In the similar field of endeavor of multi-chip packaging devices, DeLaCruz et al. Fig. 22, discloses wherein the conductive vias pass through at least a portion of the first logic die (“several TSVs 2222 are defined through the second die” ¶ [0122]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the TSVs of CHONG et al. with the pass through TSVs of DeLaCruz et al. in order to electrically connect to interconnects/pads on the backside of the second die, on which multiple levels of interconnects are defined (DeLaCruz et al., ¶ [0122]) and to create the signal paths for defining one or more system level circuits for the 3D chip (DeLaCruz et al., ¶ [0123]).
Regarding Claim 4, CHONG et al. discloses the limitations of claim 2. However, CHONG et al. does not disclose, wherein the conductive vias are electrically connected to respective conductive bond pads.
In the similar field of endeavor of multi-chip packaging devices, DeLaCruz et al. Fig. 22, discloses, wherein the conductive vias are electrically connected to respective conductive bond pads (“TSVs electrically connect to interconnects/pads” ¶ [0122]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the TSVs of CHONG et al. with the pass through TSVs connected to bond pads of DeLaCruz et al. in order to electrically connect to interconnects/pads on the backside of the second die, on which multiple levels of interconnects are defined (DeLaCruz et al., ¶ [0122]) and to create the signal paths for defining one or more system level circuits for the 3D chip (DeLaCruz et al., ¶ [0123]).
Regarding Claim 5, CHONG et al. discloses the limitations of claim 4. However, CHONG et al. does not disclose, wherein the first logic die comprises the conductive vias and the second logic die comprises the conductive bond pads.
In the similar field of endeavor of multi-chip packaging devices, DeLaCruz et al. Figs. 1-22, discloses, wherein the first logic die comprises the conductive vias and the second logic die comprises the conductive bond pads (“the power/ground lines on the interconnect layer 1325 of the second die connect to pads on this die's interconnect layer 1320, and these pads are connected through direct bonded connections (e.g., DBI connections) to power lines on the interconnect layer 1315” ¶ [0084]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the TSVs of CHONG et al. with the pass through TSVs connected to bond pads of DeLaCruz et al. in order to distribute the power/ground signals to other interconnect and substrate layers on each die through vias (DeLaCruz et al., ¶ [0084]) and The direct-bonded connections in some embodiments emanate from the corners of some of the H-structures and travel along the z-axis. The center of the largest H-structure in this clock tree receives the clock signal from a clock circuit that is defined on the second die's substrate in some embodiments. In other embodiments, this signal is supplied to other locations of the H-structure from the clock circuit on the second die's substrate, or to a location on the H-structure from a clock circuit on the first die's substrate (DeLaCruz et al., ¶ [0085]).
Regarding Claim 22, CHONG et al. discloses the limitations of claim 21. However, CHONG et al. does not disclose, wherein the first die comprises the plurality of conductive connections and the second die comprises a plurality of conductive bond pads.
In the similar field of endeavor of multi-chip packaging devices, DeLaCruz et al. Figs. 1-22, discloses, wherein the first die comprises the plurality of conductive connections and the second die comprises a plurality of conductive bond pads (“the power/ground lines on the interconnect layer 1325 of the second die connect to pads on this die's interconnect layer 1320, and these pads are connected through direct bonded connections (e.g., DBI connections) to power lines on the interconnect layer 1315” ¶ [0084]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the TSVs of CHONG et al. with the pass through TSVs connected to bond pads of DeLaCruz et al. in order to distribute the power/ground signals to other interconnect and substrate layers on each die through vias (DeLaCruz et al., ¶ [0084]) and The direct-bonded connections in some embodiments emanate from the corners of some of the H-structures and travel along the z-axis. The center of the largest H-structure in this clock tree receives the clock signal from a clock circuit that is defined on the second die's substrate in some embodiments. In other embodiments, this signal is supplied to other locations of the H-structure from the clock circuit on the second die's substrate, or to a location on the H-structure from a clock circuit on the first die's substrate (DeLaCruz et al., ¶ [0085]).
Regarding Claim 23, CHONG as modified by DeLaCruz et al. discloses the limitations of claim 22. However, CHONG et al. does not disclose, wherein the plurality of conductive connections comprises conductive vias electrically connecting the first die to the second die through the conductive bond pads.
In the similar field of endeavor of multi-chip packaging devices, DeLaCruz et al. Fig. 22, discloses, wherein the conductive vias are electrically connected to respective conductive bond pads (“TSVs electrically connect to interconnects/pads” ¶ [0122]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the TSVs of CHONG et al. with the pass through TSVs connected to bond pads of DeLaCruz et al. in order to electrically connect to interconnects/pads on the backside of the second die, on which multiple levels of interconnects are defined (DeLaCruz et al., ¶ [0122]) and to create the signal paths for defining one or more system level circuits for the 3D chip (DeLaCruz et al., ¶ [0123]).
Claims 6 are rejected under 35 U.S.C. 103 as being unpatentable over CHONG JONG WHA (KR 20150058687 A) “CHONG et al.” in view of LI, SHENGGAO (US 20160013799 A1) “LI et al.”.
Regarding Claim 6, CHONG et al. discloses the limitations of claim 1. However, CHONG et al. does not disclose, wherein the clock source comprises a phase-locked loop clock source.
In the similar field of endeavor of multi-chip packaging devices, LI et al Figs. 1A-2 discloses, wherein the clock source comprises a phase-locked loop clock source (“First Die 102 comprises a phase locked loop (PLL)” ¶ [0027]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the clock source of CHONG et al. by using phase locked loops (PLLs) in order to generate a signal of a first phase and a signal of a second phase for the phase interpolator (LI et al. ¶ [0091]) and to reduce clock skew between multiple clock domains on the same die (LI et al. ¶ [0001])
Claims 7 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over CHONG JONG WHA (KR 20150058687 A) “CHONG et al.” in view of LEE, Dong Uk (US 20210295940 A1) “LEE et al.”.
Regarding Claim 7, CHONG et al. discloses the limitations of claim 1. CHONG et al. further discloses, wherein the second logic die further comprises a local clock source (“clock dice are formed in each of the dies” ¶ [0018]).
However, CHONG et al. does not disclose, clock source configured to generate a test clock signal for testing of the second logic die separate from the first logic die.
In the similar field of endeavor of multi-chip packaging devices, LEE et al Figs. 4-6 discloses, clock source configured to generate a test clock signal for testing of the second logic die separate from the first logic die (“The second test control signal generation circuit 480 may generate second internal test data IDATA1 by serializing the parallelized test data PDATA1 in response to the first internal test clock ICLK0 and the second external test clock TCLK1.” ¶ [0045]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the clock source of CHONG et al. by using test clock of LEE et al. in order to produce parallelized test data and transfer the parallelized test data to a memory area in response to the input clock and the output clock; and a test control signal generation circuit suitable for generating internal test data by serializing the parallelized test data and transferring the internal test data to the channel in response to the input clock and the output clock. (LEE et al. ¶ [0007]) and to perform a clock gating operation and may be synchronized to the input timing of the internal test data IDATA. Therefore, the internal test data IDATA, the internal test clock ICLK, and the internal reset signals IRESET may be synchronized and transferred between the memory devices (LEE et al. ¶ [0071]).
Regarding Claim 11, CHONG et al. discloses the limitations of claim 1. CHONG et al. further discloses, wherein: the first logic die further comprises:
a first plurality of state storage elements (“the sinks” ¶ [0019]) configured for receiving the clock signal from the first clock mesh (“A clock signal may be provided to the sinks from the clock source via a top-level tree, a mesh driver, and a leaf-level clock mesh.” ¶ [0019]);
the second logic die further comprises:
a second plurality of state storage elements configured for receiving the clock signal from the second clock mesh (“A clock signal may be provided to the sinks from the clock source via a top-level tree, a mesh driver, and a leaf-level clock mesh.” ¶ [0019]);
However, CHONG et al. does not disclose, at least one first level of gating between the first clock mesh and the first plurality of state storage elements; and
at least one second level of gating between the second clock mesh and the second plurality of state storage elements.
In the similar field of endeavor of multi-chip packaging devices, LEE et al Figs. 4-6 discloses, at least one first level of gating between the first clock mesh and the first plurality of state storage elements (“clock generation circuit 520 may include logic gates that combine the reference clock RCLK and the external test clock TCLK, respectively, with the reset signal RESET.” ¶ [0054]); and
at least one second level of gating between the second clock mesh and the second plurality of state storage elements (“clock generation circuit 520 may include logic gates that combine the reference clock RCLK and the external test clock TCLK, respectively, with the reset signal RESET.” ¶ [0054]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the clock source of CHONG et al. by using clock source with gating of LEE et al. in order to produce parallelized test data and transfer the parallelized test data to a memory area in response to the input clock and the output clock; and a test control signal generation circuit suitable for generating internal test data by serializing the parallelized test data and transferring the internal test data to the channel in response to the input clock and the output clock. (LEE et al. ¶ [0007]) and to perform a clock gating operation and may be synchronized to the input timing of the internal test data IDATA. Therefore, the internal test data IDATA, the internal test clock ICLK, and the internal reset signals IRESET may be synchronized and transferred between the memory devices (LEE et al. ¶ [0071]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over CHONG JONG WHA (KR 20150058687 A) “CHONG et al.” in view of LEE, Dong Uk (US 20210295940 A1) “LEE et al.” further in view of Ding, Yi-Xiao (US 12339701 B1) “Ding et al.”.
Regarding Claim 12, CHONG et al. as modified by LEE et al. discloses the limitations of claim 11. However, CHONG et al. does not disclose, wherein:
the first plurality of state storage elements comprises a first plurality of flip-flop elements; and
the second plurality of state storage elements comprises a second plurality of flip-flop elements.
In the similar field of endeavor of IC device with clock tree system Ding et al. Fig. 2 discloses, the first plurality of state storage elements comprises a first plurality of flip-flop elements (“the clock sinks include registers or flip-flops that can store information, synchronized by the clock signal. In a circuit for using edge-triggered registers, when a clock edge (e.g., rising edge or falling edge) arrives at a register, the data stored at the register is updated.” Column 2 lines 12-17); and
the second plurality of state storage elements comprises a second plurality of flip-flop elements (“the clock sinks include registers or flip-flops that can store information, synchronized by the clock signal. In a circuit for using edge-triggered registers, when a clock edge (e.g., rising edge or falling edge) arrives at a register, the data stored at the register is updated.” Column 2 lines 12-17).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the clock sinks of CHONG et al. with the flip-flops of Ding et al. in order to store information, synchronized by the clock signal. In a circuit for using edge-triggered registers, when a clock edge (e.g., rising edge or falling edge) arrives at a register, the data stored at the register is updated (Ding et al. Column 2 lines 13-17).
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over CHONG JONG WHA (KR 20150058687 A) “CHONG et al.” in view of LEE, Dong Uk (US 20210295940 A1) “LEE et al.” further in view of DeLaCruz; Javier (US 20180350775 A1) “DeLaCruz et al.”.
Regarding Claim 8, CHONG et al. as modified by LEE et al. discloses the limitations of claim 7. However, CHONG et al. does not disclose, wherein the second logic die further comprises a tri-state driver between the local clock source and the second clock mesh.
In the similar field of endeavor of multi-chip packaging devices, DeLaCruz et al. Figs. 1-22, discloses, wherein the second logic die further comprises a tri-state driver (“I/O circuitry (e.g., I/O drivers)” ¶ [0111]; an Input/Output (I/O) driver in a memory chip is practically always a tri-state driver (or tri-state buffer)) between the local clock source and the second clock mesh (“two face-to-face mounted IC dies that form a 3D chip 2052 and that share data I/O circuits.” ¶ [0110]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the TSVs of CHONG et al. with the pass through TSVs connected to bond pads of DeLaCruz et al. in order to electrically connect to perform the computation operations of the dies (DeLaCruz et al., ¶ [0111]).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over CHONG JONG WHA (KR 20150058687 A) “CHONG et al.” in view of Lotz; Jonathan P. (US 20120292777 A1) “Lotz et al.”.
Regarding Claim 9, CHONG et al. discloses the limitations of claim 1. CHONG et al. further discloses, wherein the plurality of conductive connections comprises conductive connections between the first clock mesh and the second clock mesh (“the design method may select the mesh size of each die considering the position of sinks present in each die, the threshold of clock skew, and the maximum number of insertable TSVs.” ¶ [0032]).
However, CHONG explicitly does disclose at least one hundred conductive connections.
In the similar field of endeavor of IC devices, Lotz et al. discloses, at least one hundred conductive connections (“millions of components (e.g., transistors, interconnects, pads, etc.) are integrated into a single wafer/die” ¶ [0004]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the number of interconnects of CHONG et al. with the number of interconnects of Lotz et al. in order to improve chip performance by increasing the component density on the wafer/die while adding or maintaining the number of power supply and input/output (I/O) pins for each integrated circuit device, all while simultaneously improving electrical performance, increasing thermal dissipation, and reducing die size (Lotz et al., ¶ [0004]).
Regarding Claim 10, CHONG et al. discloses the limitations of claim 1. CHONG et al. further discloses, wherein the plurality of conductive connections comprises conductive connections between the first clock mesh and the second clock mesh (“the design method may select the mesh size of each die considering the position of sinks present in each die, the threshold of clock skew, and the maximum number of insertable TSVs.” ¶ [0032]).
However, CHONG explicitly does disclose at least one thousand conductive connections.
In the similar field of endeavor of IC devices, Lotz et al. discloses, at least one hundred conductive connections (“millions of components (e.g., transistors, interconnects, pads, etc.) are integrated into a single wafer/die” ¶ [0004]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the number of interconnects of CHONG et al. with the number of interconnects of Lotz et al. in order to improve chip performance by increasing the component density on the wafer/die while adding or maintaining the number of power supply and input/output (I/O) pins for each integrated circuit device, all while simultaneously improving electrical performance, increasing thermal dissipation, and reducing die size (Lotz et al., ¶ [0004]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over CHONG JONG WHA (KR 20150058687 A) “CHONG et al.” in view of DeLaCruz; Javier (US 20180350775 A1) “DeLaCruz et al.” further in view of Lotz; Jonathan P. (US 20120292777 A1) “Lotz et al.”.
Regarding Claim 20, CHONG et al. discloses the limitations of claim 19. CHONG et al. further discloses, wherein electrically shorting the first clock mesh to the second clock mesh with an array of conductive connections comprises electrically shorting the first clock mesh to the second clock mesh (“Each die is formed with a mesh structure consisting of a vertical connection line and a horizontal connection line, i. E. Each die comprises a plurality of mesh grids.”; “Each of the connecting lines may be a metal wire” ¶ [0018]) with conductive vias (“the design method may select the mesh size of each die considering the position of sinks present in each die, the threshold of clock skew, and the maximum number of insertable TSVs.” ¶ [0032]) passing through at least a portion of the first logic die (“inserts the TSV into the dies to connect the dies (S402).” ¶ [0031]).
However, CHONG et al. does not explicitly show wherein the conductive vias pass through at least a portion of the first logic die.
In the similar field of endeavor of multi-chip packaging devices, DeLaCruz et al. Fig. 22, discloses wherein the conductive vias pass through at least a portion of the first logic die (“several TSVs 2222 are defined through the second die” ¶ [0122]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the TSVs of CHONG et al. with the pass through TSVs of DeLaCruz et al. in order to electrically connect to interconnects/pads on the backside of the second die, on which multiple levels of interconnects are defined (DeLaCruz et al., ¶ [0122]) and to create the signal paths for defining one or more system level circuits for the 3D chip (DeLaCruz et al., ¶ [0123]).
However, DeLaCruz et al. does not disclose, at least one hundred conductive connections.
In the similar field of endeavor of IC devices, Lotz et al. discloses, at least one hundred conductive connections (“millions of components (e.g., transistors, interconnects, pads, etc.) are integrated into a single wafer/die” ¶ [0004]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the number of interconnects of CHONG et al. with the number of interconnects of Lotz et al. in order to improve chip performance by increasing the component density on the wafer/die while adding or maintaining the number of power supply and input/output (I/O) pins for each integrated circuit device, all while simultaneously improving electrical performance, increasing thermal dissipation, and reducing die size (Lotz et al., ¶ [0004]).
Claims 13 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over CHONG JONG WHA (KR 20150058687 A) “CHONG et al.” in view of Kang; Uk-song (US 20110292708 A1) “Kang et al.”.
Regarding Claim 13, CHONG et al. discloses the limitations of claim 1. However, CHONG et al. does not disclose, wherein the first logic die further comprises a tri-state driver between the clock source and the first clock mesh,
wherein the tri-state driver is deactivated during testing of the first logic die separate from the second logic die and is activated during operation of the first logic die and second logic die stacked over the first logic die to boost the clock signal for use by both the first logic die and the second logic die.
In the similar filed of endeavor of 3D semiconductor devices, Kang et al. Figs. 16-17 discloses, wherein the first logic die further comprises a tri-state driver (“tri-state driver” ¶ [0156]) between the clock source and the first clock mesh,
wherein the tri-state driver is deactivated (“the driver 1637 of the slave chip 120 are not used during the package level test.” ¶ [0150]) during testing of the first logic die separate from the second logic die and is activated during operation of the first logic die and second logic die stacked over the first logic die to boost the clock signal for use by both the first logic die and the second logic die (“A package level test may comprise testing a package including master chip 110 and slave chip 120 stacked with master chip 110.” ¶ [0150]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the testing of first and second dies of CHONG et al. with the testing of Kang et al. in order to achieve improved functionality and higher performance (Kang et al. ¶ [0003])
Regarding Claim 24, CHONG et al. discloses the limitations of claim 21. However, CHONG et al. does not disclose, wherein the first die further comprises a tri-state driver between the clock source and one or more of the plurality of conductive connections, wherein the tri-state driver is deactivated during testing of the first die separate from the second die and is activated during operation of the first die and second die to boost the clock signal for use by both the first die and the second die.
In the similar filed of endeavor of 3D semiconductor devices, Kang et al. Figs. 16-17 discloses, wherein the first die further comprises a tri-state driver (“tri-state driver” ¶ [0156]) between the clock source and one or more of the plurality of conductive connections,
wherein the tri-state driver is deactivated (“the driver 1637 of the slave chip 120 are not used during the package level test.” ¶ [0150]) during testing of the first die separate from the second die and is activated during operation of the first die and second die stacked over the first logic die to boost the clock signal for use by both the first logic die and the second logic die (“A package level test may comprise testing a package including master chip 110 and slave chip 120 stacked with master chip 110.” ¶ [0150]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the testing of first and second dies of CHONG et al. with the testing of Kang et al. in order to achieve improved functionality and higher performance (Kang et al. ¶ [0003]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKHEE SARKER-NAG whose telephone number is (703)756-4655. The examiner can normally be reached Monday -Friday 7:15 AM to 5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, YARA J. GREEN can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights