DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20240355747 A1 – hereinafter Li) in view of Sunohara et al. (US 7727802 B2 – hereinafter Sunohara).
Regarding independent claim 1, Li teaches:
A semiconductor package (100 – Fig. 1 – [0027] – “IC package 100”)
comprising:
an integrated circuit package component (102 – Fig. 1 – [0027] – “IC package
102”), wherein the integrated circuit package component comprises (102) a semiconductor die (104(2) – Fig. 1 – [0027] – “IC package 102 that includes first, second, and third semiconductor dies (“dies”) 104(1), 104(2), 104(3)”); and
a package substrate (108 – Fig. 1 – [0027] – “first and second routing substrates 108(1), 108(2) as substrates 108(1), 108(2)” – hereinafter ‘108’) physically and electrically connected to the integrated circuit package component (104(2)) on a first side of the package substrate (108(1) – Fig. 1 shows this), the package substrate comprising:
a plurality of routing layers, each routing layer comprising:
an insulating layer, the insulating layer comprising a polymer base; and
conductive features extending through the insulating layer; and
an electrical circuit device embedded in the routing layers, wherein the electrical circuit device is electrically connected to the integrated circuit package component by the conductive features of the plurality of routing layers.
Li does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Sunohara teaches
the package substrate (50 – Fig. 10 – [5:7] – “substrate 50”) comprising:
a plurality of routing layers (31 – Fig 8 – [5:42-43] – “laminated structure 31 made up of plural buildup layers (e.g., buildup layers 17 and 23)”), each routing layer (31) comprising:
an insulating layer (17A – Fig. 8 – [6:11-12 ] – “buildup layers 17 and 18, first, insulating layers 17A and 18A”), the insulating layer (17A) comprising a polymer base ([6:11-18] – “form the buildup layers 17 and 18, first, insulating layers 17A and 18A are respectively formed on the upper and lower surfaces of the core substrate 11 as is shown in FIG. 3. Specifically, buildup insulating resin films (simply referred to as `buildup film` hereinafter) are arranged on the surfaces of the core substrate 11 after which a hardening process is performed on the buildup films. In this way, the insulating layers 17A and 18A are formed” – a hardened resin is a ploymer); and
conductive features (14 – Fig. 8 – [11:3-4] – “wirings 14”) extending through the insulating layer (17A – Fig 8 shows this); and
an electrical circuit device (32 – Fig. 8 – [4:58] – “an embedded electronic component 32”) embedded in the routing layers (31), wherein the electrical circuit device (32) is electrically connected to the integrated circuit package component (51) by the conductive features (14) of the plurality of routing layers (31 – Fig. 10 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the package substrate structure as taught by Sunohara into Li.
An ordinary artisan would have been motivated to use the known technique of Sunohara in the manner set forth above to produce the predictable result of [0004] – “The substrate is designed to be included in an IC package to support a semiconductor die (“die”) and/or other circuits and to provide signal routing paths to the die and/or other circuits as a routing substrate.”
Regarding claim 6, Li as modified by Sunohara, teaches claim 1 from which claim 6 depends. Li further teaches
wherein a first conductive via (813(4) – Fig. 8 – [0065] – “fourth metal
interconnects 813(4) (e.g., vias, metal traces, metal lines)”) of the conductive features (130(2)(4) – Fig. 9 – [0056] – “”Metal interconnects 130(2) are patterned in the first, second, and third metallization layers 125(1)-125(3) to provide signal routing paths) of the plurality of routing layers is physically and electrically connected to the electrical circuit device (126(4) – Fig. 8 – [0065] – “the fourth electrical device 126(4)”), and wherein the electrical circuit device (126(4)) is between the first conductive via (813(4)) and the integrated circuit package (102) component (126(4) – Fig. 8 shows this).
Li does not expressly disclose the other limitations of claim 6.
However, in an analogous art, Sunohara teaches
the plurality of routing layers (31).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the routing layers structure as taught by Sunohara into Li.
An ordinary artisan would have been motivated to use the known technique of Sunohara in the manner set forth above to produce the predictable result as stated above in claim 1.
Claims 2-4, 8, 9, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Sunohara and Aoki et al. (US 20220246516 A1 – hereinafter Aoki).
Regarding claim 2, Li as modified by Sunohara, teaches claim 1 from which claim 2 depends. Li and Sunohara do not expressly disclose the other limitations of claim 2.
However, in an analogous art, Aoki teaches
wherein 30% or more ([0039] – “The insulating layers 113 are provided in
contact with the wire layers L1 to L3 in the direction of the normal to the substrate surface of the wiring substrate 11, and each insulating layer 113 includes a glass woven fabric 113 a containing a resin” – each layer means every layer which is 30% or more of the layers – hereinafter ‘30%’) of the plurality of routing layers ([0039] – “The insulating layers 113 are provided in contact with the wire layers L1 to L3” – these correspond to routing layers – hereinafter ‘RL’) each comprises a woven glass fabric (113a – Fig. 2 – [0040] – “Each insulating layer 113 includes the glass woven fabric 113a. The glass woven fabric 113a is a woven fabric of glass fibers. The glass woven fabric 113a contains a resin. Thus, each insulating layer 113 is formed by impregnating the glass woven fabric 113a with a resin”) embedded in the polymer base ([0083] – “The glass fibers GF1 and GF2 in the glass woven fabric 113 a of the insulating layer 1131 are S-glass, for example. The glass fibers GF1 and GF2 in the glass woven fabric 113 a of the insulating layer 1132 are E-glass, for example. In such a case, the wiring substrate 11 has a higher coefficient of thermal expansion at positions closer to the semiconductor chips CH1, and has a smaller coefficient of thermal expansion at positions closer to the metal bumps B. When the wiring substrate 11 is produced, the insulating layers 1131 and 1132 are bonded together, and then are heated to the curing temperature of the wiring substrate 11” – a heated resin is a polymer) of the corresponding insulating layer ([0039] – “The insulating layers 113).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the routing layers and woven structure as taught by Aoki into Li and Sunohara.
An ordinary artisan would have been motivated to use the known technique of Aoki in the manner set forth above to produce the predictable result of preventing [0004] – “a substrate (i.e., the package) warps due to the difference in the coefficient of thermal expansion between silicon (Si) of a memory chip and the substrate.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 3, Li as modified by Sunohara and Aoki, teaches claim 2 from which claim 3 depends. Li further teaches
wherein the 30% or more of the plurality of routing layers with the woven
glass fabrics are consecutive routing layers (122(1) – Fig. 1 – [0029] – “metallization structure 122(1)”) in on a second side (Fig. 1 annotated, see below – hereinafter ‘S2’) of the package substrate (108), and wherein the second side (S2) is opposite to the first side (Fig. 1 annotated, see below – hereinafter ‘S1’).
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Li and Sunohara do not expressly disclose the other limitations of claim 3.
However, in an analogous art, Aoki teaches
wherein the 30% or more (30%) of the plurality of routing layers (RL)
with the woven glass fabrics (113a).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the routing layers and woven structure as taught by Aoki into Li and Sunohara.
An ordinary artisan would have been motivated to use the known technique of Aoki in the manner set forth above to produce the predictable result as stated above in claim 2.
Regarding claim 4, Li as modified by Sunohara and Aoki, teaches claim 2 from which claim 4 depends. Li does not expressly disclose the limitations of claim 4.
However, in an analogous art, Sunohara teaches
wherein the electrical circuit device (32) extends through one or more
routing layers (31 – Fig. 8 shows this) with the woven glass fabrics.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the routing layers structure as taught by Sunohara into Li.
An ordinary artisan would have been motivated to use the known technique of Sunohara in the manner set forth above to produce the predictable result as stated above in claim 1.
Li and Sunohara do not expressly disclose the other limitations of claim 3.
However, in an analogous art, Aoki teaches
the woven glass fabrics (113a).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the woven structure as taught by Aoki into Li and Sunohara.
An ordinary artisan would have been motivated to use the known technique of Aoki in the manner set forth above to produce the predictable result as stated above in claim 2.
Regarding independent claim 8, Li teaches:
A semiconductor package comprising:
an integrated circuit package component (102 – Fig. 1 – [0027] – “IC package
102”), wherein the integrated circuit package component (102) comprises a semiconductor die (104(2) – Fig. 1 – [0027] – “IC package 102 that includes first, second, and third semiconductor dies (“dies”) 104(1), 104(2), 104(3)”); and
a package substrate (108 – Fig. 1 – [0027] – “first and second routing substrates 108(1), 108(2) as substrates 108(1), 108(2)” – hereinafter ‘108’) bonded to the integrated circuit package component (104(2)) on a first side of the package substrate (108(1) – Fig. 1 shows this), the package substrate comprising:
insulating layers, wherein each of the insulating layers comprises a woven glass fabric and a polymer base coated on the woven glass fabric;
conductive features, wherein each of the conductive features comprises a conductive line between neighboring insulating layers and a conductive via extending through the corresponding insulating layer; and
an electrical circuit device (126(4) – Fig. 4E – [0065] – “the fourth electrical device 126(4)”), wherein a top surface of the electrical
circuit device (126(4)) is covered by a first insulating layer (408(1) – Fig. 4F – [0055] – “first insulating layer 408(1)”) of the insulating layers (408) and a bottom surface of the electrical circuit device (126(4)) is in contact with a second insulating layer (408(2) – Fig. 4F – [0055] – “second insulating layer 408(2)”) of the insulating layers (408), wherein the first insulating layer (408(1)) is between the electrical circuit device (126(4)) and the integrated circuit package component (104(2) – Fig. 1 shows this), and wherein a first conductive via (813(4) – Fig. 8 – [0065] – “fourth metal interconnects 813(4) (e.g., vias, metal traces, metal lines)”) of the conductive features (130(2)(4) – Fig. 9 – [0071] – “metal interconnects 130(2)(4)”) extends through the second insulating layer (408(2)) to physically and electrically connect to the electrical circuit device (126(4) – Fig. 9 shows this).
Li does not expressly disclose the other limitations of claim 8.
However, in an analogous art, Sunohara teaches
conductive features (14 – Fig. 8 – [11:3-4] – “wirings 14”), wherein each of the conductive features (14) comprises a conductive line (17C – Fig. 8 – [5:4-5] – “the wiring layers 17C, 18C, 23C, 24C, 34C, and 35C are interconnected by the vias 17B, 18B, 23B, 24B, 34B, and 35B”) between neighboring insulating layers (17A) and a conductive via (17B – Fig. 8 – [5:4-5] – “the wiring layers 17C, 18C, 23C, 24C, 34C, and 35C are interconnected by the vias 17B, 18B, 23B, 24B, 34B, and 35B”) extending through the corresponding insulating layer (17A).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive feature structure as taught by Sunohara into Li.
An ordinary artisan would have been motivated to use the known technique of Sunohara in the manner set forth above to produce the predictable result as stated above in claim 1.
Li and Sunohara do not expressly disclose the other limitations of claim 8.
However, in an analogous art, Aoki teaches
the package substrate (11 – Fig. 1 – [0027] – “wiring substrate 11”) comprising:
insulating layers (113 – Fig. 2 – [0039] – “The insulating layers 113 are provided in contact with the wire layers L1 to L3” – these correspond to routing layers – hereinafter ‘RL’), wherein each of the insulating layers (113) comprises a woven glass fabric (113a – Fig. 2 – [0040] – “Each insulating layer 113 includes the glass woven fabric 113a. The glass woven fabric 113a is a woven fabric of glass fibers. The glass woven fabric 113a contains a resin. Thus, each insulating layer 113 is formed by impregnating the glass woven fabric 113a with a resin”) and a polymer base ([0083] – “The glass fibers GF1 and GF2 in the glass woven fabric 113 a of the insulating layer 1131 are S-glass, for example. The glass fibers GF1 and GF2 in the glass woven fabric 113 a of the insulating layer 1132 are E-glass, for example. In such a case, the wiring substrate 11 has a higher coefficient of thermal expansion at positions closer to the semiconductor chips CH1, and has a smaller coefficient of thermal expansion at positions closer to the metal bumps B. When the wiring substrate 11 is produced, the insulating layers 1131 and 1132 are bonded together, and then are heated to the curing temperature of the wiring substrate 11” – a heated resin is a polymer) coated on the woven glass fabric (113a).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the substrate and woven structure as taught by Aoki into Li and Sunohara.
An ordinary artisan would have been motivated to use the known technique of Aoki in the manner set forth above to produce the predictable result as stated above in claim 2.
Regarding claim 9, Li as modified by Sunohara and Aoki, teaches claim 8 from which claim 9 depends. Li further teaches
wherein the electrical circuit device (126(4)) is an integrated passive
device ([0003] – “a passive electrical device such as a deep trench capacitor (DTC) may be embedded”), and wherein the electrical circuit device (126(4)) is electrically connected to the integrated circuit package component (102 – Fig. 1 – [0027] – “IC package 102”).
Regarding claim 11, Li as modified by Sunohara and Aoki, teaches claim 8 from which claim 11 depends. Li and Aoki do not expressly disclose the other limitations of claim 11.
However, in an analogous art, Sunohara teaches
wherein the polymer base ([8:36-43] – “a gap is provided between the inner
wall of the cavity 30 and the embedded electronic component 32 in order to facilitate accommodation of the electronic component 32. However, the gap is filled in with resin of the insulating layer 34 when a thermal hardening process is performed on the insulating layer 34A of the buildup layer 34 so that a void may not be created at the cavity 30” – a heated resin is a polymer) comprises a first material ([8:39] – “resin of the insulating layer 34” – hereinafter ‘FMR’) and wherein the first material (FMR) extends on a sidewall of the electrical circuit device (32 – Fig. 8 – [4:58] – “an embedded electronic component 32” – Fig. 7 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the polymer base structure as taught by Sunohara into and Aoki.
An ordinary artisan would have been motivated to use the known technique of Sunohara in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 13, Li as modified by Sunohara and Aoki, teaches claim 8 from which claim 13 depends. Li further teaches
further comprising:
a solder resist layer (Fig. 2A annotated, see below – {412 – Fig. 4H – [0057] –
“solder resist layer 412” – only discussed on the first side of the substrate but solder balls, 118 – [0028] – “external metal interconnects 118 (e.g., ball grid array (BGA) interconnects” are also on the second side of the substrate) on a second side (Fig. 2A annotated, see below, hereinafter ‘2S’) of the package substrate (208 – Fig. 2A – [0053] – “package substrate 208”), wherein the second side (2S) is opposite to the first side (Fig. 2A annotated, see below, hereinafter ‘1S’); and
external connectors (118 – [0028] – “external metal interconnects 118 (e.g., ball grid array (BGA) interconnects”) extending through the solder resist layer (412), wherein the external connectors (118) are physically and electrically connected the conductive features (130 – Fig. 1 shows this).
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Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Sunohara and Luan (US 20120074592 A1 – hereinafter Luan).
Regarding claim 5, Li as modified by Sunohara, teaches claim 1 from which claim 5 depends. Li and Sunohara do not expressly disclose the limitations of claim 5.
However, in an analogous art, Luan teaches
wherein the polymer base comprises resin ([0011] – “woven strands are
fiberglass and the polymer material is an epoxy” – epoxy is a resin).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the polymer base structure as taught by Luan into Li and Sunohara.
An ordinary artisan would have been motivated to use the known technique of Luan in the manner set forth above to produce the predictable result of [0016] – “the package can be made thin and yet strong. The package is also resistant to brittle fracture and outperforms equivalent packages in drop tests and mechanical load tests. Circuits packaged according to the method are better able to withstand drops, as occurs with portable electronic devices.”
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Sunohara and Yu et al. (US 20220352109 A1 – hereinafter Yu).
Regarding claim 7, Li as modified by Sunohara, teaches claim 1 from which claim 7 depends. Li and Sunohara do not expressly disclose the limitations of claim 7.
However, in an analogous art, Yu teaches
further comprising an underfill (136 – Fig. 7 – [0040] – “underfill 136 is filled
between the first and second semiconductor dies 120, 130 and the redistribution layer 110”) extending between the integrated circuit package component (120 – Fig. 7 – [0040] – “first and second semiconductor dies 120, 130 and the redistribution layer 110”) and package substrate (200 – Fig. 7 – [0035] – “substrate 200”), wherein the plurality of routing layers (110 – Fig. 7 – [0040] – “redistribution layer 110” – this is a plurality of layers) are in contact with the underfill (136 – Fig. 7 shows).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the underfill structure as taught by Yu into Li and Sunohara.
An ordinary artisan would have been motivated to use the known technique of Yu in the manner set forth above to produce the predictable result of [0033] – “the underfill 240 filled between the structure JS and the circuit substrate 200 can protect the fused connectors 210 against thermal or physical stresses and further secure the bonding of the structure JS with the circuit substrate 200.”
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Sunohara, Aoki, and Yu.
Regarding claim 10, Li as modified by Sunohara and Aoki, teaches claim 8 from which claim 10 depends. Li, Sunohara, and Aoki do not expressly disclose the limitations of claim 10.
However, in an analogous art, Yu teaches
further comprising an underfill (136 – Fig. 7 – [0040] – “underfill 136 is filled
between the first and second semiconductor dies 120, 130 and the redistribution layer 110”) extending between the integrated circuit package component (120 – Fig. 7 – [0040] – “first and second semiconductor dies 120, 130 and the redistribution layer 110”) and package substrate (200 – Fig. 7 – [0035] – “substrate 200”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the underfill structure as taught by Yu into Li, Sunohara, and Aoki.
An ordinary artisan would have been motivated to use the known technique of Yu in the manner set forth above to produce the predictable result of as stated above in claim 7.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Sunohara, Aoki, and Luan.
Regarding claim 12, Li as modified by Sunohara and Aoki, teaches claim 8 from which claim 12 depends. Li and Aoki do not expressly disclose the limitations of claim 12.
However, in an analogous art, Sunohara teaches
wherein each of the insulating layers (17A – Fig. 8 – [38 =6:11-12 ] – “buildup
layers 17 and 18, first, insulating layers 17A and 18A”) further comprises fillers embedded in the polymer base.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the insulating layer structure as taught by Sunohara into and Aoki.
An ordinary artisan would have been motivated to use the known technique of Sunohara in the manner set forth above to produce the predictable result as stated above in claim 1.
Li, Sunohara, and Aoki do not expressly disclose the other limitations of claim 10.
However, in an analogous art, Luan teaches
fillers (76 – Fig. 3 – [0033] – “the composite material base 32 which has a plurality of fiber bundles 76 that are woven together”) embedded in the polymer base ([0035] – “the woven bundles 76 of fibers 78 are placed between two polymer sheets and heated to form the support material”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the filler and polymer base structure as taught by Luan into Li and Sunohara.
An ordinary artisan would have been motivated to use the known technique of Luan in the manner set forth above to produce the predictable result of as stated above in claim 5.
Claims 14, 15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Sunohara, Aoki, and Chang et al. (US 20150041969 A1 – hereinafter Chang).
Regarding independent claim 14, Li teaches:
A method of manufacturing a semiconductor package (100 – Fig. 1 –
[0027] – “IC package 100”), the method comprising:
forming a package substrate (108 – Fig. 1 – [0027] – “first and second routing substrates 108(1), 108(2) as substrates 108(1), 108(2)” – hereinafter ‘108’), forming the package substrate (108) comprising:
forming a first plurality of insulating layers on a carrier, wherein each of the first plurality of insulating layers comprises a woven glass fabric and a polymer base coated on the woven glass fabric;
forming a first plurality of conductive features extending through the first plurality of insulating layers;
forming a cavity in the first plurality of insulating layers by laser drilling;
placing an electrical circuit device in the cavity;
forming a second plurality of insulating layers on the electrical
circuit device and the first plurality of insulating layers, wherein each of the second plurality of insulating layers comprises the woven glass fabric and the polymer base coated on the woven glass fabric;
forming a second plurality of conductive features extending through the second plurality of insulating layers; and
removing the carrier.
Li does not expressly disclose the other limitations of claim 14.
However, in an analogous art, Sunohara teaches
forming a first plurality of insulating layers (17A – Fig. 8 – [6:11-12 ] – “buildup layers 17 and 18, first, insulating layers 17A and 18A”),
forming a first plurality of conductive features (14 – Fig. 8 – [11:3-4] – “wirings 14”) extending through the first plurality of insulating layers (17A – Fig. 8 – [6:11-12 ] – “buildup layers 17 and 18, first, insulating layers 17A and 18A”);
forming a cavity (30 – Fig. 6 – (suno ([8:37] – “the cavity 30”) in the first plurality of insulating layers (17A) by laser drilling ([2:48-50] – “the cavity formation step includes forming the cavity through laser processing”);
placing an electrical circuit device (32 – Fig. 8 – [4:58] – “an embedded electronic component 32” – Fig. 7 shows this) in the cavity (30 – Fig. 7 shows this);
forming a second plurality of insulating layers (34A – Fig. 8 – [5:1-2] – “insulating layers 17A, 18A, 23A, 24A, 34A, 35A”) on the electrical
circuit device (32) and the first plurality of insulating layers (17A), wherein each of the second plurality of insulating layers (34A) comprises the woven glass fabric and the polymer base coated on the woven glass fabric;
forming a second plurality of conductive features (34B – Fig. 8 – [5:2] – “vias 17B, 18B, 23B, 24B, 34B, 35B”) extending through the second plurality of insulating layers (34A).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the insulating layers and cavity feature structure as taught by Sunohara into Li.
An ordinary artisan would have been motivated to use the known technique of Sunohara in the manner set forth above to produce the predictable result as stated above in claim 1.
Li and Sunohara do not expressly disclose the other limitations of claim 14.
However, in an analogous art, Aoki teaches
wherein each of the first plurality of insulating layers ([0039] – “The insulating layers 113) comprises a woven glass fabric (113a – Fig. 2 – [0040] – “Each insulating layer 113 includes the glass woven fabric 113a. The glass woven fabric 113a is a woven fabric of glass fibers. The glass woven fabric 113a contains a resin. Thus, each insulating layer 113 is formed by impregnating the glass woven fabric 113a with a resin”) and a polymer base ([0083] – “The glass fibers GF1 and GF2 in the glass woven fabric 113a of the insulating layer 1131 are S-glass, for example. The glass fibers GF1 and GF2 in the glass woven fabric 113a of the insulating layer 1132 are E-glass, for example. In such a case, the wiring substrate 11 has a higher coefficient of thermal expansion at positions closer to the semiconductor chips CH1, and has a smaller coefficient of thermal expansion at positions closer to the metal bumps B. When the wiring substrate 11 is produced, the insulating layers 1131 and 1132 are bonded together, and then are heated to the curing temperature of the wiring substrate 11” – a heated resin is a polymer, hereinafter ‘PB’) coated on the woven glass fabric ([0083] – “The glass fibers GF1 and GF2 in the glass woven fabric 113a of the insulating layer 1131 are S-glass, for example. The glass fibers GF1 and GF2 in the glass woven fabric 113 a of the insulating layer 1132 are E-glass, for example. In such a case, the wiring substrate 11 has a higher coefficient of thermal expansion at positions closer to the semiconductor chips CH1, and has a smaller coefficient of thermal expansion at positions closer to the metal bumps B. When the wiring substrate 11 is produced, the insulating layers 1131 and 1132 are bonded together, and then are heated to the curing temperature of the wiring substrate 11” – a heated resin is a polymer);
the woven glass fabric (113a) and the polymer base (PB) coated on the woven glass fabric (113a).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the substrate and woven structure as taught by Aoki into Li and Sunohara.
An ordinary artisan would have been motivated to use the known technique of Aoki in the manner set forth above to produce the predictable result as stated above in claim 2.
Li, Sunohara, and Aoki do not expressly disclose the other limitations of claim 14.
However, in an analogous art, Chang teaches
forming a first plurality of insulating layers on a carrier (20 – Fig. 2D –
[0055] – “the carrier 20 is removed”),
removing the carrier (20 – Fig. 2D – [0055] – “the carrier 20 is removed”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the carrier structure as taught by Chang into Li, Sunohara, and Aoki.
An ordinary artisan would have been motivated to use the known technique of Chang in the manner set forth above to produce the predictable result of [0006] – “If the semiconductor chip 12 is directly disposed on the packaging substrate 14, joints formed between the solder bumps 121 of the semiconductor chip 12 and the bonding pads 140 of the packaging substrate 14 can be adversely affected by a big CTE (Coefficient of Thermal Expansion) mismatch between the semiconductor chip 12 and the packaging substrate 14, thus easily resulting in delamination of the solder bumps 121 from the packaging substrate 14. Further, the CTE mismatch between the semiconductor chip 12 and the packaging substrate 14 induces more thermal stresses and leads to more serious warpages, thereby reducing the reliability of electrical connection between the semiconductor chip 12 and the packaging substrate 14 and even resulting in failure of a reliability test.”
Regarding claim 15, Li as modified by Sunohara, Aoki, and Chang, teaches claim 14 from which claim 15 depends. Li, Aoki, and Chang do not expressly disclose the limitations of claim 15.
However, in an analogous art, Sunohara teaches
wherein the second plurality of conductive features (34A) are physically
and electrically connected to the electrical circuit device (32) and the first plurality of conductive features (34A – Fig. 8 shows this), and wherein the electrical circuit device (32) is physically and electrically isolated from the first plurality of conductive features (34A) before forming the second plurality of conductive features (34A – Fig. 7 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second conductive features structure as taught by Sunohara into Li, Aoki, and Chang.
An ordinary artisan would have been motivated to use the known technique of Sunohara in the manner set forth above to produce the predictable result as stated above in claim 1.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 17, Li as modified by Sunohara, Aoki, and Chang, teaches claim 14 from which claim 17 depends. Li, Aoki, and Chang do not expressly disclose the limitations of claim 17.
However, in an analogous art, Sunohara teaches
wherein forming the second plurality of insulating layers (34A) comprises
placing a first insulating layer (34A) of the second plurality of insulating layers (34A) over the electrical circuit device (32) and melting the polymer base ([8:36-43] – “a gap is provided between the inner wall of the cavity 30 and the embedded electronic component 32 in order to facilitate accommodation of the electronic component 32. However, the gap is filled in with resin of the insulating layer 34 when a thermal hardening process is performed on the insulating layer 34A of the buildup layer 34 so that a void may not be created at the cavity 30” – a heated resin is a polymer, hereinafter ‘PB’) of the first insulating layer (34A), and wherein a portion of the polymer base (PB) of the first insulating layer (34A) fills in a gap between the electrical circuit device (32) and a sidewall of the cavity (30) after melting the polymer base of the first insulating layer ([8:36-43] – “a gap is provided between the inner wall of the cavity 30 and the embedded electronic component 32 in order to facilitate accommodation of the electronic component 32. However, the gap is filled in with resin of the insulating layer 34 when a thermal hardening process is performed on the insulating layer 34A of the buildup layer 34 so that a void may not be created at the cavity 30”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the insulating layer and cavity structure as taught by Sunohara into Li, Aoki, and Chang.
An ordinary artisan would have been motivated to use the known technique of Sunohara in the manner set forth above to produce the predictable result as stated above in claim 1.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Sunohara, Aoki, Chang, and Lee et al. (US 20210233859 A1 – hereinafter Lee).
Regarding claim 16, Li as modified by Sunohara, Aoki, and Chang, teaches claim 14 from which claim 16 depends. Li further teaches
wherein forming the first plurality of conductive
features (130(2)(4) – Fig. 9 – [0056] – “”Metal interconnects 130(2) are patterned in the first, second, and third metallization layers 125(1)-125(3) to provide signal routing paths) comprises forming a first opening (204(4) – Fig. 7 – [0040] – “openings 204(2)(3), 204(3)(2), 204(4)(1) are formed through the respective second, third, and fourth third core layers 110(2)-110(4)”) in a first insulating layer ([0029] – “lower metallization structure 122(2) is a structure that includes one or more metallization layers 125 that include one or more metal layers insulated by insulating layers” – not labeled in Fig. 7, hereinafter ‘IL’) of the first plurality of insulating layers (IL) by laser drilling and forming a first conductive via (813(4) – Fig. 8 – [0065] – “fourth metal interconnects 813(4) (e.g., vias, metal traces, metal lines)”) of the first plurality of conductive features (130(2)(4)) in the first opening (204(4)), wherein the first opening (204(4)) exposes a first conductive line (125 – Fig. 7 – [0029] – “lower metallization structure 122(2) is a structure that includes one or more metallization layers 125 that include one or more metal layers insulated by insulating layers”) of the first plurality of conductive features (130(2)(4)), and wherein the first conductive via (813(4) is physically and electrically connected to the first conductive line (125).
Li, Sunohara, Aoki, and Chang do not expressly disclose the other limitations of claim 17.
However, in an analogous art, Lee teaches
by laser drilling ([0061] – “partially removing the lower solder resist layer 130a of the back-side wiring substrate 100 using a light exposure process, a CO.sub.2 laser, or the like, thereby exposing the lower back-side wiring layer 115a” – this describes laser drilling to create openings).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the laser drilling as taught by Lee into Li, Sunohara, Aoki, and Chang.
An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable result to form the openings.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Sunohara, Aoki, Chang, and Luan.
Regarding claim 18, Li as modified by Sunohara, Aoki, and Chang, teaches claim 14 from which claim 18 depends. Li, Aoki, and Chang do not expressly disclose the limitations of claim 18.
However, in an analogous art, Sunohara teaches
wherein each of the first plurality of insulating layers (17A – Fig. 8 – [6:11-
12] – “buildup layers 17 and 18, first, insulating layers 17A and 18A”) further comprises fillers embedded in the polymer base.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the insulating layer structure as taught by Sunohara into Li, Aoki, and Chang.
An ordinary artisan would have been motivated to use the known technique of Sunohara in the manner set forth above to produce the predictable result as stated above in claim 1.
Li, Aoki, Chang, and Sunohara do not expressly disclose the other limitations of claim 18.
However, in an analogous art, Luan teaches
fillers (76 – Fig. 3 – [0033] – “the composite material base 32 which has a plurality of fiber bundles 76 that are woven together”) embedded in the polymer base ([0035] – “the woven bundles 76 of fibers 78 are placed between two polymer sheets and heated to form the support material”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the filler and polymer base structure as taught by Luan into Li, Aoki, Chang, and Sunohara.
An ordinary artisan would have been motivated to use the known technique of Luan in the manner set forth above to produce the predictable result of as stated above in claim 5.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Sunohara, Aoki, Chang, and Lim et al. (US 10049950 B2 – hereinafter Lim).
Regarding claim 19, Li as modified by Sunohara, Aoki, and Chang, teaches claim 14 from which claim 19 depends. Li, Sunohara, Aoki, and Chang do not expressly disclose the limitations of claim 19.
However, in an analogous art, Lim teaches
wherein removing the carrier (110 – Fig. 8 – [4:45-46] – ” the carrier 110
is partially sacrificed and removed”) comprises cutting off a seal ring (110b – Fig. 8 – [4:45-47] – “the carrier 110 is partially sacrificed and removed, for example by etching, so that a ring 110b remains”) on the carrier (110) encircling the electrical circuit device in a top-down view (Fig. 8 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the carrier and seal ring structure as taught by Lim into Li, Sunohara, Aoki, and Chang.
An ordinary artisan would have been motivated to use the known technique of Lim in the manner set forth above to produce the predictable result [1:30-33] – “the patterned conductor layouts are electrically isolated from each other, whereas on a conventional leadframe, each conductor layout corresponding to each die is electrically connected to an adjacent layout.”
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Sunohara, Aoki, Chang, and Yu.
Regarding claim 20, Li as modified by Sunohara, Aoki, and Chang, teaches claim 14 from which claim 20 depends. Li further teaches
further comprising:
bonding the package substrate (108) to an integrated circuit package
component (102 – Fig. 1 – [0027] – “IC package 102”), wherein the integrated circuit package component (102) comprises a semiconductor die (104(2) – Fig. 1 – [0027] – “IC package 102 that includes first, second, and third semiconductor dies (“dies”) 104(1), 104(2), 104(3)”); and
forming underfill between the integrated circuit package component and package substrate, wherein the underfill is in contact with the first plurality of insulating layers.
Li, Sunohara, Aoki, and Chang do not expressly disclose the other limitations of claim 20.
However, in an analogous art, Yu teaches
forming underfill (136 – Fig. 7 – [0040] – “underfill 136 is filled between the first and second semiconductor dies 120, 130 and the redistribution layer 110”) between the integrated circuit package component (120 – Fig. 7 – [0040] – “first and second semiconductor dies 120, 130 and the redistribution layer 110”) and package substrate (200 – Fig. 7 – [0035] – “substrate 200”), wherein the underfill (136) is in contact with the first plurality of insulating layers (110 – Fig. 7 – [0040] – “redistribution layer 110” – this is a plurality of layers – Fig. 7 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the underfill structure as taught by Yu into Li, Sunohara, Aoki, and Chang.
An ordinary artisan would have been motivated to use the known technique of Yu in the manner set forth above to produce the predictable result of as stated above in claim 7.
Conclusion
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897