DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/04/2026 has been entered.
Response to Amendments
Applicant's response of 08/04/2026 has been acknowledged. Claims 1 and 14 have been amended. No new matter has been added.
This office action considers claims 1-20 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant's arguments of 08/04/2026 with respect to the rejections of claims have
been fully considered, and are persuasive. Therefore, the rejection of claims 1-18, and 20-21 have been withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
In reference to claim 3, the claim requires “wherein the 30% or more of the
plurality of routing layers with the woven glass fabric is consecutive routing layers on a second side of the package substrate, and wherein the second side is opposite to the first side.”
It is unclear where the first side and second side areas begin and end regarding the routing layers.
Prior art known at the effective filing date of the claimed invention, disclose routing layers containing woven glass fabric along with first side and second side of a substrate.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is that the substrate contains routing layers and that 30% or more of the routing layers near the second side of the substrate contain woven glass fabric.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. (US 20240172368 A1 – hereinafter Ji) in view of Seo et al. (US 20250140676 A1 – hereinafter Seo) and Tanaka (US 20090244865 A1 – hereinafter Tanaka).
Regarding independent claim 1, Ji teaches
(Currently Amended) A semiconductor package (not labeled) (500D –
Fig. 22 – [0068] – “printed circuit board 500D”) comprising:
an integrated circuit package component (310 – Fig. 22 – [0035] –
“semiconductor chip 310”), wherein the integrated circuit package component comprises (500D) a semiconductor die (310 – the package component is a chip); and
a package substrate (100 – Fig. 22 – [0043] – “board unit 100” – this corresponds to a package substrate) physically and electrically connected to the integrated circuit package component (500D) on a first side of the package substrate (100 – Fig. 22 shows this), the package substrate (100) comprising:
a plurality of routing layers (110 – Fig. 22 – [0044] – “board unit 110” – this corresponds to a routing layer in which there is a plurality), each of the plurality of routing layers (110) comprising:
an insulating layer (111 – Fig. 22 – [0044] – “insulating layers 111”), the insulating layer (111) comprising a polymer base ([0045] – “insulating layer 111 may include an insulating material, and the insulating material may use an insulating resin such as a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide, a material in which this resin is mixed with an inorganic filler such as silica, a resin impregnated into a core material such as a glass fiber (i.e., glass fiber, glass cloth or glass fabric) together with the inorganic filler, for example, Ajinomoto build-up film (ABF), prepreg, or the like, and is not limited thereto”); and
conductive features (113 – Fig. 22 – [0047] – “via layer 113”) extending through the insulating layer (111 – Fig. 22 shows this); and
an electrical circuit device (210 – Fig. 22 – [0052] – “first and second passive devices 210 and 220 may be chip-type components such as inductors and capacitors, may be the integrated passive devices (IPDs), and are not limited thereto”) embedded in the plurality of routing layers (110), wherein the electrical circuit device (210) is electrically connected to the integrated circuit package component (500D) by the conductive features (113) of the plurality of routing layers (110), wherein a first insulating layer of the plurality of routing layers interfaces the electrical circuit device, wherein a first conductive via of the conductive features extends through the first insulating layer to the electrical circuit device, wherein a second conductive via of the conductive features extends through the first insulating layer, [[and]] wherein the first conductive via (60 – Fig. 11 – [0035] – “via-hole 60”) has a greater height than the second conductive via (Fig. 11 annotated, see below – hereinafter ’60-2’, Fig. 11 annotated shows element 60 has a height greater than element 60-2), and wherein an interface between the electrical circuit device and the first conductive via is level with a top surface of the first insulating layer.
Ji does not expressly disclose the limitations of claim 1.
However, in an analogous art, Seo teaches
wherein a first insulating layer (111A – Fig. 25 – [0081] – “first insulating layer 111A”) of the plurality of routing layers (112 – Fig. 25 – [0081] – “redistribution layer 112”) interfaces the electrical circuit device (130 – Fig. 14 – [0080] – “a semiconductor chip 130”), wherein a first conductive via (113A – Fig. 14 – [0081] – “first via 113A”) of the conductive features (113 – Fig. 25 – [0081] – “via 113”) extends through the first insulating layer (111A) to the electrical circuit device (130), wherein a second conductive via (112A – Fig. 25 – [0092] – “first redistribution layer 112A” – this corresponds to the conductive via) of the conductive features (112) extends through the first insulating layer (111A),
wherein an interface between the electrical circuit device (130) and the first conductive via (113A) is level with a top surface of the first insulating layer (111A – Fig. 24 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the layer structure as taught by Seo into Ji.
An ordinary artisan would have been motivated to use the known technique of Seo in the manner set forth above to produce the predictable result of [0005] – “provide wiring structures capable of implementing a fine pitch and thereby increasing a degree of freedom of wiring, and semiconductor packages to which the wiring structure is applied.”
Ji and Seo do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Tanaka teaches
wherein the first conductive via (60 – Fig. 11 – [0035] – “via-hole 60”) has a greater height than the second conductive via (Fig. 11 annotated, see below – hereinafter ’60-2’, Fig. 11 annotated shows element 60 has a height greater than element 60-2).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive feature height structure as taught by Tanaka into Ji and Seo.
An ordinary artisan would have been motivated to use the known technique of Tanaka in the manner set forth above to produce the predictable result of [0003] – “a method for manufacturing a build-up multilayer printed wiring board, and more particularly to a method for manufacturing a multilayer printed wiring board having electronic components such as active devices such as an IC chip and passive devices such as a chip capacitor built therein.”
Regarding claim 6, Ji, as modified by Seo and Tanaka, teaches claim 1 from which claim 6 depends. Ji further teaches
the integrated circuit package component (500D).
Ji and Tanaka do not expressly disclose the other limitations of claim 6.
However, in an analogous art, Seo teaches
(Previously Presented) The semiconductor package of claim 1, wherein the
first conductive via (113A) of the conductive features (113) of the plurality of routing layers (112) is physically and electrically connected to the electrical circuit device (130), and wherein the electrical circuit device (130) is between the first conductive via (113A) and the integrated circuit package component (500D).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the layer structure as taught by Seo into Ji and Tanaka.
An ordinary artisan would have been motivated to use the known technique of Seo in the manner set forth above to produce the predictable result as stated above in claim 1.
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Ji in view of Seo, Tanaka, and Aoki et al. (US 20220246516 A1 – hereinafter Aoki).
Regarding claim 2, Ji, as modified by Seo and Tanaka, teaches claim 1 from which claim 2 depends. Ji, Seo and Tanaka do not expressly disclose the other limitations of claim 2.
However, in an analogous art, Aoki teaches
(Original) The semiconductor package of claim 1, wherein 30% or more
([0039] – “The insulating layers 113 are provided in contact with the wire layers L1 to L3 in the direction of the normal to the substrate surface of the wiring substrate 11, and each insulating layer 113 includes a glass woven fabric 113 a containing a resin” – each layer means every layer which is 30% or more of the layers – hereinafter ‘30%’) of the plurality of routing layers ([0039] – “The insulating layers 113 are provided in contact with the wire layers L1 to L3” – these correspond to routing layers – hereinafter ‘RL’) each comprises a woven glass fabric (113a – Fig. 2 – [0040] – “Each insulating layer 113 includes the glass woven fabric 113a. The glass woven fabric 113a is a woven fabric of glass fibers. The glass woven fabric 113a contains a resin. Thus, each insulating layer 113 is formed by impregnating the glass woven fabric 113a with a resin”) embedded in the polymer base ([0083] – “The glass fibers GF1 and GF2 in the glass woven fabric 113 a of the insulating layer 1131 are S-glass, for example. The glass fibers GF1 and GF2 in the glass woven fabric 113 a of the insulating layer 1132 are E-glass, for example. In such a case, the wiring substrate 11 has a higher coefficient of thermal expansion at positions closer to the semiconductor chips CH1, and has a smaller coefficient of thermal expansion at positions closer to the metal bumps B. When the wiring substrate 11 is produced, the insulating layers 1131 and 1132 are bonded together, and then are heated to the curing temperature of the wiring substrate 11” – a heated resin is a polymer) of the corresponding insulating layer ([0039] – “The insulating layers 113).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the routing layers and woven structure as taught by Aoki into Ji, Seo and Tanaka.
An ordinary artisan would have been motivated to use the known technique of Aoki in the manner set forth above to produce the predictable result of preventing [0004] – “a substrate (i.e., the package) warps due to the difference in the coefficient of thermal expansion between silicon (Si) of a memory chip and the substrate.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 3, Ji, as modified by Seo, Tanaka, and Aoki, teaches claim 2 from which claim 3 depends. Ji further teaches
(Previously Presented) The semiconductor package of claim 2,
wherein the 30% or more of the plurality of routing layers (110) with the woven glass fabric is consecutive routing layers (110) on a second side of the package substrate (100), and wherein the second side is opposite to the first side (Fig. 22 shows this).
Ji, Seo and Tanaka do not expressly disclose the other limitations of claim 3.
However, in an analogous art, Aoki teaches
woven glass fabric (113a).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the woven structure as taught by Aoki into Ji, Seo and Tanaka.
An ordinary artisan would have been motivated to use the known technique of Aoki in the manner set forth above to produce the predictable result as stated above in claim 2.
Regarding claim 4, Ji, as modified by Seo, Tanaka, and Aoki, teaches claim 2 from which claim 4 depends. Ji further teaches
(Previously Presented) The semiconductor package of claim 2,
wherein the electrical circuit device (210) extends through one or more of the plurality of routing layers (110) with the woven glass fabric (113a).
Ji, Seo and Tanaka do not expressly disclose the other limitations of claim 4.
However, in an analogous art, Aoki teaches
woven glass fabric (113a).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the woven structure as taught by Aoki into Ji, Seo and Tanaka.
An ordinary artisan would have been motivated to use the known technique of Aoki in the manner set forth above to produce the predictable result as stated above in claim 2.
Regarding claim 5, Ji, as modified by Seo and Tanaka, teaches claim 1 from which claim 5 depends. Ji, Seo and Tanaka do not expressly disclose the other limitations of claim 5.
However, in an analogous art, Aoki teaches
(Original) The semiconductor package of claim 1, wherein the polymer base
(60A) comprises resin ([0083] – “The glass fibers GF1 and GF2 in the glass woven fabric 113 a of the insulating layer 1131 are S-glass, for example. The glass fibers GF1 and GF2 in the glass woven fabric 113 a of the insulating layer 1132 are E-glass, for example. In such a case, the wiring substrate 11 has a higher coefficient of thermal expansion at positions closer to the semiconductor chips CH1, and has a smaller coefficient of thermal expansion at positions closer to the metal bumps B. When the wiring substrate 11 is produced, the insulating layers 1131 and 1132 are bonded together, and then are heated to the curing temperature of the wiring substrate 11” – a heated resin is a polymer).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the woven structure as taught by Aoki into Ji, Seo and Tanaka.
An ordinary artisan would have been motivated to use the known technique of Aoki in the manner set forth above to produce the predictable result as stated above in claim 2.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ji in view of Seo, Tanaka, and Yu et al. (US 20220352109 A1 – hereinafter Yu).
Regarding claim 7, Ji, as modified by Seo and Tanaka, teaches claim 1 from which claim 7 depends. Ji, Seo, and Tanaka do not expressly disclose the other limitations of claim 7.
However, in an analogous art, Yu teaches
(Previously Presented) The semiconductor package of claim 1, further
comprising an underfill (136 – Fig. 7 – [0040] – “underfill 136 is filled between the first and second semiconductor dies 120, 130 and the redistribution layer 110”) extending between the integrated circuit package component (120 – Fig. 7 – [0040] – “first and second semiconductor dies 120, 130 and the redistribution layer 110”) and the package substrate (200 – Fig. 7 – [0035] – “substrate 200”), wherein the plurality of routing layers (110 – Fig. 7 – [0040] – “redistribution layer 110” – this is a plurality of layers) is in contact with the underfill (136 – Fig. 7 shows).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the underfill structure as taught by Yu into Ji, Seo, and Tanaka.
An ordinary artisan would have been motivated to use the known technique of Yu in the manner set forth above to produce the predictable result of [0033] – “the underfill 240 filled between the structure JS and the circuit substrate 200 can protect the fused connectors 210 against thermal or physical stresses and further secure the bonding of the structure JS with the circuit substrate 200.”
Claims 8-13 rejected under 35 U.S.C. 103 as being unpatentable over Ji in view of Aoki, Sunohara et al. (US 7727802 B2 – hereinafter Sunohara), and Nakamura et al. (US 20110169164 A1 – hereinafter Nakamura).
Regarding independent claim 8, Ji teaches
(Previously Presented) A semiconductor package (500D – Fig. 22 –
[0068] – “printed circuit board 500D”) comprising:
an integrated circuit package component (310 – Fig. 22 – [0035] –
“semiconductor chip 310”), wherein the integrated circuit package component comprises (500D) a semiconductor die (310 – the package component is a chip);
an underfill between the integrated circuit package component and a package substrate; and
the package substrate bonded to the integrated circuit package component on a first side of the package substrate, the package substrate comprising:
insulating layers, wherein each of the insulating layers comprises a woven glass fabric and a polymer base coated on the woven glass fabric;
conductive features (110 – Fig. 22 – [0041] – “insulating layers 111 and 121 included in the board unit 110”), wherein each of the conductive features (110) comprises a conductive line (112 – Fig. 22 – [0041] – “wiring layers 112”) between neighboring insulating layers (111 – Fig. 22 – [0044] – “insulating layers 111”) and a conductive via (113 – Fig. 22 – [0047] – “via layer 113”) extending through the corresponding insulating layer (111 – Fig. 22 shows this); and
an electrical circuit device, wherein a top surface of the electrical
circuit device is covered by a first insulating layer of the insulating layers and a bottom surface of the electrical circuit device (210 – Fig. 22 – [0052] – “first and second passive devices 210 and 220 may be chip-type components such as inductors and capacitors, may be the integrated passive devices (IPDs), and are not limited thereto”) is in contact with a second insulating layer (121 – Fig. 22 – [0041] – “insulating layers 121”) of the insulating layers (111 and 121 – Fig. 22 – [0041] – “insulating layers 111 and 121”), wherein the first insulating layer (111) is between the electrical circuit device (210) and the integrated circuit package component (310 – Fig. 22 – [0035] – “semiconductor chip 310”), and wherein a first conductive via (113) of the conductive features (110) extends through the second insulating layer (121) to physically and electrically connect to the electrical circuit device (210); and
a solder resist layer, wherein the insulating layers extend continuously from a bottom surface of the underfill to a top surface of the solder resist layer.
Ji does not expressly disclose the other limitations of claim 8.
However, in an analogous art, Sunohara teaches
an electrical circuit device (32 – Fig. 8 – [27 = 4:58] – “an embedded electronic
component 32”), wherein a top surface of the electrical circuit device (32) is covered by a first insulating layer (34A – Fig. 8 – [53 = ] – “buildup layer 34 includes an insulating film 34A, vias 34B, and a wiring layer 34C”) of the insulating layers (31 – fig. 8 – [53 = 6:20-23] – “first buildup layer laminated structure 31 (i.e., buildup layers 17 and 23)” – these are insulating layers).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the electric circuit device structure as taught by Sunohara into Ji.
An ordinary artisan would have been motivated to use the known technique of Sunohara in the manner set forth above to produce the predictable result of [0004] – “The substrate is designed to be included in an IC package to support a semiconductor die (“die”) and/or other circuits and to provide signal routing paths to the die and/or other circuits as a routing substrate.”
Ji and Sunohara do not expressly disclose the other limitations of claim 8.
However, in an analogous art, Aoki teaches
the package substrate (11 – Fig. 1 – [0027] – “wiring substrate 11”) comprising:
insulating layers (113 – Fig. 2 – [0039] – “The insulating layers 113 are provided in contact with the wire layers L1 to L3” – these correspond to routing layers – hereinafter ‘RL’), wherein each of the insulating layers (113) comprises a woven glass fabric (113a – Fig. 2 – [0040] – “Each insulating layer 113 includes the glass woven fabric 113a. The glass woven fabric 113a is a woven fabric of glass fibers. The glass woven fabric 113a contains a resin. Thus, each insulating layer 113 is formed by impregnating the glass woven fabric 113a with a resin”) and a polymer base ([0083] – “The glass fibers GF1 and GF2 in the glass woven fabric 113 a of the insulating layer 1131 are S-glass, for example. The glass fibers GF1 and GF2 in the glass woven fabric 113 a of the insulating layer 1132 are E-glass, for example. In such a case, the wiring substrate 11 has a higher coefficient of thermal expansion at positions closer to the semiconductor chips CH1, and has a smaller coefficient of thermal expansion at positions closer to the metal bumps B. When the wiring substrate 11 is produced, the insulating layers 1131 and 1132 are bonded together, and then are heated to the curing temperature of the wiring substrate 11” – a heated resin is a polymer) coated on the woven glass fabric (113a).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the substrate and woven structure as taught by Aoki into Ji and Sunohara.
An ordinary artisan would have been motivated to use the known technique of Aoki in the manner set forth above to produce the predictable result as stated above in claim 2.
Ji, Sunohara, and Aoki do not expressly disclose the other limitations of claim 8.
However, in an analogous art, Nakamura teaches
an underfill (158 fig 13) (nak (70 – Fig. 32 – [0168] – “underfill resin 70”) between the integrated circuit package component (50 – Fig. 32 – [0168] – “a semiconductor chip 50”) and a package substrate (nak( Fig. 32 annotated, see below – hereinafter ‘PS’); and
the package substrate (PS) bonded to the integrated circuit package component (50) on a first side of the package substrate (PS),
a solder resist layer (18 – Fig. 32 – [0097] – “solder resist layer 18”), wherein the insulating layers (12, 14, 16 – Fig. 32 – [0097 ] –“ first insulating layer 12 … second insulating layer 14 … third insulating layer 16”) extend continuously (Fig. 32 shows this) from a bottom surface of the underfill (70) to a top surface of the solder resist layer (18 – Fig. 32 shows this).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the underfill and solder resist structure as taught by Nakamura into Ji, Sunohara, and Aoki.
An ordinary artisan would have been motivated to use the known technique of Nakamura in the manner set forth above to produce the predictable result of [0022] – “wiring substrate having an easily recognizable alignment mark, a manufacturing method of the wiring substrate, and a semiconductor package having the wiring substrate on which various electronic components such as a semiconductor chip and a chip capacitor are installed.”
Regarding claim 9, Ji, as modified by Sunohara, Aoki, and Nakamura, teaches claim 8 from which claim 9 depends. Ji further teaches
(Original) The semiconductor package of claim 8, wherein the
electrical circuit device (210) is an integrated passive device ([0041] – “first passive device 210”), and wherein the electrical circuit device (210) is electrically connected to the integrated circuit package component (310 – [0041] – “the first and second electrical connection paths P1 and P2 may pass through the wiring layers 112 and 122 in the board units 110 and 120 and the semiconductor chip 310”).
Regarding claim 10, Ji, as modified by Sunohara, Aoki, and Nakamura, teaches claim 8 from which claim 10 depends. Ji, Sunohara, and Aoki do not expressly disclose the limitations of claim 10.
However, in an analogous art, Nakamura teaches
(Previously Presented) The semiconductor package of claim 8, wherein the
underfill (70) encircles and extends on a sidewall of the integrated circuit package component (50 – Fig. 32 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the underfill structure as taught by Nakamura into Ji, Sunohara, and Aoki.
An ordinary artisan would have been motivated to use the known technique of Nakamura in the manner set forth above to produce the predictable result as stated above in claim 8.
Regarding claim 11, Ji, as modified by Sunohara, Aoki, and Nakamura, teaches claim 8 from which claim 11 depends. Ji further teaches
(Original) The semiconductor package of claim 8, wherein the
polymer base ([0045] – “insulating layer 121 may include an insulating material, the insulating material may use the insulating resin such as a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide, the material in which this resin is mixed with the inorganic filler such as silica, the resin impregnated into a core material such as a glass fiber (i.e., glass fiber, glass cloth or glass fabric) together with the inorganic filler”) comprises a first material (the first material is interpreted as the resin of insulating layer 121 – hereinafter ‘FMR’) and wherein the first material (FMR) extends on a sidewall ([0049] – “At least one of the one or more second insulating layers 121 may cover at least a portion of the first passive device 210 and fill at least a portion of the first cavity C1”) of the electrical circuit device (210 – Fig. 22 shows this).
Regarding claim 12, Ji, as modified by Sunohara, Aoki, and Nakamura, teaches claim 8 from which claim 12 depends. Ji further teaches
(Original) The semiconductor package of claim 8, wherein each of
the insulating layers (121) further comprises fillers embedded in the polymer base ([0045] – “insulating layer 121 may include an insulating material, the insulating material may use the insulating resin such as a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide, the material in which this resin is mixed with the inorganic filler such as silica, the resin impregnated into a core material such as a glass fiber (i.e., glass fiber, glass cloth or glass fabric) together with the inorganic filler”).
Regarding claim 13, Ji, as modified by Sunohara, Aoki, and Nakamura, teaches claim 8 from which claim 13 depends. Ji, Sunohara, and Aoki do not expressly disclose the limitations of claim 13.
However, in an analogous art, Nakamura teaches
(Previously Presented) The semiconductor package of claim 8,
wherein external connectors (60 – Fig. 35 – [0168] – “solder bumps 60”) extend through the solder resist layer (18), and wherein the external connectors (60) are physically and electrically connected to the conductive features (13 – Fig. 35 – [0102] – “interconnection patterns 13” – Fig. 35 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the external connector structure as taught by Nakamura into Ji, Sunohara, and Aoki.
An ordinary artisan would have been motivated to use the known technique of Nakamura in the manner set forth above to produce the predictable result as stated above in claim 8.
Claims 14-16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ji in view of Aoki, Tanaka, and Jeong et al. (US 20240282685 A1 – hereinafter Jeong).
Regarding independent claim 14, Ji teaches
(Currently Amended) A method of manufacturing a semiconductor
package (500D – Fig. 22 – [0068] – “printed circuit board 500D”), the method
comprising:
forming a package substrate (100 – Fig. 22 – [0043] – “board unit 100” – this corresponds to a package substrate), forming the package substrate (100) comprising:
forming a first plurality of insulating layers (111 – Fig. 22 – [0044] – “insulating layers 111”) on a carrier (710 – Fig. 5 – [0061] – “the carrier board 710 may be removed”), wherein each of the first plurality of insulating layers comprises a woven glass fabric and a polymer base coated on the woven glass fabric;
forming a first plurality of conductive features (113 – Fig. 22 – [0047] – “via layer 113”) extending through the first plurality of insulating layers (111);
laser drilling a cavity in the first plurality of insulating layers to expose a top surface of an insulating layer of the first plurality of insulating layers;
placing an electrical circuit device (210 – Fig. 22 – [0052] – “first and second passive devices 210 and 220 may be chip-type components such as inductors and capacitors, may be the integrated passive devices (IPDs), and are not limited thereto”) in the cavity (C1 – Fig. 7 – [0058] – “first cavity C1”), wherein a bottom of the electrical circuit device directly contacts the top surface of the insulating layer of the first plurality of insulating layers that was exposed by the laser drilling;
forming a second plurality of insulating layers (121 – Fig. 22 – [0041] – “insulating layers 121”) on the electrical circuit device (210) and the first plurality of insulating layers (111), wherein each of the second plurality of insulating layers (121) comprises the woven glass fabric and the polymer base coated on the woven glass fabric;
forming a second plurality of conductive features (120 – Fig. 22 – [0060] – “the second board unit 120 may be formed on the first board unit 110 in the build-up process”) extending through the second plurality of insulating layers (121); and
removing the carrier (710 – [0061] – “the carrier board 710 may be removed”).
Ji does not expressly disclose the other limitations of claim 14.
However, in an analogous art, Aoki teaches
wherein each of the first plurality of insulating layers ([0039] – “The insulating layers 113) comprises a woven glass fabric (113a – Fig. 2 – [0040] – “Each insulating layer 113 includes the glass woven fabric 113a. The glass woven fabric 113a is a woven fabric of glass fibers. The glass woven fabric 113a contains a resin. Thus, each insulating layer 113 is formed by impregnating the glass woven fabric 113a with a resin”) and a polymer base ([0083] – “The glass fibers GF1 and GF2 in the glass woven fabric 113a of the insulating layer 1131 are S-glass, for example. The glass fibers GF1 and GF2 in the glass woven fabric 113a of the insulating layer 1132 are E-glass, for example. In such a case, the wiring substrate 11 has a higher coefficient of thermal expansion at positions closer to the semiconductor chips CH1, and has a smaller coefficient of thermal expansion at positions closer to the metal bumps B. When the wiring substrate 11 is produced, the insulating layers 1131 and 1132 are bonded together, and then are heated to the curing temperature of the wiring substrate 11” – a heated resin is a polymer, hereinafter ‘PB’) coated on the woven glass fabric ([0083] – “The glass fibers GF1 and GF2 in the glass woven fabric 113a of the insulating layer 1131 are S-glass, for example. The glass fibers GF1 and GF2 in the glass woven fabric 113 a of the insulating layer 1132 are E-glass, for example. In such a case, the wiring substrate 11 has a higher coefficient of thermal expansion at positions closer to the semiconductor chips CH1, and has a smaller coefficient of thermal expansion at positions closer to the metal bumps B. When the wiring substrate 11 is produced, the insulating layers 1131 and 1132 are bonded together, and then are heated to the curing temperature of the wiring substrate 11” – a heated resin is a polymer);
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate insulating layer structure as taught by Aoki into Ji.
An ordinary artisan would have been motivated to use the known technique of Aoki in the manner set forth above to produce the predictable result as stated above in claim 2.
Ji and Aoki do not expressly disclose the other limitations of claim 14.
However, in an analogous art, Tanaka teaches
wherein a bottom of the electrical circuit device (20 – Fig. 4(C) – [0031] – “IC chip 20”) directly contacts the top surface of the insulating layer (50 – Fig. 4(C) – [0031] – “interlayer resin insulation layer 50”) of the first plurality of insulating layers (30 – [0045] – “insulation resin substrate (core substrate) 30 composed of a one-surface-copper-bonded and laminate sheet, which is prepared by overlapping prepregs, each of which is composed of a core material such as a glass cloth impregnated with a resin such as epoxy and laminating the prepregs on one surface of a copper foil 26” – Fig. 4(C) shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive feature height structure as taught by Tanaka into Ji and Aoki.
An ordinary artisan would have been motivated to use the known technique of Tanaka in the manner set forth above to produce the predictable result as stated above in claim 1.
Ji, Aoki, and Tanaka do not expressly disclose the other limitations of claim 14.
However, in an analogous art, Jeong teaches
laser drilling ([0185] – “the laser process for forming the cavity 160”) a cavity (160 – Fig. 2a – [0166] – “cavity 160 may be formed in the second insulating layer 120”) in the first plurality of insulating layers (120 – Fig. 2a – [0166] – “cavity 160 may be formed in the second insulating layer 120”)
to expose a top surface ({[0241] – “a first pad portion 141a may be exposed in the cavity 160. In this case, the second-first insulating layer 121 may be disposed in a region other than the area where the first pad portion 141a is formed within the cavity 160”}, {[0096] – “insulating layer 120 may be included a second-first insulating layer 121”} – Fig. 2A shows this) of an insulating layer (120) of the first plurality of insulating layers ([0091] – “a first insulating layer 110, a second insulating layer 120, a third insulating layer 130” – this is a plurality);
that was exposed by the laser drilling ([0185] – “the laser process for forming the cavity 160”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the cavity structure as taught by Jeong into Ji, Aoki, and Tanaka.
An ordinary artisan would have been motivated to use the known technique of Jeong in the manner set forth above to produce the predictable result of [0014] – “a circuit board that provides a cavity without a stop layer and a package substrate including the same.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 15, Ji, as modified by Aoki, Tanaka, and Jeong, teaches claim 14 from which claim 15 depends. Ji further teaches
(Original)The method of claim 14, wherein the second plurality of
conductive features (120) are physically and electrically connected to the electrical circuit device (210) and the first plurality of conductive features (110), and wherein the electrical circuit device (210) is physically and electrically isolated from the first plurality of conductive features (110) before forming the second plurality of conductive features (120).
Regarding claim 16, Ji, as modified by Aoki, Tanaka, and Jeong, teaches claim 14 from which claim 16 depends. Ji further teaches
(Original) The method of claim 14, wherein forming the first plurality
of conductive features (110) comprises forming a first opening (C1) in a first insulating layer (111) of the first plurality of insulating layers (111) by laser drilling ([0058] – “The first cavity C1 may be formed using a blast method, is not limited thereto, and may be formed using a laser method or the like”) and forming a first conductive via (113 – Fig. 22 – [0047] – “via layer 113”) of the first plurality of conductive features (110) in the first opening (C1), wherein the first opening (C1) exposes a first conductive line (112 – Fig. 22 – [0046] – “wiring layer 112”) of the first plurality of conductive features (112), and wherein the first conductive via (113) is physically and electrically connected to the first conductive line (112 – Fig. 22 shows this).
Regarding claim 18, Ji, as modified by Aoki, Tanaka, and Jeong, teaches claim 14 from which claim 18 depends. Ji further teaches
(Original) The method of claim 14, wherein each of the first plurality
of insulating layers (121) further comprises fillers embedded in the polymer base ([0045] – “insulating layer 121 may include an insulating material, the insulating material may use the insulating resin such as a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide, the material in which this resin is mixed with the inorganic filler such as silica, the resin impregnated into a core material such as a glass fiber (i.e., glass fiber, glass cloth or glass fabric) together with the inorganic filler”).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Ji in view of Aoki, Tanaka, Jeong, and Sunohara.
Regarding claim 17, Ji, as modified by Aoki, Tanaka, and Jeong, teaches claim 14 from which claim 17 depends. Ji further teaches
(Original) The method of claim 14, wherein forming the second
plurality of insulating layers (121) comprises placing a first insulating layer (121) of the second plurality of insulating layers ([0045] – “insulating layer 121 may include an insulating material, the insulating material may use the insulating resin such as a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide, the material in which this resin is mixed with the inorganic filler such as silica, the resin impregnated into a core material such as a glass fiber (i.e., glass fiber, glass cloth or glass fabric) together with the inorganic filler”) over the electrical circuit device (210) and melting the polymer base ([0045] – “insulating layer 121 may include an insulating material, the insulating material may use the insulating resin such as a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide, the material in which this resin is mixed with the inorganic filler such as silica, the resin impregnated into a core material such as a glass fiber (i.e., glass fiber, glass cloth or glass fabric) together with the inorganic filler” – hereinafter ‘PB’) of the first insulating layer (111), and wherein a portion of the polymer base (PB) of the first insulating layer (111 is the first insulating layer however insulating layer 121 referes to the same process, Fig. 22 shows this) fills in a gap between the electrical circuit device (210) and a sidewall of the cavity (C1) after melting the polymer base (PB) of the first insulating layer (121 – [0049] – “At least one of the one or more second insulating layers 121 may cover at least a portion of the first passive device 210 and fill at least a portion of the first cavity C1”).
Ji, Aoki, Tanaka, and Jeong do not expressly disclose the other limitations of claim 17.
However, in an analogous art, Sunohara teaches
melting ([55 = 8:36-43] – “a gap is provided between the inner wall of the cavity 30 and the embedded electronic component 32 in order to facilitate accommodation of the electronic component 32. However, the gap is filled in with resin of the insulating layer 34 when a thermal hardening process is performed on the insulating layer 34A of the buildup layer 34 so that a void may not be created at the cavity 30”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the electric circuit device structure as taught by Sunohara into Ji, Aoki, Tanaka, and Jeong.
An ordinary artisan would have been motivated to use the known technique of Sunohara in the manner set forth above to produce the predictable result as stated above in claim 8.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Ji in view of Aoki, Tanaka, Jeong, and Lim et al. (US 10049950 B2 – hereinafter Lim).
Regarding claim 19, Ji as modified by Aoki, Tanaka, and Jeong, teaches claim 14 from which claim 19 depends. Ji, Aoki, Tanaka, and Jeong do not expressly disclose the limitations of claim 19.
However, in an analogous art, Lim teaches
(Original) The method of claim 14, wherein removing the carrier (110 – Fig.
8 – [4:45-46] – ” the carrier 110 is partially sacrificed and removed”) comprises cutting off a seal ring (110b – Fig. 8 – [4:45-47] – “the carrier 110 is partially sacrificed and removed, for example by etching, so that a ring 110b remains”) on the carrier (110) encircling the electrical circuit device in a top-down view (Fig. 8 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the carrier and seal ring structure as taught by Lim into Ji, Aoki, Tanaka, and Jeong.
An ordinary artisan would have been motivated to use the known technique of Lim in the manner set forth above to produce the predictable result [1:30-33] – “the patterned conductor layouts are electrically isolated from each other, whereas on a conventional lead frame, each conductor layout corresponding to each die is electrically connected to an adjacent layout.”
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ji in view of Aoki, Tanaka, Jeong, and Yu.
Regarding claim 20, Ji as modified by Aoki, Tanaka, and Jeong, teaches claim 14 from which claim 19 depends. Ji further teaches
(Previously Presented) The method of claim 14, further comprising:
bonding the package substrate (100) to an integrated circuit package
component (310), wherein the integrated circuit package component (310) comprises a semiconductor die (310 – the package component is a chip); and
forming an underfill between the integrated circuit package component and package substrate, wherein the underfill is in contact with the first plurality of insulating layers.
Ji, Aoki, Tanaka, and Jeong do not expressly disclose the other limitations of claim 20.
However, in an analogous art, Yu teaches
forming an underfill (136 – Fig. 7 – [0040] – “underfill 136 is filled between the first and second semiconductor dies 120, 130 and the redistribution layer 110”) between the integrated circuit package component (120 – Fig. 7 – [0040] – “first and second semiconductor dies 120, 130 and the redistribution layer 110”) and package substrate (200 – Fig. 7 – [0035] – “substrate 200”), wherein the underfill (136) is in contact with the first plurality of insulating layers (110 – Fig. 7 – [0040] – “redistribution layer 110” – this is a plurality of layers – Fig. 7 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the underfill structure as taught by Yu into Ji, Aoki, Tanaka, and Jeong.
An ordinary artisan would have been motivated to use the known technique of Yu in the manner set forth above to produce the predictable result of as stated above in claim 7.
Pertinent Art
For the benefits of the Applicant, US 20240355747 A1 and US 20120074592 A1 are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations the specific cavity insulation.
Conclusion
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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