DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-7 in the reply filed on 5/12/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, line 13 recites “a third power line extending in a second direction vertical to the first direction”. Vertical means “positioned up and down rather than side to side; going straight up” (definition taken from Merriam Webster on 7/25/2026) and is thus and absolute and not a relative direction. Thus the statement “vertical to the first direction” does not make sense. This issue renders the claim indefinite. For the purposes of examination, the examiner will interpret the limitation as “a third power line extending in a second direction perpendicular to the first direction”.
Claim 5, line 13 recites “a third power line extending in a second direction vertical to the first direction”. Vertical means “positioned up and down rather than side to side; going straight up” (definition taken from Merriam Webster on 7/25/2026) and is thus and absolute and not a relative direction. Thus the statement “vertical to the first direction” does not make sense. This issue renders the claim indefinite. For the purposes of examination, the examiner will interpret the limitation as “a third power line extending in a second direction perpendicular to the first direction”.
Note that dependent claims necessarily inherit any indefiniteness from the claims on which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5 and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KOBAYASHI (US 20080128830).
Regarding claim 1, as best as the examiner is able to ascertain the claimed invention, KOBOYASHI discloses a semiconductor integrated circuit device, comprising:
a chip (the chip 1 which fig 2-8 show a portion of , see fig 1, para 33);
a core region (the first area 12, see fig 1-8, para 37) provided on the chip;
an IO region (second area 13, see fig 1-8, para 37) provided on the chip between the core region and an outer periphery of the chip (13 will be between some border of the chip and 12, see fig 1-8);
an IO cell row provided in the IO region and constituted by a plurality of IO cells including first and second IO cells (each individual transistor with a gate 21, see fig 1-6, para 43) arranged in line in a first direction (transistor are arranged along the x-direction in fig 6-7), the first direction being a direction along the outer periphery (the x-direction in fig 6-7 will extend along a side of the outer periphery of 1, see fig 1 and 6-7);
a first power line (fig 1-8, 32a, para 66) extending in the first direction (32a extends in the x direction, see fig 8) in the IO region (32a extends in the first area 12, see fig 8, para 37), formed in a first interconnect layer (32a is formed in the interconnect layer comprising L1 and L2, see fig 4, para 66) and supplying first power (32a is connected to the power supply, see fig 1-8, para 68);
a second power line (fig 1-8, 32b, para 67) extending in the first direction (32b extends in the x direction of fig 8) in the core region (32b extends in the second area 13, see fig 4, para 67) and supplying the first power (32b is connected to the power supply, see fig 1-8, para 68);
a third power line (a middle gate 21 in region 12, see fig 4 and 7, para 43) extending in a second direction vertical to the first direction (21 extend in the y-direction in fig 7), formed in a second interconnect layer located below the first interconnect layer (21 are formed in the layer GL which is below L1, see fig 4) and connected to the first and second power lines (the gate 21 in the first area 12 is connected to 32a by TH, and is further connected to 32B by 11, see fig 4, para 38);
first and second external connection pads respectively corresponding to the first and second IO cells (two of the drain electrode pads 15 associated with first and second transistors, respectively, see fig 2-8, para 38);
a first interconnect connecting the first IO cell and the first external connection pad (the left interconnect between 15 and drain region 28 of the first transistor comprising TH and 31d that extends through GL in the first area, see fig 5, para 58), formed in the second interconnect layer; and
a second interconnect connecting the second IO cell and the second external connection pad (the right interconnect between 15 and drain region 28 of the second transistor comprising TH and 31d that extends through GL in the first area, see fig 5, para 58), formed in the second interconnect layer,
wherein the third power line overlaps the first external connection pad in planar view (the middle gate 21 in the first area overlaps with 15 along the vertical direction in fig 5) and is placed between the first interconnect and the second interconnect in the first direction (the middle gate 21 is between the left and right interconnects TH in the first area, see fig 5).
Regarding claim 2, as best as the examiner is able to ascertain the claimed invention, KOBOYASHI discloses the semiconductor integrated circuit device of claim 1, wherein the third power line overlaps the first and second external connection pads in planar view (the gate electrodes 21 extend in the x-direction in fig 2 to extend under a plurality of pads 15, see fig 2 and 5).
Regarding claim 4, as best as the examiner is able to ascertain the claimed invention, KOBOYASHI discloses the semiconductor integrated circuit device of claim 1, further comprising: a fourth power line (fig 2-8, 31, para 56) extending in the first direction in the IO region (31 extends in the x-direction in the first area, see fig 4), formed in the first interconnect layer (31 is formed in the interconnect layer comprising L1 and L2, see fig 4) and supplying second power different from the first power (31 is connected to the source connection line 30, see fig 4, para 56).
Regarding claim 5, as best as the examiner is able to ascertain the claimed invention, KOBOYASHI discloses a semiconductor integrated circuit device, comprising:
a chip (the chip 1 which fig 2-8 show a portion of , see fig 1, para 33);
a core region (the first area 12, see fig 1-8, para 37) provided on the chip;
an IO region (second area 13, see fig 1-8, para 37) provided on the chip between the core region and an outer periphery of the chip (13 will be between some border of the chip and 12, see fig 1-8);
an IO cell row provided in the IO region and constituted by a plurality of IO cells including first and second IO cells (each individual transistor with a gate 21, see fig 1-6, para 43) arranged in line in a first direction (transistor are arranged along the x-direction in fig 6-7), the first direction being a direction along the outer periphery (the x-direction in fig 6-7 will extend along a side of the outer periphery of 1, see fig 1 and 6-7);
a first power line (fig 1-8, 32a, para 66) extending in the first direction (32a extends in the x direction, see fig 8) in the IO region (32a extends in the first area 12, see fig 8, para 37), formed in a first interconnect layer (32a is formed in the interconnect layer comprising L1 and L2, see fig 4, para 66) and supplying first power (32a is connected to the power supply, see fig 1-8, para 68);
a second power line (fig 1-8, 32b, para 67) extending in the first direction (32b extends in the x direction of fig 8) in the core region (32b extends in the second area 13, see fig 4, para 67) and supplying the first power (32b is connected to the power supply, see fig 1-8, para 68);
a third power line (a left gate 21 in region 12, see fig 4 and 7, para 43) extending in a second direction vertical to the first direction (21 extend in the y-direction in fig 7), formed in a second interconnect layer located below the first interconnect layer (21 are formed in the layer GL which is below L1, see fig 4) and connected to the first and second power lines (the gate 21 in the first area 12 is connected to 32a by TH, and is further connected to 32B by 11, see fig 4, para 38);
a fourth power line (a right gate 21 in region 12, see fig 4 and 7, para 43) extending in the second direction, formed in the second interconnect layer (21 are formed in the layer GL which is below L1, see fig 4) and connected to the first and second power lines (the gate 21 in the first area 12 is connected to 32a by TH, and is further connected to 32B by 11, see fig 4, para 38);
a first external connection pad corresponding to the first IO cell (a drain electrode pad 15 associated with first and second transistors, respectively, see fig 2-8, para 38); and
a first interconnect connecting the first IO cell and the first external connection pad (the middle interconnect between 15 and drain region 28 of the first transistor comprising TH and 31d that extends through GL in the first area, see fig 5, para 58), formed in the second interconnect layer,
wherein the third and fourth power lines overlap the first external connection pad in planar view (the left and right gates 21 in the first area overlaps with 15 along the vertical direction in fig 5), and the first interconnect is placed between the third power line and the fourth power line in the first direction (the middle interconnect TH is between the left and right gates in 12, see fig 5).
Regarding claim 7, as best as the examiner is able to ascertain the claimed invention, KOBOYASHI discloses the semiconductor integrated circuit device of claim 5, further comprising: a fifth power line (fig 2-8, 31, para 56) extending in the first direction in the IO region (31 extends in the x-direction in the first area, see fig 4), formed in the first interconnect layer (31 is formed in the interconnect layer comprising L1 and L2, see fig 4) and supplying second power different from the first power (31 is connected to the source connection line 30, see fig 4, para 56).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOBOYASHI (US 20080128830) in view of HSU (US 20210296235).
Regarding claim 3, KOBOYASHI discloses the semiconductor integrated circuit device of claim 1.
KOBOYASHI fails to explicitly disclose a device, further comprising: a fourth power line extending in the first direction in the IO region, formed in the first interconnect layer and supplying the first power.
HSU teaches a device, further comprising: a fourth power line extending in the first direction in the IO region, formed in the first interconnect layer and supplying the first power (the additional interconnect 125 between the first power line 122 and the third power line 11G in the lower interconnect layer, see fig 3, para 42).
KOBOYASHI and HSU are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOBOYASHI with the additional electrode layer of HSU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOBOYASHI with the additional electrode layer of HSU in order to improve design and fabrication (see HSU para 67).
Regarding claim 6, KOBOYASHI discloses the semiconductor integrated circuit device of claim 5.
KOBOYASHI fails to explicitly disclose a device, further comprising: a fifth power line extending in the first direction in the IO region, formed in the first interconnect layer and supplying the first power.
HSU teaches a device, further comprising: a fifth power line extending in the first direction in the IO region, formed in the first interconnect layer and supplying the first power (the additional interconnect 125 between the first power line 122 and the third power line 11G in the lower interconnect layer, see fig 3, para 42).
KOBOYASHI and HSU are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOBOYASHI with the additional electrode layer of HSU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOBOYASHI with the additional electrode layer of HSU in order to improve design and fabrication (see HSU para 67).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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