DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 7, 13, and 14 are rejected for indefiniteness.
Claims 6 and 7 recite “current flows from … in response to … having a higher bias than …” The claims are indefinite because while claims 6 and 7 begin by reciting an apparatus/device, claims 6 and 7 further include a method of using the structure in causing current to flow in response to a higher bias between two components. The claims are not considered product by process claims because the claims do not state that any feature was made using current flowing between two components in response to a higher bias. The claim recites that the apparatus/device is used to perform current flowing in response to a higher bias between two components.
A single claim that includes both an apparatus and a method of using the apparatus/device is indefinite (See MPEP 2173.05(p)(II)). It is unclear if infringement would occur when the apparatus/device is created or when the apparatus/device is used in the performing of causing current to flow in response to a higher bias between two components. For the purposes of examination, the process limitation will be treated as an intended result limitation (i.e. the apparatus must be capable of being used in causing current to flow in response to a higher bias between two components).
Regarding claims 13 and 14, the claims recite, "the MT1 terminal." there is insufficient antecedent basis for this element. To further prosecution, Examiner will assume the claims should read, "the first MT1 terminal." Proper correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Plummer (US RE33209 E), and further in view of Bacuvier (US 4812893 A).
Regarding claim 1, Plummer teaches a triode for alternating current semiconductor (Fig 11; functions as a MOS controlled silicon controlled rectifier, [Col 7, Ln 12-13]) comprising:
an N- region (104) sandwiched between (shown sandwiched between) a first P region () and a second P region (), wherein
the first P region (105) is coupled (shown coupled) to an MT2 terminal (110) and
the second P region (102) is coupled (shown coupled) to a first MT1 terminal (111) and a second MT1 terminal (112);
a trench (T: trench below upper surface of 106 shown extending down into N- region 104) disposed between (shown between; the gate electrode 108 is comprised of two parts: 108L is the first gate terminal on the left of the trench T, 108R is the second gate terminal on the right of the trench T; please see annotated figure below) a first gate terminal (108L) and a second gate terminal (108R).
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Plummer fails to explicitly teach a first plurality of N+ regions disposed within the first P region.
However, Bacuvier teaches a first plurality of N+ regions (N3, Fig 9) disposed within (shown within) the first P region.
Plummer and Bacuvier are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor triac devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Plummer with the features of Bacuvier to create a triode with a first plurality of N+ regions disposed within the first P region insensitive to re-enabling by dV/dt striking on switching to be sensitive to a control provided by a low gate current (Bacuvier, [Col 1, Ln 63-66]) since triacs thus formed behave particularly well in so far as the resistance to dV/dt striking on switching is concerned, without significantly affecting the sensitivity to triggering by a gate current in quadrants I, II, III (Bacuvier, [Col 5, Ln 60-64]).
Regarding claim 2, the combination of Plummer and Bacuvier discloses the semiconductor of claim 1. Plummer goes on to teach further comprising a second plurality of N+ regions (100, Fig 11) disposed within the second P region (102).
Regarding claim 3, the combination of Plummer and Bacuvier discloses the semiconductor of claim 2. Plummer goes on to teach wherein a first N+ region (100L: 100 on left, Fig 11) of the second plurality of N+ regions (100) is disposed beneath (shown beneath; please see annotated figure above) the first gate terminal (108L) and a second N+ region (100R: 100 on right) of the second plurality of N+ regions (100) is disposed beneath (shown beneath) the second gate terminal (108R).
Regarding claim 4, the combination of Plummer and Bacuvier discloses the semiconductor of claim 3. Plummer goes on to teach wherein the trench (T; please see annotated figure above) cuts through (shown cutting through) the second P region (102).
Regarding claim 5, the combination of Plummer and Bacuvier discloses the semiconductor of claim 4. Plummer goes on to teach wherein the trench (T; please see annotated figure above) cuts into (shown cutting into) the N- region (104).
Regarding claim 6, the combination of Plummer and Bacuvier discloses the semiconductor of claim 1. Plummer teaches the MT2 terminal (110, Fig 11) and the first MT1 terminal (111).
Bacuvier goes on to teach wherein current flows (Bacuvier is capable of this function; a triac is achieved in four distinct modes, [Col 2, Ln 5]) from the MT2 terminal to the first MT1 terminal in response to the MT2 terminal having a higher bias than the first MT1 terminal.
Regarding claim 7, the combination of Plummer and Bacuvier discloses the semiconductor of claim 1. Plummer teaches the second MT1 terminal (112, Fig 11) and the MT2 terminal (110).
Bacuvier goes on to teach wherein current flows (Bacuvier is capable of this function; a triac is achieved in four distinct modes, [Col 2, Ln 5]) from the second MT1 terminal to the MT2 terminal in response to the second MT1 terminal having a higher bias than the MT2 terminal.
Regarding claim 8, the combination of Plummer and Bacuvier discloses the semiconductor of claim 2. Plummer teaches the first P region (105, Fig 11) and the N- region (104).
Bacuvier goes on to teach further comprising a first junction (QA: junction between first P region P2 and N- region N2, Fig 9; please see annotated figure below) between the first P region and the N- region.
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Regarding claim 9, the combination of Plummer and Bacuvier discloses the semiconductor of claim 8. Plummer teaches the N- region (104, Fig 11) and the second P region (102).
Bacuvier goes on to teach further comprising a second junction (QB: junction between N- region N2 and second P region P1; please see annotated figure above) between the N- region and the second P region.
Regarding claim 10, the combination of Plummer and Bacuvier discloses the semiconductor of claim 9. Plummer teaches the second P region (102, Fig 11) and the second plurality of N+ regions (100).
Bacuvier goes on to teach further comprising a third junction (QC: junction between second P region P1 and second plurality of N+ regions N1; please see annotated figure above) between the second P region and the second plurality of N+ regions.
Regarding claim 11, the combination of Plummer and Bacuvier discloses the semiconductor of claim 10. Plummer teaches the first P region (105, Fig 11).
Bacuvier goes on to teach further comprising a fourth junction (QD: junction between first plurality of N+ regions N3 and first P region P2; please see annotated figure above) between the first plurality of N+ regions (N3) and the first P region.
Regarding claim 12, the combination of Plummer and Bacuvier discloses the semiconductor of claim 1. Plummer goes on to teach wherein there is no shunt current (no shunt current; shunting occurs in a different device of Fig 2, [Col 4, Ln 30-32]).
Regarding claim 13, the combination of Plummer and Bacuvier discloses the semiconductor of claim 2. Plummer goes on to teach wherein a first N+ region (100L: 100 on left, Fig 11) of the second plurality of N+ regions (100) is disposed beneath (shown beneath) the MT1 terminal (111).
Regarding claim 14, the combination of Plummer and Bacuvier discloses the semiconductor of claim 13. Plummer teaches the second plurality of N+ regions (100, Fig 11) and the MT1 terminal (111).
Bacuvier goes on to teach wherein a second N+ region (N1L: N1 on left, Fig 9) of the second plurality of N+ regions is disposed beneath (shown beneath) the MT1 terminal.
Regarding claim 15, the combination of Plummer and Bacuvier discloses the semiconductor of claim 14. Plummer teaches the second plurality of N+ regions (100, Fig 11) and the MT1 terminal (111).
Bacuvier goes on to teach wherein a third N+ region (N1R: N1 on right, Fig 9) of the second plurality of N+ regions is disposed beneath (shown beneath) the MT1 terminal.
Regarding claim 16, the combination of Plummer and Bacuvier discloses the semiconductor of claim 1. Plummer teaches the MT2 terminal (110, Fig 11).
Bacuvier goes on to teach wherein a first N+ region (N3R: N3 on right, Fig 9) of the first plurality of N+ regions (N3) is disposed beneath (shown beneath) the MT2 terminal.
Regarding claim 17, the combination of Plummer and Bacuvier discloses the semiconductor of claim 16. Plummer teaches the MT2 terminal (110, Fig 11).
Bacuvier goes on to teach wherein a second N+ region (N3M: N3 in middle) of the first plurality of N+ regions (N3) is disposed beneath (shown beneath) the MT2 terminal.
Regarding claim 18, the combination of Plummer and Bacuvier discloses the semiconductor of claim 17. Plummer teaches the MT2 terminal (110, Fig 11).
Bacuvier goes on to teach wherein a third N+ region (N3LA; the N3 region on the left side of Fig 9, N3L, is comprised of two subparts: N3LA is the left half of N3L disposed under N4, N3LB is the right half of N3L) of the first plurality of N+ regions (N3) is disposed beneath (shown beneath) the MT2 terminal.
Regarding claim 19, the combination of Plummer and Bacuvier discloses the semiconductor of claim 18. Plummer teaches the MT2 terminal (110, Fig 11).
Bacuvier goes on to teach wherein a fourth N+ region (N3LB; the N3 region on the left side of Fig 9, N3L, is comprised of two subparts: N3LA is the left half of N3L disposed under N4, N3LB is the right half of N3L) of the first plurality of N+ regions (N3) is disposed beneath (shown beneath) the MT2 terminal.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hague (US 20120161200 A1) - Groove through P layer into N layer, wherein a gate could be added to make a triac.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897