Prosecution Insights
Prosecution Insights
Technology area: Semiconductors, Circuits & Optics
7 pending office actions • 6 art units • 7 examiners • 0 of 7 (0%) have an AI response strategy ready • 8 patents granted in the last 365 days
Littelfuse Semiconductor (Wuxi) Co. Ltd. currently manages 6 pending office actions within the Semiconductors, Circuits & Optics technology area. These actions are distributed across 6 distinct examiners, indicating that each pending matter is being reviewed by a different individual. This variety suggests that the company's prosecution outcomes are not overly dependent on the habits of any single examiner. The portfolio's progress depends on navigating a variety of examiner perspectives simultaneously.
The portfolio spans 5 distinct art units, showing a broad technical reach within the semiconductor field. Purvis, Sue A is identified as the busiest examiner, though she is responsible for only 1 pending office action. With 6 pending actions and six distinct examiners, the workload is perfectly distributed, requiring the company to navigate the specific requirements of five different art units simultaneously. This structure allows the company to gather diverse insights into examiner behavior across multiple technical groups.
Based on the USPTO statutory response window for each pending office action. 1 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 3 (43%) |
| §102 only | 1 (14%) |
| Multi-statute (no §101) | 3 (43%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| PURVIS, SUE A | 1 | 64.0% | +11.8% |
| SABUR, ALIA | 1 | 74.6% | +6.3% |
| WINTERS, SEAN AYERS | 1 | 88.2% | +19.3% |
| LINDSEY, COLE LEON | 1 | 88.9% | +12.7% |
| SALERNO, SARAH KATE | 1 | 73.6% | +15.0% |
| BELOUSOV, ALEXANDER | 1 | 76.6% | +16.3% |
| PETERSON, ERIK T | 1 | 76.5% | +11.0% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18526532 | TRIAC DEVICE WITH HIGH COMMUTATING CAPABILITY | LINDSEY, COLE LEON | 9d overdue |
| 18526436 | SCR STRUCTURE WITH HIGH NOISE IMMUNITY | WINTERS, SEAN AYERS | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18426051 | METHOD OF PEAK ON-STATE VOLTAGE REDUCTION FOR SEMICONDUCTOR DEVICE FABRICATION | SABUR, ALIA | — |
| 18490963 | UNIDIRECTIONAL HIGH VOLTAGE PUNCH THROUGH TVS DIODE AND METHOD OF FABRICATION | SALERNO, SARAH KATE | — |
| 17706008 | SEMICONDUCTOR MESA DEVICE FORMATION METHOD | PETERSON, ERIK T | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 6 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18526532 | TRIAC DEVICE WITH HIGH COMMUTATING CAPABILITY | LINDSEY, COLE LEON | 9d overdue |
| 18591815 | POWER MODULE WITH IMPROVED SEMICONDUCTOR DIE ARRANGEMENT FOR ACTIVE CLAMPING | PURVIS, SUE A | — |
| 18526436 | SCR STRUCTURE WITH HIGH NOISE IMMUNITY | WINTERS, SEAN AYERS | — |
| 18490963 | UNIDIRECTIONAL HIGH VOLTAGE PUNCH THROUGH TVS DIODE AND METHOD OF FABRICATION | SALERNO, SARAH KATE | — |
| 18369054 | BIDIRECTIONAL ASYMMETRIC TRANSIENT VOLTAGE SUPPRESSOR DEVICE | BELOUSOV, ALEXANDER | — |
| 17706008 | SEMICONDUCTOR MESA DEVICE FORMATION METHOD | PETERSON, ERIK T | — |
| Art Unit | Apps |
|---|---|
| 2898 | 2 |
| 2893 | 1 |
| 2892 | 1 |
| 2812 | 1 |
| 2814 | 1 |
| 2818 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18591815 | POWER MODULE WITH IMPROVED SEMICONDUCTOR DIE ARRANGEMENT FOR ACTIVE CLAMPING | PURVIS, SUE A | 2893 | §103 | Non-Final OA | — | Pending | Feb 29, 2024 |
| 18426051 | METHOD OF PEAK ON-STATE VOLTAGE REDUCTION FOR SEMICONDUCTOR DEVICE FABRICATION | SABUR, ALIA | 2898 | §102§103§112 | Non-Final OA | — | Pending | Jan 29, 2024 |
| 18526436 | SCR STRUCTURE WITH HIGH NOISE IMMUNITY | WINTERS, SEAN AYERS | 2892 | §102 | Non-Final OA | — | Pending | Dec 01, 2023 |
| 18526532 | TRIAC DEVICE WITH HIGH COMMUTATING CAPABILITY | LINDSEY, COLE LEON | 2812 | §103 | Final Rejection | 9d overdue | Pending | Dec 01, 2023 |
| 18490963 | UNIDIRECTIONAL HIGH VOLTAGE PUNCH THROUGH TVS DIODE AND METHOD OF FABRICATION | SALERNO, SARAH KATE | 2814 | §102§103 | Non-Final OA | — | Pending | Oct 20, 2023 |
| 18369054 | BIDIRECTIONAL ASYMMETRIC TRANSIENT VOLTAGE SUPPRESSOR DEVICE | BELOUSOV, ALEXANDER | 2818 | §103 | Non-Final OA | — | Pending | Sep 15, 2023 |
| 17706008 | SEMICONDUCTOR MESA DEVICE FORMATION METHOD | PETERSON, ERIK T | 2898 | §103§112 | Non-Final OA | — | Pending | Mar 28, 2022 |
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