Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicant’s election without traverse of Species II in the reply filed on 4/27/2026 is acknowledged.
Claim 6 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/27/2026.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Canada on 6/08/2022. It is noted, however, that applicant has not filed a certified copy of the PCT/CA2022/050911 application as required by 37 CFR 1.55.
Filing Dates for the Claims — All Claims Not Entitled to Priority DateTo be entitled to the filing date of the foreign priority application PCT/CA2022/050911 a certified copy of the application in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in certified copy.
Claim Objections
Claim 13 objected to because of the following informalities:
Claim 13 recites the limitation “The SPAD array as defined in Claim 1, wherein each of the SPAD cells in the array are separated by a pitch of 5 to 100 pm.” In the specification the pitch is described in para. 61 as “In this exemplary buildup, each of the SPAD cells 41 in the array may be separated by a pitch of 50 to 100 µm. Lower pitch separation, for example as low as 5 µm may be achievable depending on the manufacturing process and may be useful for a number of applications. “
For examination purposes the claim is being interpreted to read “The SPAD array as defined in Claim 1, wherein each of the SPAD cells in the array are separated by a pitch of 5 to 100 µm.”
Appropriate correction is required.
35 USC § 103 Rejections
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1, 3-5, 11-13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Piemonte (US Pub 20190312070) hereinafter referred to as Piemonte 2019, I view of Piemonte et al. (US Pub. 20180374978) hereinafter referred to as Piemonte 2018.
Regarding claim 1, Piemonte 2019 teaches vertically integrated frontside illuminated single photon avalanche diode (SPAD) array comprising: a substrate (Piemonte 2019, 104, Fig. 2B, paras. 29, 54); a plurality of layers of integrated circuitry disposed on said substrate (Piemonte 2019 236, Fig. 2D, para. 56), said integrated circuitry comprising interconnection circuit elements (Piemonte 2019, 232, Fig. 2D, para. 56) including surface contacts (Piemonte 2019, 140, Fig. 2D, para. 41) disposed in an array; a first material layer of a n-type semiconductor (Piemonte 2019, 112, Fig. 2D, paras 29, 46) disposed on said surface contact; a second material layer of a p-type semiconductor disposed on said first material layer (Piemonte 2019, 108, Fig. 2D, paras 29, 46), wherein an arrangement of said first and second material layer defines a SPAD junction (Piemonte 2019, 132, Fig. 2D, para. 40; a top surface electrode disposed on said second material layer (Piemonte 2019, 136, Fig. 2D, para. 40); a layer of insulation material (Piemonte 2019, 116, Fig. 2D para. 40), wherein the layer of insulation material is thinner than a thickness of the first material layer or than a thickness of the second material layer (Piemonte 2019, Fig. 2D, 116 is thinner than 112 or 108); and opto-electrical insulation barriers (Piemonte 2019, 120, Fig. 2D, para. 41) filling a space defined by trench walls extending through said first and second material layer to optically and electrically insulate individual SPAD cells of said SPAD array from one another.
Piemonte 2019 does not explicitly teach wherein the layer of insulation material is covering an outer most surface of the SPAD array.
However, Piemonte 2018 teaches a SPAD semiconductor device with an outer layer (Piemonte 2018, 132, Fig. 1B, para. 33) which may include a dielectric layer.
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the SPAD of Piemonte 2019 with the protective layer of Piemonte 2018 in order to physically protect the other components of the semiconductor device from environmental hazards, but permit light (e.g., photons) or the like to pass therethrough (Piemonte 2018, para. 33)
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Regarding claim 3, modified Piemonte 2019 teaches the SPAD array as defined in Claim 1, wherein said interconnection circuit elements further comprise a top surface contact to a side of said SPAD cells for providing external control over a voltage on said top surface electrode (Piemonte 2019, para. 29).
Regarding claim 4, modified Piemonte 2019 teaches the SPAD array as defined in Claim 1, wherein said top surface electrode comprise a metal grid operable to bias all SPAD to the same voltage (Piemonte, 2019, paras. 51, 29).
Regarding claim 11, modified Piemonte 2019 teaches the SPAD array as defined in Claim 1, wherein said surface contacts (Piemonte 2019, 232, Fig. 2D, para. 56) extend over more than one half of an area of said first material layer (Piemonte, 2019, para. 44, shows the metal may be configured to more than 50% of the back surface of the device) to provide a high conductivity path such that the timing jitter intrinsic to the formation and propagation of the avalanche is reduced.
Regarding claim 12, modified Piemonte 2019 teaches the SPAD array as defined in Claim 1, wherein said surface contacts of said circuitry comprise a Germanium interconnecting layer (Piemonte 2019, para. 55, states the contact may be fined by any known CMOS or other processes, and para. 37 of the instant application states that the contact “may be a germanium layer, as it is known in the art and common in CMOS technologies).
Regarding claim 13, modified Piemonte teaches, as interpreted above, the SPAD array as defined in Claim 1, wherein each of the SPAD cells in the array are separated by a pitch of 5 to 100 µm (Piemonte 2019, para. 43).
Regarding claim 16, modified Piemonte 2019 teaches the SPAD array as defined in Claim 1, wherein the layer of insulation material is thinner than a thickness of a thinnest of the first and second material layer (Piemonte 2019, Fig. 2D, 116 is thinner than 112 or 108).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Piemonte 2019 and Piemonte 2018 as applied to claim 1 above, and further in view of Finkelstein (US Pub. 20200135776), hereinafter referred to as Finkelstein.
Regarding claim 2, modified Piemonte 2019 teaches the SPAD array as defined in Claim 1, but does not teach wherein said interconnection circuit elements further comprises a data bus, data bus contacts connected to said data bus, surface contacts connected to said data bus, and readout circuitry connected to said surface contacts and to said data bus.
However, Finkelstein teaches a SPAD array with a readout wafer (Finkelstein, 102, Fig. 1A, para. 62) which includes controller, timing and correlation circuitry (Finkelstein, Figs. 6A and 6B, para. 62).
Therefore it would have been obvious to one having ordinary skill in the art to combine the SPAD of modified Piemonte 2019 with the readout wafer of Finkelstein to create a SPAD array to perform time of flight measurement operations (Finkelstein, para. 69).
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Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Piemonte 2019 and Piemonte 2018 as applied to claim 1 above, and further in view of Cao (US Pub. 20210167102), hereinafter referred to as Cao.
Regarding claim 7, modified Piemonte 2019 teaches the SPAD array as defined in Claim 1, but does not teach wherein said arrangement of said first and second material layer is configured to extend a sensitivity of said SPAD array for working with a wavelength below 350 nm.
However, Cao teaches a SPAD sensor in which the avalanche photodiodes (Cao, 110, Fig. 1, para. 34 ) are configured to operate between 250 and 320 nm (Cao para. 34).
Therefore It would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the SPAD of Piemonte 2019 with the configuration of CAO for use in including fire detection, industrial manufacturing, biochemical research, light sources, and environmental and structural health monitoring (Cao, para. 3).
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Regarding claim 17, modified Piemonte 2019 teaches the SPAD array as defined in Claim 7, wherein the layer of insulation material (Cao, 130, Fig. 1, para. 34) is thin enough to allow photons with the wavelength below 350 nm to pass through said layer of insulation material.
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Piemonte 2019, Piemonte 2018 and Cao as applied to claim 7 above, and further in view of Dautet (US Pub 20130009265) hereinafter referred to as Dautet.
Regarding claim 8, modified Piemonte 2019 teaches the SPAD array as defined in Claim 7, but does not teach that it comprises a third material layer disposed on said second material layer, wherein said third material layer is configured to drift surface photoelectrons to said SPAD junction.
However, Dautet teaches a SPAD wherein there is a third layer (Dautet, 106, Fig. 1B, para. 29) wherein the p-n junction can be modified to detect certain wavelengths (Dautet, para. 31).
Therefore it is obvious to one having ordinary skill in the art to combine the SPAD of modified Piemonte with the third layer of Dautet to be able to selectively detect wavelengths of light (Dautet, para. 31).
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Regarding claim 9, modified Piemonte 2019 teaches the SPAD array as defined in Claim 8, wherein said third material layer is a highly boron doped silicon layer (Dautet paras. 26, 29).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Piemonte 2019 and Piemonte 2018 as applied to claim 1 above, and further in view of Piemonte (US 20200135956) hereinafter referred to as Piemonte 2020.
Regarding claim 10, modified Piemonte 2019 teaches the SPAD array as defined in Claim 1, but does not teach wherein said opto-electrical insulation barriers comprise in-situ doped polysilicon such that crosstalk between SPADs is reduced.
However, Piemonte 2020 teaches a trench structure wherein the trenches contain a layer (Piemonte 2020, 136, Fig. 1B, para. 32) made up of doped polysilicon.
Therefore it would have been obvious to one having ordinary skill in the art to combine the SPAD of modified Piemonte 2019 with the trench structure of Piemonte 2020 to reduce optical cross-talk (Piemonte 2020, para. 21).
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Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Piemonte 2019 and Piemonte 2018 as applied to claim 1 above, and further in view of Shen et al. (US Pub. 20220037268)
Regarding claim 14, modified Piemonte 2019 teaches the SPAD array as defined in Claim 1, but does not teach wherein a seal ring surrounds a whole die and provides mechanical support.
However, Shen teaches a semiconductor device wherein the die (Shen, 320, Fig. 25, para. 65) is surrounded by a seal ring (Shen, 468, Fig. 25, paras. 59, 65).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the SPAD array of modified Piemonte with the seal ring of Shen in order to reduce chipping propagation and keep out humidity and contaminants from penetrating along the bonding interface and/or between the two wafers (Shen, para. 64)
Regarding claim 15, modified Piemonte2019 teaches the SPAD array as defined in Claim 14, wherein the seal ring is made of aluminum-germanium composite (Shen, para. 58-59).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nagano et al. (US Pub. 2014091486) teaches an avalanche photodiode with an electrode arranged on top of the APD region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:00-4:3.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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