DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is made non-final.
Claims 1-20 are pending. Claims 1, 11 and 20 are independent claims.
Claim Rejections - 35 USC § 112
Claims 2, 5, 12 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "to the at least one different processing node". There is insufficient antecedent basis for this limitation in the claim.
Claim 5 recites the limitation "the third processing device". There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "to the at least one different processing node". There is insufficient antecedent basis for this limitation in the claim.
Claim 15 recites the limitation "as the third processing device". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1:
Step 1: This part of the eligibility analysis evaluates whether the claim falls within any statutory category. See MPEP 2106.03. Claim 1 recites: A processor comprising: one or more circuits to… Claim 1 is directed to an apparatus. (Step 1: YES).
Step 2A prong 1: Does the claim recite a judicial exception? Claim 1 recites: identify, based at least on a representation of a quantum computing circuit, a first distribution corresponding to an allocation of one or more portions of the quantum computing circuit for simulation using a plurality of processing devices of a computing platform, arranged according to a network topology (identifying an arrangement or mapping for a circuit based on a network topology is a mental process); compute a first latency value according to a latency metric, the first latency value indicating a latency corresponding to simulating operations associated with the one or more portions of the quantum computing circuit according to the first distribution (computing a latency value according to a latency metric based on simulated operations of the circuit is a mental process or mathematical calculation, i.e., counting connections of a certain type, judging some size dimension of the circuit); determine, based on the network topology, a second distribution corresponding to a reallocation of at least one operation associated with the one or more portions of the quantum computing circuit based at least on a hierarchy of the network topology (determining a new arrangement for the circuit based on the network topology is a mental process); compute a second latency value that is less than the first latency according to the latency metric, the second latency value indicating a latency corresponding to simulating the one or more portions of the quantum computing circuit according to the second distribution (computing a new latency value based on a latency metric is again a mental process, and the latency value being reduced can be the result of the mental determination of the second distribution of the circuit)… These steps can be performed mentally or are mathematical calculations (Step 2A prong 1: YES).
Step 2A prong 2: Does the claim recite additional elements? Do those additional elements, considered individually and in combination, integrate the judicial exception into a practical application? Claim 1 recites: and simulate the quantum computing circuit on the computing platform using the second distribution. Simulating the quantum computing circuit on the computing platform is insignificant extra-solution activity of data outputting, i.e., implementing the selected circuit arrangement (Step 2A prong 2: NO).
Step 2B: These elements are recited at such a high level of generality that they fail to integrate the abstract idea into a practical application, since they since they only amount to data gathering or outputting without significantly more (MPEP 2106.05(g)). These limitations, taken either alone or in combination, fail to provide an inventive concept (Step 2B: NO). Thus, the claim is not patent eligible.
Regarding claims 2-10, they recite limitations which further narrow the abstract idea by specifying more details of the mental and mathematical process that occurs (Claim 2, redistributing portions of state vector in the circuit is either a mental process if done in the determination of the distribution or insignificant extra-solution activity of data outputting if done in relation to the actual implementation of the second distribution; Claim 3, selecting portions of a circuit, identifying gate groups that fulfil a criteria of a circuit, a selecting a qubit of the selected portion of the circuit o be reallocated are all mental processes; Claim 4, identifying an additional device of the platform to allocate qubits to is a mental process, i.e., identifying devices according to the network topology; Claim 5, selecting devices from the same layer of a hierarchy is a mental process; Claim 6, determining gate groups that have qubits allocated to them, and also have characteristics including a maximum number of qubits is a mental process, and combining gate groups based on that maximum qubit count is a mental process as well; Claim 7, sorting gate groups in order of qubit count is a mental process, and determining if gate groups have more than a threshold number of qubits is a mental process; Claim 8, outputting a simulation result using the generated second distribution for the circuit is insignificant extra-solution activity of data outputting; Claim 9, the network topology being a hierarchical profile of the computing platform’s resources still results in the allocation of qubits being a mental process; Claim 10, specifying that the processor is comprised in a control system for an autonomous/semi-autonomous machine, etc., is an attempt to limit the field of use without significantly more (MPEP 2106.05(h))).
Regarding claim 11, it is a method that recites similar limitations to the apparatus of claim 1 and is rejected on the same grounds – see above.
Regarding claims 12-19, they recite similar limitations to claims 2-9 respectively, and are rejected on the same grounds – see above.
Regarding claim 20:
Step 1: This part of the eligibility analysis evaluates whether the claim falls within any statutory category. See MPEP 2106.03. Claim 20 recites: A system comprising: a computing platform comprising a plurality of processing devices arranged according to a hierarchical network topology… Claim 20 is directed to an apparatus. (Step 1: YES).
Step 2A prong 1: Does the claim recite a judicial exception? Claim 20 recites: redistributing, based at least on a hierarchy of the network topology, at least one operation corresponding to a portion of the plurality of portions from a first processing device of the plurality of processing devices to a second processing device of the plurality of processing devices… (redistributing operations from a first device to another is a mental process, i.e., determining a schedule). These steps can be performed mentally or are mathematical calculations (Step 2A prong 1: YES).
Step 2A prong 2: Does the claim recite additional elements? Do those additional elements, considered individually and in combination, integrate the judicial exception into a practical application? Claim 20 recites: wherein a quantum computing circuit is simulated as a plurality of portions of the quantum computing circuit using the plurality of processing devices by... to reduce a communication latency corresponding to a simulation of the quantum computing circuit. Specifying that the circuit is a quantum computing circuit is an additional element(s) specifying a field of use without significantly more. Specifying that the mental redistributing results in a reduced communication latency is no more than mere instructions to implement the abstract idea which is equivalent to adding the words “apply it” to the recited judicial exception, reciting only the idea of a solution or outcome while omitting details on how said outcome is accomplished (Step 2A prong 2: NO).
Step 2B: These elements are recited at such a high level of generality that they fail to integrate the abstract idea into a practical application, since they since they only amount to limit the field of use without significantly more (MPEP 2106.05(h)) or provide nothing more than an idea of a solution or outcome (MPEP 2106.05(f)). These limitations, taken either alone or in combination, fail to provide an inventive concept (Step 2B: NO). Thus, the claim is not patent eligible.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 8, 9, 10, 11, 12, 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gambetta et al. (US 20200334563 A1), herein Gambetta, in view of Alam et al. (US 12387130 B1), herein Alam, and Kelcey et al. (US 20240135571 A1), herein Kelcey.
Regarding claim 1, Gambetta teaches: A processor comprising: one or more circuits to: identify, based at least on a representation of a quantum computing circuit, a first distribution corresponding to an allocation of one or more portions of the quantum computing circuit for simulation using… a computing platform (¶12, An embodiment produces a configuration of a first quantum circuit from the classical computing system, the first quantum circuit being executable using the quantum computing system), arranged according to a network topology (note: DAG refers to a directed acyclic graph – ¶38, In the DAG format, an embodiment models each input qubit as a starting vertex, and models each output qubit as an ending vertex. Between starting and ending vertices, an embodiment models operations on qubits as vertices. Just as a wire, representing a qubit, connects one gate to another in a quantum circuit representation, a graph edge, representing a qubit, connects one vertex to another in a DAG representation of the quantum circuit. Using such a DAG format, dataflow and dependencies between elements are explicit)… determine, based on the network topology, a second distribution corresponding to a reallocation of at least one operation associated with the one or more portions of the quantum computing circuit based at least on a hierarchy of the network topology (Abstract, In a first transformation pass according to a first transformation operation, the portion is transformed, resulting in a second quantum circuit, by reconfiguring a gate in the first quantum circuit such that a qubit used in the gate complies with the constraint on the quantum circuit design while participating in the second quantum circuit – and – ¶55, An embodiment continues in this fashion, alternating analysis and transformation passes, until an end criterion is reached. In one embodiment, an end criterion is an analysis result that conforms to the transpilation goal. For example, a transpilation goal may have been to reduce the depth of the quantum circuit to a specified depth)… and simulate the quantum computing circuit on the computing platform using the second distribution (¶58, generating a more optimized quantum circuit producing the same results as the original in a shorter time, with faster execution and using fewer resources, while performing the optimizing in a modular manner with execution and access controls).
Gambetta fails to teach: a plurality of processing devices of…
However, in the same field of endeavor, Alam teaches: a plurality of processing devices of (col. 7, line 29, a single quantum processor unit can include multiple quantum processor cells. For example, the QPU 103A can be a dual-QPU that includes multiple independent quantum processor cells in a shared environment. For instance, the dual-QPU may include two independently operated superconducting quantum processor circuits in the same cryogenic environment, on the same chip or substrate, or in another type of shared circuit environment. In some cases, the QPU 103A includes two, three, four or more quantum processor cells that can operate in parallel)…
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use multiple processing devices as disclosed by Alam in the apparatus disclosed by Gambetta to improve efficiency (col. 3, line 16, the quantum program synthesis techniques described here can be parallelized across many classical, quantum or hybrid (classical/quantum) resources in a computing system. And in some cases, multiple levels of optimization can be applied to utilize classical and quantum resources efficiently for solving optimization problems. Accordingly, in some cases, the techniques described here can improve the speed, efficiency and accuracy with which quantum resources are used to solve optimization problems).
Gambetta in view of Alam fails to explicitly teach: compute a first latency value according to a latency metric, the first latency value indicating a latency corresponding to simulating operations associated with the one or more portions of the quantum computing circuit according to the first distribution… compute a second latency value that is less than the first latency according to the latency metric, the second latency value indicating a latency corresponding to simulating the one or more portions of the quantum computing circuit according to the second distribution… Gambetta does discuss creating quantum computing circuits that have improved speed (¶58, A method of an embodiment described herein, when implemented to execute on a device or data processing system, comprises substantial advancement of the functionality of a quantum circuit by generating a more optimized quantum circuit producing the same results as the original in a shorter time, with faster execution and using fewer resources, while performing the optimizing in a modular manner with execution and access controls), but does not explicitly recite calculating or measuring a runtime, latency or speed.
However, in the same field of endeavor, Kelcey teaches: compute a first latency value according to a latency metric, the first latency value indicating a latency corresponding to simulating operations associated with the one or more portions of the quantum computing circuit according to the first distribution… compute a second latency value that is less than the first latency according to the latency metric, the second latency value indicating a latency corresponding to simulating the one or more portions of the quantum computing circuit according to the second distribution (¶34, In some implementations, the performance of a configuration may be determined by calculating a latency (e.g., an inference time), a memory usage (e.g., a random access memory (RAM) and/or a read only memory (ROM) usage), an energy usage (e.g., power consumption), and/or level of accuracy associated with the configuration when implemented on the target device. For example, the latency, or inference time, may be an amount of time for the configuration of the pipeline to process input data and produce output data when the configuration is implemented on a target device)…
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to measure a latency metric as disclosed by Kelcey in the apparatus disclosed by Gambetta in view of Alam to achieve satisfactory performance (¶34, In some implementations, a configuration may be selected, based on the configuration satisfying the application constraint).
Regarding claim 2, Gambetta further teaches: The processor of claim 1, wherein the one or more circuits are to: redistribute, to the at least one different processing node, at least a portion of a state vector corresponding to the portion of the quantum computing circuit to simulate (¶106, Example pass 1010 depicts results of performing a transformation operation to redistribute quantum gates in a circuit – also see the referenced Fig. 10 which contains the referenced Example pass 1010).
Regarding claim 8, Gambetta further teaches: The processor of claim 1, wherein the one or more circuits are to: output a simulation result for the quantum computing circuit, wherein the simulation result is computed based at least on simulation results of simulating the quantum computing circuit on the computing platform according to the second distribution (¶58, A method of an embodiment described herein, when implemented to execute on a device or data processing system, comprises substantial advancement of the functionality of a quantum circuit by generating a more optimized quantum circuit producing the same results as the original in a shorter time, with faster execution and using fewer resources, while performing the optimizing in a modular manner with execution and access controls).
Regarding claim 9, Gambetta further teaches: The processor of claim 1, wherein the network topology comprises a hierarchical profile of computing resources of the computing platform for executing a simulation of the quantum computing circuit (¶38, In the DAG format, an embodiment models each input qubit as a starting vertex, and models each output qubit as an ending vertex. Between starting and ending vertices, an embodiment models operations on qubits as vertices. Just as a wire, representing a qubit, connects one gate to another in a quantum circuit representation, a graph edge, representing a qubit, connects one vertex to another in a DAG representation of the quantum circuit. Using such a DAG format, dataflow and dependencies between elements are explicit).
Regarding claim 10, Gambetta further teaches: The processor of claim 1, wherein the processor is comprised in at least one of: a control system for an autonomous or semi-autonomous machine; a perception system for an autonomous or semi-autonomous machine; a system for performing simulation operations; a system for performing digital twin operations; a system for performing light transport simulation; a system for performing collaborative content creation for 3D assets; a system for generating or presenting at least one of virtual reality content, augmented reality content, or mixed reality content; a system for performing deep learning operations; a system implemented using an edge device (¶114, Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network… The network may comprise copper transmission cables… edge servers); a system implemented using a robot; a system for performing conversational AI operations; a system for generating synthetic data; a system incorporating one or more virtual machines (VMs); a system implemented at least partially in a data center; a system for performing generative AI operations; a system implemented at least partially using a language model; a system implemented at least partially using cloud computing resources; a system implemented at least partially using quantum computing resources; a system utilizing a Quantum Processing Unit (QPU); a system for performing a state preparation; a system for compiling a quantum circuit; a system for executing a quantum circuit; a system for measuring a quantum state; or a system for measuring a state of a qubit or qubits (¶36, In accordance with the illustrative embodiments, the environment includes at least one quantum compute node (QCN), and at least one conventional node (CN) on which an embodiment can execute. Such a computing environment is hereinafter referred to as a quantum computing environment (QCE). The QCE may include one or more CNs in a suitable configuration—such as a cluster—to execute applications using conventional binary computing. The hybrid environment can be implemented using cloud computing architecture – and – ¶39, For example, input metadata can specify specific attributes of a quantum processor for which the quantum circuit should be adapted, or a specific type of transformation to be performed on the quantum circuit).
Regarding claim 11, 12, 18 and 19, they recite similar limitations to claims 1, 2, 8 and 9 and are rejected on the same grounds – see above.
Claim(s) 3, 4, 5, 6, 13, 14, 15 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gambetta in view of Alam and Kelcey as applied to claims 1 and 11 above, and further in view of Naveh et al. (US 20230112525 A1), herein Naveh.
Regarding claim 3, Gambetta in view of Kelcey fails to explicitly teach: The processor of claim 1, wherein to determine the second distribution, the one or more circuits are to: select a first portion of the quantum computing circuit corresponding to a first qubit of the quantum computing circuit, the first qubit being allocated to a first part of the computing platform according to the first distribution; identify a gate group associated with the first qubit, the gate group comprising the first qubit and one or more first quantum gates of the quantum computing circuit coupled with the first qubit and measurable with input restricted to the first qubit; and select, based at least on the gate group, the first qubit to be reallocated for simulation using a second part of the computing platform, the second part comprising a different part from the first part.
However, in the same field of endeavor, Naveh teaches: wherein to determine the second distribution, the one or more circuits are to: select a first portion of the quantum computing circuit corresponding to a first qubit of the quantum computing circuit, the first qubit being allocated to a first part of the computing platform according to the first distribution; identify a gate group associated with the first qubit, the gate group comprising the first qubit and one or more first quantum gates of the quantum computing circuit coupled with the first qubit and measurable with input restricted to the first qubit; and select, based at least on the gate group, the first qubit to be reallocated for simulation using a second part of the computing platform, the second part comprising a different part from the first part (¶81, as part of determining the one or more optimizations, Functional Level Processing Component 130 may estimate whether some of the qubits used by a function block can be borrowed from a different functional block, instance, or the like. In some exemplary embodiments, a borrowed qubit may include a dirty qubit that can be temporarily used in condition that it is returned in its original state. Some quantum algorithms are capable of using qubits without relying on their exact state, e.g., even if they are unentangled with the rest of the system – and – ¶3, to thereby synthesize respective executable circuits that can be executed by a quantum computer, the method comprising: obtaining a gate-level representation of a quantum circuit, wherein the gate-level representation comprises a set of quantum gates defining operations on a set of qubits, wherein the gate-level representation comprises a gate-level implementation of a functional block of a functional-level representation of the quantum circuit, wherein the functional block defines an operation of the quantum circuit over at least two cycles – Naveh discusses function blocks that include gate-level implantation details that are able to borrow qubits in an optimization process).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to reallocate qubits that are part of one functional block to another functional block as disclosed by Naveh in the apparatus disclosed by Gambetta in view of Kelcey to improve memory usage (¶81, may reduce the overall quantum memory requirements and thereby decrease a utilization of qubit resources, at the expense of cleaning or returning the state of the borrowed qubit).
Gambetta in view of Kelcey and Naveh fails to teach: processing device… processing device… processing device… processing device… processing device.
However, in the same field of endeavor, Alam teaches: multiple processing devices (col. 7, line 29, a single quantum processor unit can include multiple quantum processor cells. For example, the QPU 103A can be a dual-QPU that includes multiple independent quantum processor cells in a shared environment. For instance, the dual-QPU may include two independently operated superconducting quantum processor circuits in the same cryogenic environment, on the same chip or substrate, or in another type of shared circuit environment. In some cases, the QPU 103A includes two, three, four or more quantum processor cells that can operate in parallel).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to allocate computing tasks to a second processing device as disclosed by Alam in the apparatus disclosed by Gambetta in view of Kelcey and Naveh to improve efficiency (col. 3, line 16, the quantum program synthesis techniques described here can be parallelized across many classical, quantum or hybrid (classical/quantum) resources in a computing system. And in some cases, multiple levels of optimization can be applied to utilize classical and quantum resources efficiently for solving optimization problems. Accordingly, in some cases, the techniques described here can improve the speed, efficiency and accuracy with which quantum resources are used to solve optimization problems).
Regarding claim 4, Gambetta in view of Kelcey and Naveh fails to explicitly teach: The processor of claim 3, wherein the one or more circuits are to: identify a third processing device of the computing platform allocated to simulate at least one operation of the gate group associated with the first qubit.
However, in the same field of endeavor, Alam teaches: wherein the one or more circuits are to: identify a third processing device of the computing platform allocated to simulate at least one operation of the gate group associated with the first qubit (col. 7, line 36, In some cases, the QPU 103A includes two, three, four or more quantum processor cells that can operate in parallel).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to allocate computing tasks to a second processing device as disclosed by Alam in the apparatus disclosed by Gambetta in view of Kelcey and Naveh to improve efficiency (col. 3, line 16, the quantum program synthesis techniques described here can be parallelized across many classical, quantum or hybrid (classical/quantum) resources in a computing system. And in some cases, multiple levels of optimization can be applied to utilize classical and quantum resources efficiently for solving optimization problems. Accordingly, in some cases, the techniques described here can improve the speed, efficiency and accuracy with which quantum resources are used to solve optimization problems).
Regarding claim 5, Gambetta in view of Kelcey and Naveh fails to explicitly teach: The processor of claim 3, wherein the second processing device comprises a processing device corresponding to a same layer of the hierarchy of the network layer as the third processing device (the referenced “third processing device” will be interpreted to mean the “third processing device” of claim 4).
However, in the same field of endeavor, Alam teaches: wherein the second processing device comprises a processing device corresponding to a same layer of the hierarchy of the network layer as the third processing device (col. 7, line 36, In some cases, the QPU 103A includes two, three, four or more quantum processor cells that can operate in parallel).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to allocate computing tasks to a third processing device as disclosed by Alam in the apparatus disclosed by Gambetta in view of Kelcey and Naveh to improve efficiency (col. 3, line 16, the quantum program synthesis techniques described here can be parallelized across many classical, quantum or hybrid (classical/quantum) resources in a computing system. And in some cases, multiple levels of optimization can be applied to utilize classical and quantum resources efficiently for solving optimization problems. Accordingly, in some cases, the techniques described here can improve the speed, efficiency and accuracy with which quantum resources are used to solve optimization problems).
Regarding claim 6, Gambetta in view of Alam and Kelcey fails to teach: The processor of claim 1, wherein the one or more circuits are to: generate two or more gate groups each including one or more qubits of the quantum computing circuit, each of the gate groups satisfying a threshold indicating a maximum number of qubits that can be allocated to a gate group among the gate groups; and combine a first gate group of the two or more gate groups and a second gate group of the two or more gate groups in response to a determination that the first gate group and the second gate group include a number of the qubits satisfying the threshold.
However, in the same field of endeavor, Naveh teaches: wherein the one or more circuits are to: generate two or more gate groups each including one or more qubits of the quantum computing circuit, each of the gate groups satisfying a threshold indicating a maximum number of qubits that can be allocated to a gate group among the gate groups; and combine a first gate group of the two or more gate groups and a second gate group of the two or more gate groups in response to a determination that the first gate group and the second gate group include a number of the qubits satisfying the threshold (¶172, As an example, the number of qubits utilized by the modified first sub-circuit may be smaller than a number of qubits utilized by the first sub-circuit. Accordingly, qubit resources may be freed to be utilized by the remainder portion of the sub-circuit. In some exemplary embodiments, the remainder portion may be re-synthesized taking into account the freed resources as well as previously available resources, to generate a modified second sub-circuit. The first and second sub-circuits may be combined to form a modified circuit – gates are referenced in ¶170, In some exemplary embodiments, the gate-level representation of the quantum circuit may comprise a set of quantum gates defining operations on a set of qubits… may comprise a first sub-circuit and a second sub-circuit… The gate-level processing component may modify or otherwise change the circuit, e.g., by modifying the first sub-circuit and creating a modified first sub-circuit instead).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify part of as disclosed by Naveh in the apparatus disclosed by Gambetta in view of Alam and Kelcey to improve efficiency or performance (¶178, may improve the overall resource utilization, so that the resource utilization of the quantum circuit representation that is created based on the modified first sub-circuit may be a Pareto improvement over the resource utilization of the originally synthesized quantum circuit representation).
Regarding claims 13-16, they recite similar limitations to claims 3-6, respectively, and are rejected on the same grounds – see above.
Claim(s) 7 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gambetta in view of Alam, Kelcey and Naveh as applied to claims 6 and 16 above, and further in view of Kalendarov et al. (US 20210049496 A1), herein Kalendarov.
Regarding claim 7, Gambetta in view of Alam, Kelcey and Naveh fails to explicitly teach: The processor of claim 6, wherein the one or more circuits are to: sort the two or more gate groups into a group order based on corresponding numbers of qubits in each of the gate groups; and determine, in response to iteration over one or more of the gate groups according to the group order, that the first gate group and the second gate group include the number of the qubits satisfying the threshold.
However, in the same field of endeavor, Kalendarov teaches: wherein the one or more circuits are to: sort the two or more gate groups into a group order based on corresponding numbers of qubits in each of the gate groups; and determine, in response to iteration over one or more of the gate groups according to the group order, that the first gate group and the second gate group include the number of the qubits satisfying the threshold (¶34, In an implementation form of the first aspect, the device is further configured to, when generating the set of clusters of quantum gates: order a cluster including more quantum gates before a cluster including less quantum gates in the order of the clusters – and – ¶35, In an implementation form of the first aspect, the device is further configured to, when generating the set of clusters of quantum gates: generate the clusters based on a maximum possible number of qubits in a cluster).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to sort gate groups in order of qubit count and ensure they include a number of qubits below a threshold as disclosed by Kalendarov in the apparatus disclosed by Gambetta in view of Alam, Kelcey and Naveh to improve efficiency (¶36, The above implementation forms lead to an improved efficiency of the algorithm performed by the device of the first aspect – and – ¶33, The device of the first aspect can be used in a distributed quantum circuit simulator, and may provide gate scheduling and qubits reordering. In other words, the device can provide a sophisticated gates and qubits permutation calculation for the quantum circuit simulator. The calculated permutations allow an optimal data exchange and quantum gate application schedule in a quantum circuit simulator, thus significantly reducing the amount of data transferred between nodes of the simulator).
Regarding claim 17, it recites similar limitations to claim 7 and is rejected on the same grounds – see above.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gambetta in view of Alam.
Regarding claim 20, Gambetta teaches: A system comprising: a computing platform (¶12, An embodiment produces a configuration of a first quantum circuit from the classical computing system, the first quantum circuit being executable using the quantum computing system) comprising a plurality of parts arranged according to a hierarchical network topology (¶38, In the DAG format, an embodiment models each input qubit as a starting vertex, and models each output qubit as an ending vertex. Between starting and ending vertices, an embodiment models operations on qubits as vertices. Just as a wire, representing a qubit, connects one gate to another in a quantum circuit representation, a graph edge, representing a qubit, connects one vertex to another in a DAG representation of the quantum circuit. Using such a DAG format, dataflow and dependencies between elements are explicit), wherein a quantum computing circuit is simulated as a plurality of portions of the quantum computing circuit using the plurality of parts by redistributing, based at least on a hierarchy of the network topology, at least one operation corresponding to a portion of the plurality of portions from a first part of the plurality of parts to a second part of the plurality of parts (Abstract, In a first transformation pass according to a first transformation operation, the portion is transformed, resulting in a second quantum circuit, by reconfiguring a gate in the first quantum circuit such that a qubit used in the gate complies with the constraint on the quantum circuit design while participating in the second quantum circuit – and – ¶55, a transpilation goal may have been to reduce the depth of the quantum circuit to a specified depth) to reduce a communication latency corresponding to a simulation of the quantum computing circuit (¶58, A method of an embodiment described herein, when implemented to execute on a device or data processing system, comprises substantial advancement of the functionality of a quantum circuit by generating a more optimized quantum circuit producing the same results as the original in a shorter time, with faster execution and using fewer resources, while performing the optimizing in a modular manner with execution and access controls).
Gambetta fails to explicitly teach: processing devices… processing devices… processing device… processing devices… processing device… processing devices.
However, in the same field of endeavor, Alam teaches: multiple processing devices (col. 7, line 29, a single quantum processor unit can include multiple quantum processor cells. For example, the QPU 103A can be a dual-QPU that includes multiple independent quantum processor cells in a shared environment. For instance, the dual-QPU may include two independently operated superconducting quantum processor circuits in the same cryogenic environment, on the same chip or substrate, or in another type of shared circuit environment. In some cases, the QPU 103A includes two, three, four or more quantum processor cells that can operate in parallel).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to allocate portions of a quantum circuit to different processing devices as disclosed by Alam in the apparatus disclosed by Gambetta to improve efficiency (col. 3, line 16, the quantum program synthesis techniques described here can be parallelized across many classical, quantum or hybrid (classical/quantum) resources in a computing system. And in some cases, multiple levels of optimization can be applied to utilize classical and quantum resources efficiently for solving optimization problems. Accordingly, in some cases, the techniques described here can improve the speed, efficiency and accuracy with which quantum resources are used to solve optimization problems).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chernoguzov et al. (US 20220414507 A1), which discusses positioning qubits within a quantum computing environment to reduce a time cost, and Pagageorge et al. (US 10540604 B1), which discusses a quantum processor organized in a layered structure and uses higher layer ancilla qubits for communicating between qubit clusters.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRISON CHAN YOUNG KIM whose telephone number is (571)272-0713. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CESAR PAULA can be reached at (571) 272-4128. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HARRISON C KIM/ Examiner, Art Unit 2145
/CESAR B PAULA/ Supervisory Patent Examiner, Art Unit 2145
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