Prosecution Insights
Last updated: July 17, 2026
Application No. 18/526,862

DISPLAY DEVICE

Non-Final OA §102§112
Filed
Dec 01, 2023
Priority
Dec 16, 2022 — RE 10-2022-0177434
Examiner
SUN, YU-HSI DAVID
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Display Co., Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
669 granted / 867 resolved
+9.2% vs TC avg
Moderate +8% lift
Without
With
+8.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
34 currently pending
Career history
888
Total Applications
across all art units

Statute-Specific Performance

§101
3.8%
-36.2% vs TC avg
§103
58.6%
+18.6% vs TC avg
§102
11.8%
-28.2% vs TC avg
§112
15.2%
-24.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 867 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species I in the reply filed on 3/9/2026 is acknowledged. Claims 5, 7, 8, and 11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/9/2026. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 18 recites the limitation "the second upper planarization layer" in line 2. There is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-4, 12, 16, 18 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by KIM et al. (US PG Pub 2023/0317762, hereinafter Kim). Regarding claim 1, figures 6 and 8 of Kim disclose a display device, comprising: a substrate (BSL) including a plurality of sub pixels (within display area DA, see figure 4); a first assembly line (TE1) and a second assembly line (TE2) which are disposed in the plurality of sub pixels on the substrate and are spaced apart from each other; a first upper planarization layer (BNK1) which is disposed on the first assembly line and the second assembly line; an opening (OPN) in the first upper planarization layer, the opening overlapping the first assembly line and the second assembly line; a light emitting diode (LD) which is disposed in the opening and includes a first electrode (CNE1) and a second electrode (CNE2) on the first electrode, the light emitting diode having a side surface and a top surface; a contact electrode (ELT1) which electrically connects with the first assembly line (TE1), the second assembly line (TE2), and the first electrode (CNE1) (TE1 and TE2 are electrically connected when the transistor is operating); and an organic (¶ 150) insulating layer which (INP) is disposed in a part of the opening and covers (blocks from the side) a part of the side surface of the light emitting diode (LD). Regarding claim 2, figures 6 and 8 of Kim disclose a part of the side surface of the light emitting diode (LD) is in contact with a first part of the organic insulating layer (INP), and another part of the side surface of the light emitting diode is in contact with the contact electrode (CNE1). Regarding claim 3, figures 6 and 8 of Kim disclose a second upper planarization layer (INS4) disposed on the light emitting diode and the organic insulating layer (INP), wherein the second upper planarization layer is in a part of the opening (OPN). Regarding claim 4, figures 6 and 8 of Kim disclose the opening includes an organic insulating layer opening, and wherein the second upper planarization layer (INS4) is in the organic insulating layer opening of the opening. Regarding claim 12, figures 6 and 8 of Kim disclose an area in which the side surface of the light emitting diode (LD) and the contact electrode (CNE1) are in contact with each other is smaller than an area in which the side surface of the light emitting diode and the first part are in contact with each other. Regarding claim 16, figures 6 and 8 of Kim disclose the organic insulating layer (INP) further includes a third part (lower portion) disposed below (lower than) the light emitting diode (LD). Regarding claim 18, figures 6 and 8 of Kim disclose the second upper planarization layer (INS4) is disposed on the contact electrode (ELT1) at the inside of the opening. Regarding claim 20, figures 6 and 8 of Kim disclose a display device, comprising: a substrate (BSL); a plurality of assembly lines (TE1, TE2) on the substrate and are spaced apart from each other; a first upper planarization layer (BNK1) on the plurality of assembly lines; an opening (OPN) in the first upper planarization layer; an organic insulating layer (INP); a light emitting diode (:D) disposed in the opening, the light emitting diode having a side surface; and a contact electrode (ELT1) disposed in the opening, wherein the contact electrode is disposed to contact with the plurality of assembly lines and the light emitting diode (TE1 and TE2 are electrically connected when the transistor is operating), and wherein the organic insulating layer overlaps (at an angle) with the plurality of assembly lines in the opening and is contact (indirectly, or in thermal contact) with the side surface of the light emitting diode. Allowable Subject Matter Claims 6, 9, 10, 13-15, 17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU-HSI D SUN/ Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Dec 01, 2023
Application Filed
Apr 09, 2026
Non-Final Rejection mailed — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
86%
With Interview (+8.5%)
2y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 867 resolved cases by this examiner. Grant probability derived from career allowance rate.

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