DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The prior art documents submitted by applicant in the Information Disclosure Statement(s) filed on January 6, 2025 have all been considered and made of record (note the attached copy(ies) of form PTO-1449).
Drawings
Twenty-four sheets of drawings were filed on December 1, 2023 and have been accepted by the examiner.
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The limitation “wherein the forming the mirror coating forms copper” is nonsensical. The examiner will treat the limitation to mean the mirror coating is “made of copper” which is consistent with the applicant specification (Para [0060]).
Appropriate corrections is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6-7, and 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al (US 2021/0215894 A1, herein “Huang”).
Claim 1. Huang discloses a method of manufacturing an optical device (Fig. 11), the method comprising:
patterning a first substrate (Fig. 11: 410) to form a recess with a sidewall (Fig. 11: within 410 a recess is formed wherein sidewalls 311 which protrudes from the bottom upward is considered part of the substrate as well);
forming a mirror coating on the sidewall (Fig. 11: reflector 309 is made of metal coating and is capable of functioning as a mirror; reflector 309 is located on top of bottom surface of 410 or 311);
depositing and patterning a material to form a first waveguide adjacent to the mirror coating (Fig. 11: 421a is located next to mirror 309; Para [0052]); and
bonding an optical interposer over the first waveguide (Fig. 11: layer 430 over 421a).
Claim 6. Huang discloses the method of claim 1, wherein the forming the mirror coating (Fig. 309) is made of copper (Para [0044]).
Claim 7. Huang discloses the method of claim 1, wherein the optical interposer (Fig. 11:430) is bonded to an electrical integrated circuit (Fig. 11: 440; Para [0058]).
Claim 15. Huang discloses an optical device (Fig. 11) comprising:
an optical interposer (Fig. 11: interconnect structure 430);
an electrical integrated circuit (Fig. 11: integrated circuit die 440 or planarized chip 440’) bonded to the optical interposer (interconnect structure 430 via molding material 445); and
a mirror structure (Fig. 11: 309/311/201’/410) bonded to the optical interposer (interconnect structure 430 via molding material 445 and the fully assembly the layers would necessitate bonding the interposer and the mirror structure together), the mirror structure (Fig. 11: 309/311/201/410; examiner would like to note the claimed mirror structure is a plurality components and not just reflective coating structure, hence structures 309/311/201’/410 all contains portions related to mirror component shown in Fig. 11) comprising:
a silicon substrate (Fig. 11: 410/311);
a mirror coating (309) along a sidewall of the silicon substrate (Fig. 11: 309 disposed along the bottom side wall of 410 within the cavity area or 309 is located along the top sidewall of 311); and
an edge coupler adjacent to the mirror coating (Fig. 11; waveguide 421b may function as an edge coupler because it is located on the edge and can couple light; optical fiber 500 also functions as an edge coupler because it is located on an edge for coupling light).
Claim 16. Huang discloses the device of claim 15, further comprising a through via (Fig. 11: 408; Para [0048]) extending through the mirror structure (Fig. 11: via 408 extends through 410 which is part of the mirror structure).
Claim 17. Huang discloses the device of claim 16, wherein the mirror structure (Fig. 11: 309/311/201’/410) further comprises an external connector in electrical connection with the through via (Fig. 11: 455 connected to via 408)
Claim 18. Huang discloses the method of claim 17, further comprising an interposer substrate bonded to the external connector (Fig. 11: 451).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 8-11, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Chen et al. (US 2021/0302654 A1, herein “Chen”).
Regarding Claims 2-4, Huang discloses the method of Claim 1, wherein Huang further teaches comprising forming a through via to make physical contact with the contact pad (Fig. 11: 408 and 411); and further comprising removing a portion of the first substrate to expose the contact pad (Fig. 11: 410 substrate is removed to create the through via, the hole / channel is then filled with 408. Substrate 410 has a bottom opening that was created through a removal process that allows 408 to make contact with 411; [0049]).
Huang does not teach further comprising forming a contact pad simultaneously with the mirror coating.
Chen teaches a method of making a photonic chip further comprising forming an interconnect layer (Fig. 2a: 2) that contains a recess and vertically coupling area 8, contacts pads (24a) within (optical IC 2) and the coupling area (optical features 8) which contain a grating layer are formed simultaneously. Although the grating features of 8 are not same as the mirror layer in Huang. They both related to method of depositing a metal layer for its formation (Para [0020]) which is similar process as Huang.
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify the method of Huang wherein both the reflector mirror coating and the contacts pads (411) are formed simultaneously similarly to what is disclosed by Chen (Para [0020]). This allows the manufacturing process to be speed up and increase the yield of production for the device by reduce the time needed.
Regarding claim 8, Huang discloses a method of manufacturing an optical device (Fig. 11), the method comprising: patterning a first substrate (Fig. 11: 410) to form a first recess (Fig. 11: recess that houses elements 201/ 309); applying a mirror coating (Fig. 1: 309; Para [0064]) along at least one sidewall of the first recess (along bottom sidewall of 410 in the recess or top surface of 311 which is also considered part of the substrate); and depositing a gap-fill material around the optical interposer (Fig. 11: 445 is filled around the top surface of the gap in 430; Para [0066]).
Huang does not disclose an optical interposer within the first recess wherein a waveguide within the optical interposer is aligned with the mirror coating.
Chen teaches an optical interposer layer (Fig. 2a: layer 26a-d) of which is removed to from the recess area (Fig. 2a: 28; Para [0019]). The dielectric that makes up 26a-d are then refilled within the first recess wherein a waveguide (16) within the optical interposer is aligned with the grating coupler coating 8 (Fig. 2a: 10, 16 and 8; Para [0019]) in order to protect the area from risk of contamination (Para [0019]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Huang to fill up the with interposer dielectric material to ensure the area does not remain expose and protected from environmental contamination. Further using similar dielectric materials to 26a-d will ensure the device of Chen have similar optical and electrical properties throughout the package such CTE, thermal, electrical and optical properties. Thus, using the solution taught by Chen, one can apply it to Huang and use the same dielectric interposer materials of 430 to fill in gaps or opening to obtain a similar result.
Regarding claim 9, Huang in view of Chen teach the method of Claim 8, wherein Huang further comprising removing a portion of the first substrate (Fig. 11: 410) to expose the optical interposer (Fig. 11: both layer 410 and 430 are removed and exposed to form the opening that houses 309).
Regarding claim 10, Huang in view of Chen teach the method of Claim 9, wherein Huang further comprising thinning a second substrate (a Planarizing process on layer 445 which houses 300a and 440 which means some portion of 445/300a/440 will be thinned out or removed) attached to the optical interposer (410) after the placing the optical interposer (430 on top of 410)
Regarding claim 11, Huang in view of Chen teach the method of Claim 8, wherein Huang further teaches comprising attaching a first support substrate (445) to the gap-fill material (Fig. 11: 445 placed on top of the recess at 309).
Regarding claim 14, Huang in view of Chen teaches the method of Claim 8, wherein Huang discloses the optical interposer (430) is bonded to an electronic integrated circuit (440) comprising a through device via (see via channel having interconnect elements within 430).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of McLaurin (US 12,191,626 B1, herein “McLaurin”).
Huang discloses the device of Claim 1 wherein a mirror coating is applied on sidewall within the recess or cavity (Fig. 11: 309).
Huang does not disclose wherein the metal coating is a distributed Braggs reflector.
McLaurin teaches the angled facets are coated with highly reflective coatings such as dielectric Distributed Bragg reflectors (DBRs). McLaurin further teaches the DBRs are provided to optimize the reflectance of the angled facets and prevent the facets degradation due to interaction with the light in the laser cavity with absorbing states associated with the facet surface (Fig. 12A-C, Col. 63, lines 47-65).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize DBRs has extremely high, wavelength-specific reflectivity, which significantly enhances the efficiency of light coupling and extraction in optoelectronic devices. One would be motivated to employ DBRs as the reflectors for all the features noted above, and for high wavelength selectivity to be coupled in and out of the waveguide and optoelectronic devices.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of the Chen (herein “Huang / Chen”) as applied to claim 11 above, and further in view of the Doany et al. (US 2013/0209026 A1, herein “Doany”).
Huang / Chen teach the method of Claim 11.
Huang / Chen do not teach wherein the first support substrate comprises a first lens and a second lens different from the first lens.
Doany teaches a photonic circuit packaging (Fig. 2) wherein the first support substrate (110) comprises a first lens (Fig. 1: 132) and a second lens (132) different from the first lens (the lenses are oriented different relative to vertical direction in order to collimate and focus base on the orientation of light exiting or entering the 110; Para [0046], thus making the lens different due to the functionality purpose; Para [0046]). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the channel of housing the reflector 309 in Huang to contain a vertical pair of lenses that oriented in a series configuration in order to collimate and focus light to improve coupling and transmission alignment (Para [0046]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Huang / Chen in view of Doany (herein “Huang / Chen / Doany”), as applied to claim 11 above, and further in view of Venkatesan et al. (US 2023/0176303 A1, herein “Venkatesan”).
Huang / Chen teach the method of Claim 11.
Huang / Chen do not teach wherein a lens is located on the 1st substrate and 2nd lens is located on 2nd substrate wherein the lenses are different.
Doany teaches a photonic circuit packaging (Fig. 2) wherein the first support substrate (110) comprises a first lens (Fig. 1: 132) and the second support substrate (Fig. 2a: block that houses fiber 114) contain a second lens (132) wherein the lenses are different (the lenses are oriented different relative to vertical direction in order to collimate and focus base on the orientation of light exiting or entering the 110; Para [0046], thus making the lens different due to the functionality purpose; Para [0046]). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the channel of housing the reflector 309 in Huang belong to substrate 200 to contain a lens while 2nd support substrate 100 contain a second lens in a vertical series manner similar to Doany. The vertical series lens configuration allows the device to collimate and focus light in order to improve coupling and transmission alignment (Para [0046]).
Huang / Chen / Doany do not teach bonding the first support substrate to a second support substrate prior to the attaching the first support substrate. The applicant disclosure described the “attaching” step as a step that requires the use of an adhesive (Applicant’s Patent Publication 2025/0044530US Para [0044]) while the bond process requires the use of thermal to ensure the two substrates stays bonded (Para [0048]).
Venkatesan teaches a FAU (fiber array unit having substrate block structure (Fig. 1b: 101a) being “attach” to a substrate (Fig. 1b: 150) using an adhesive; Para [0057]). Then adhesive is cured to make the ensure “bonding” occurs using UV light or a thermal process (Para [0057]). It would have been obvious to one of ordinary skill in the before the effective filing date to use the bonding process Venkatesan in combination with the process and orientation shown in Doany having two substrates with lens vertically aligned, in order to ensure the alignments stays fixed to each other during operation. The two steps of attach and bonding ensure the bond is provides for strong mechanical coupling between the two substrates.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Weng et al. (US 2022/0365273 A1, herein “Weng”).
Regarding claims 19-20, Huang discloses the method of claim 1.
Huang does not disclose further comprising an integrated fan-out substrate bonded to the external connector wherein the integrated fan-out substrate comprises a local silicon interconnect.
Weng teaches an interconnect carrier substrate (Fig. 1a: substrate within die 30) having a plurality of optical and electrical components disposed on it surface (Fig. 1a: 30 ; Para [0026]) the substrate of 30 has a plurality of bumps and connectors (Para [0312]) of which is coupled to an integrated fan-out substrate (Fig. 1a: 10 and Para [0020]) bonded to the external connector (104 and 312) wherein 10 is made of silicon materials (Para [0020]) and may have a fan-out configuration (Para [0020]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Huang wherein it can be further attached to fan-out substrate to allow the device to incorporate additional chips package such as the one shown in Fig. 1a of Weng. This allows the device to be integrated into more complex systems for more complex applications.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erin D Chiem whose telephone number is (571)272-3102. The examiner can normally be reached 10 am - 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A. Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIN D CHIEM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874