DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date as follows:
The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
The disclosure of the prior-filed applications, Application No. 17/978029, 17/219821, 16/512591 and 62/787012, fail to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application.
New claim 1 requires the conductive path to couple the first and second electrical contacts of the PCB through the substrate and the semiconductor die. Similarly, claim 16 requires the conductive path to couple the first and second electrical contacts of the PCB through the substrate and the first semiconductor die.
New claim 5 recites “a first wire bond, at least partially external to the semiconductor die, that couples the first conductive line with the trace; and a second wire bond, at least partially external to the semiconductor die, that couples the second conductive line with the trace.” Similarly, claim 18 “a first wire bond, at least partially external to the first semiconductor die, that couples the first conductive line of the substrate with the trace of the first semiconductor die; and a second wire bond, at least partially external to the first semiconductor die, that couples the second conductive line with the trace of the first semiconductor die.”
1) According to the applicant’s written description and drawings, the only structure of a conductive path that is through the substrate (230) and the semiconductor die (202a) is the embodiment depicted in Fig. 5A and 5B which shows TSVs (515 and 516) that are through the semiconductor die (202a). However, wire bonds (215, 216 / 315, 316) of the embodiment(s) depicted in Fig. 2A-3C are not through the semiconductor die (202a) as required by claim 1 and similarly claim 16.
2) The wire bonds (215, 216 / 315, 316) are disclosed as being completely external to the semiconductor die (202a). There is no support for the recitation of “at least partially” external with respect to the relationship between the wire bonds (215, 216 / 315, 316) and the semiconductor die (202a), because that scope covers more than that which applicant has possession (i.e. wire bonds partially within the semiconductor die).
Therefore, the subject matter of claims 5 and 18 as currently written is not supported.
New claims 10 and 20 each respectively recites newly added subject matter that is broader in scope than that of which the applicant had possession in any of the originally filed applications, by use of the term “conductive bond” in the claim. The disclosures only provide support for the specific structure of “bond pads” and “wire bonds” in the written description.
And in context of the recitation in the claim, the only elements disclosed as being through which the first electrical contact (236) of the substrate (230) is coupled with the trace (247) of the semiconductor die (202a) are the conductive line (218), contact (234) and wire bond (216) of Fig. 2; or the only elements disclosed as being through which the first electrical contact (336) of the substrate (330) is coupled with the trace (347) of the semiconductor die (302a) are the conductive line (318), contact (334) and wire bond (316) of Fig. 3; or the only elements disclosed as being through which the first electrical contact (236) of the substrate (230) is coupled with the trace (247) of the semiconductor die (202a) are the conductive line (218), contact (234), conductive bump (547), contact (548) and through substrate via (516) of Fig. 5. The applicant is not in possession of any and all conductive bonds. If the recitation was a typo, perhaps the term should read as either a “wire bond” or “conductive bump.” Claims 11-15 include the limitations and do not cure the deficiencies of claim 10. Claim 21 includes the limitations and do not cure the deficiencies of claim 20.
Therefore, the new subject matter added to claims 10-15, 20 and 21 as currently written is not supported.
Specification
The specification is objected to as failing to provide proper antecedent basis for the newly claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
The new subject matter directed to a “conductive bond” added to claims 10-15, 20 and 21 is not supported by the originally filed disclosure.
Claim Objections
Claims 10-15 are objected to because of the following informalities:
Claim 10 recites “through which the first electrical contact of the substrate is coupled the trace of the semiconductor die” and should read -- through which the first electrical contact of the substrate is coupled with the trace of the semiconductor die – in order to correct a grammatical issue. Claims 11-15 include the limitations and do not cure the deficiencies of claim 10.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 5, 10-15, 18, 20 and 21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
New claim 1 requires the conductive path to couple the first and second electrical contacts of the PCB through the substrate and the semiconductor die. Similarly, claim 16 requires the conductive path to couple the first and second electrical contacts of the PCB through the substrate and the first semiconductor die.
New claim 5 recites “a first wire bond, at least partially external to the semiconductor die, that couples the first conductive line with the trace; and a second wire bond, at least partially external to the semiconductor die, that couples the second conductive line with the trace.” Similarly, claim 18 “a first wire bond, at least partially external to the first semiconductor die, that couples the first conductive line of the substrate with the trace of the first semiconductor die; and a second wire bond, at least partially external to the first semiconductor die, that couples the second conductive line with the trace of the first semiconductor die.”
1) According to the applicant’s written description and drawings, the only structure of a conductive path that is through the substrate (230) and the semiconductor die (202a) is the embodiment depicted in Fig. 5A and 5B which shows TSVs (515 and 516) that are through the semiconductor die (202a). However, wire bonds (215, 216 / 315, 316) of the embodiment(s) depicted in Fig. 2A-3C are not through the semiconductor die (202a) as required by claim 1 and similarly claim 16.
2) The wire bonds (215, 216 / 315, 316) are disclosed as being completely external to the semiconductor die (202a). There is no support for the recitation of “at least partially” external with respect to the relationship between the wire bonds (215, 216 / 315, 316) and the semiconductor die (202a), because that scope covers more than that which applicant has possession (i.e. wire bonds partially within the semiconductor die).
Therefore, the subject matter of claims 5 and 18 as currently written is not supported.
Claims 10 and 20 each respectively recite newly added subject matter that is broader in scope than that of which the applicant had possession in the originally filed application, by use of the term “conductive bond” in the claim. The disclosure only provides support for the specific structure of “bond pads” and “wire bonds” in the written description.
And in context of the recitation in the claim, the only elements disclosed as being through which the first electrical contact (236) of the substrate (230) is coupled with the trace (247) of the semiconductor die (202a) are the conductive line (218), contact (234) and wire bond (216) of Fig. 2; or the only elements disclosed as being through which the first electrical contact (336) of the substrate (330) is coupled with the trace (347) of the semiconductor die (302a) are the conductive line (318), contact (334) and wire bond (316) of Fig. 3; or the only elements disclosed as being through which the first electrical contact (236) of the substrate (230) is coupled with the trace (247) of the semiconductor die (202a) are the conductive line (218), contact (234), conductive bump (547), contact (548) and through substrate via (516) of Fig. 5. The applicant is not in possession of the new breadth for any and all conductive elements in context of the relationship of disclosed elements. If the recitation was a typo, perhaps the term should read as either a “wire bond” or “conductive bump.” Claims 11-15 include the limitations and do not cure the deficiencies of claim 10. Claim 21 includes the limitations and do not cure the deficiencies of claim 20.
Therefore, the new subject matter added to claims 10-15, 20 and 21 as currently written is not supported.
Allowable Subject Matter
Claims 2-4, 6-9, 16, 17 and 19 are allowable.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 2, the prior art of record alone or in combination neither teaches nor makes obvious the invention of a system, comprising: a printed circuit board comprising a first electrical contact of a clock trace and a second electrical contact of the clock trace; a semiconductor device comprising a semiconductor die stacked on a substrate; and a conductive path that couples the first electrical contact of the clock trace with the second electrical contact of the clock trace through the substrate and the semiconductor die of the semiconductor device in combination with all of the limitations of Claim 2. Claims 3, 4 and 6-9 include the limitations of claim 2.
Regarding Claim 16, the prior art of record alone or in combination neither teaches nor makes obvious the invention of a system, comprising: a printed circuit board comprising a first electrical contact of a clock trace and a second electrical contact of the clock trace; a semiconductor device comprising a first semiconductor die stacked on a substrate and comprising a second semiconductor die stacked on the first semiconductor die; a conductive path that couples the first electrical contact of the clock trace with the second electrical contact of the clock trace through the substrate and the first semiconductor die of the semiconductor device; and an electrical connector that couples the second semiconductor die with a trace of the first semiconductor die that is part of the conductive path in combination with all of the limitations of Claim 16. Claims 17 and 19 include the limitations of claim 16.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896
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