DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of species A, fig. 5, claims 1-8 and 12-18, in the reply filed on 3/23/26 is acknowledged.
Claims 9-11 and 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/23/6.
Allowable Subject Matter
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 7, 12-14, 16 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin, et al., US Publication No. 2021/0318583 A1.
In a first interpretation-
Shin anticipates:
1. A display device comprising (see fig. 6 annotated below for claim 1; also see figs. 2-3):
a substrate (110) comprising a display area (DA) in which display elements are arranged;
a first subpixel circuit unit (SP) in the display area and comprising a first subpixel circuit (SP1), a second subpixel circuit (SP2), and a third subpixel circuit (SP3);
a first scan line (e.g. top horizontal portion of HGLn+1) extending in a first direction (e.g. x dir) from a side of the first subpixel circuit unit;
a second scan line (e.g. top horizontal portion of HGLn) extending in the first direction from another side of the first subpixel circuit unit;
a first branch line (e.g. vertical portion of HGLn+1) extending from the first scan line (e.g. top horizontal portion of HGLn+1) in a second direction (e.g. y dir) crossing the first direction; and
a first compensation line (e.g. bottom horizontal portion HGLn+1) extending in the first direction from the first branch line (e.g. vertical portion of HGLn+1) toward the first subpixel circuit (SP1)adjacent to the second scan line. See Shin at para. [0001] – [0137], figs. 1-16.
PNG
media_image1.png
844
826
media_image1.png
Greyscale
2. The display device of claim 1, wherein the first subpixel circuit (SP1) comprises:
a first thin-film transistor (e.g. labeled in fig. 6 above; ST at bottom of SP1) in the display area and comprising a first semiconductor layer (e.g. ACT, para. [0115]) and a first gate electrode (GE) insulated from the first semiconductor layer; and
a second thin-film transistor (e.g. labeled in fig. 6 above; ST at top of SP1) in the display area and comprising a second semiconductor layer (e.g. ACT, para. [0115) and a second gate electrode (GE) insulated from the second semiconductor layer.
3. The display device of claim 2, wherein a minimum distance in the second direction (e.g. y dir) between the first thin-film transistor (e.g. labeled in fig. 6 above; ST at bottom of SP1) and the second scan line (HGLn) is less than a minimum distance in the second direction between the second thin-film transistor (e.g. labeled in fig. 6 above; ST at top of SP1) and the second scan line (HGLn), fig. 6.
4. The display device of claim 1, wherein the first subpixel circuit (SP1) is adjacent to the second scan line (HGLn),
wherein the third subpixel circuit (SP3) is adjacent to the first scan line (HGLn+1+, and
wherein the second subpixel circuit (SP3) is between the first subpixel circuit (SP1) and the third subpixel circuit (SP3), fig. 6.
6. The display device of claim 2, wherein at least a portion of the first branch line (e.g. vertical portion of HGLn+1) is integrally formed in the second gate electrode (GE) of the second thin-film transistor (e.g. labeled in fig. 6 above; ST at top of SP1) (e.g. This feature is taught in fig. 9. For example, fig. 9 shows a cross-section along III-III in fig. 6. The gate electrode GE and HGLn is integrally formed.)
7. The display device of claim 1, wherein the first compensation line (e.g. bottom horizontal portion HGLn+1) is at a same layer as the first branch line (e.g. vertical portion of HGLn+1) and comprises a same material as a material of the first branch line, fig. 6
12. A display device comprising (see fig. 6 annotated below for claim 12; also see figs. 2-3; Note that there are a plurality of pixels SP in fig. 2 so another, adjacent set of SP1-SP3 is a second subpixel circuit unit. The another, adjacent set of SP1-SP3 also has the layout shown in fig. 6.):
a substrate (110) comprising a display area (DA) in which display elements are arranged;
a second subpixel circuit unit (another, adjacent SP) in the display area and comprising a first subpixel circuit (SP1), a second subpixel circuit (SP2), and a third subpixel circuit (SP3);
a first scan line (e.g. bottom horizontal portion HGLn+1) extending in a first direction (x dir) from a side of the second subpixel circuit unit;
a second scan line (e.g. bottom horizontal portion HGLn) extending in the first direction from another side of the second subpixel circuit unit;
a second branch line (e.g. vertical portion HGLn) extending from the second scan line in a second direction (y dir) crossing the first direction; and
a third compensation line (e.g. top horizontal portion HGLn) extending in the first direction from the second branch line (e.g. vertical portion HGLn) toward the third subpixel circuit (SP3) adjacent to the first scan line. See Shin at para. [0001] – [0137], figs. 1-16.
PNG
media_image2.png
875
841
media_image2.png
Greyscale
13. The display device of claim 12, wherein the third subpixel circuit comprises:
a third thin-film transistor (e.g. labeled in fig. 6; top ST of SP3) in the display area and comprising a third semiconductor layer (ACT) and a third gate electrode (GE) insulated from the third semiconductor layer; and
a fourth thin-film transistor (e.g. labeled in fig. 6; bottom ST of SP3) in the display area and comprising a fourth semiconductor layer (ACT) and a fourth gate electrode (GE) insulated from the fourth semiconductor layer, fig. 6.
14. The display device of claim 13, wherein a minimum distance in the second direction (y dir) between the third thin-film transistor (e.g. labeled in fig. 6; top ST of SP3) and the first scan line (HGLn+1) is less than a minimum distance in the second direction between the fourth thin-film transistor (e.g. labeled in fig. 6; bottom ST of SP3) and the first scan line (HGLn+1)
16. The display device of claim 13, wherein the second branch line (e.g. vertical portion HGLn) is integrally formed in the fourth gate electrode of the fourth thin-film transistor (e.g. labeled in fig. 6; bottom ST of SP3) (e.g. This feature is taught in fig. 9. For example, fig. 9 shows a cross-section along III-III in fig. 6. The gate electrode GE and HGLn is integrally formed.)
17. The display device of claim 13, wherein the third compensation line (e.g. top horizontal portion HGLn) is at a same layer as the second branch line (e.g. vertical portion HGLn) and comprises a same material as a material of the second branch line, fig. 6
Claim(s) 1, 2 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin, et al., US Publication No. 2021/0318583 A1.
In a second interpretation-
Shin anticipates:
1. A display device comprising (see fig. 6; also see figs. 2-3):
a substrate (110) comprising a display area (DA) in which display elements are arranged;
a first subpixel circuit unit (SP) in the display area and comprising a first subpixel circuit (SP1), a second subpixel circuit (SP2), and a third subpixel circuit (SP3);
a first scan line (e.g. top horizontal portion of HGLn+1) extending in a first direction (e.g. x dir) from a side of the first subpixel circuit unit;
a second scan line (e.g. top horizontal portion of HGLn) extending in the first direction from another side of the first subpixel circuit unit;
a first branch line (e.g. vertical portion of HGLn+1) extending from the first scan line (e.g. top horizontal portion of HGLn+1) in a second direction (e.g. y dir) crossing the first direction; and
a first compensation line (e.g. bottom horizontal portion HGLn+1) extending in the first direction from the first branch line (e.g. vertical portion of HGLn+1) toward the first subpixel circuit (SP1)adjacent to the second scan line. See Shin at para. [0001] – [0137], figs. 1-16.
2. The display device of claim 1, wherein the first subpixel circuit (SP1) comprises:
a first thin-film transistor (e.g. ST at top of SP1) in the display area and comprising a first semiconductor layer (e.g. ACT, para. [0115]) and a first gate electrode (GE) insulated from the first semiconductor layer; and
a second thin-film transistor (e.g. ST at bottom of SP1) in the display area and comprising a second semiconductor layer (e.g. ACT, para. [0115) and a second gate electrode (GE) insulated from the second semiconductor layer.
5. The display device of claim 2, wherein at least a portion of the first branch line (e.g. vertical portion of HGLn+1) is integrally formed in the first gate electrode (GE) of the first thin-film transistor (e.g. ST at top of SP1) (e.g. This feature is taught in fig. 9. For example, fig. 9 shows a cross-section along III-III in fig. 6. The gate electrode GE and HGLn is integrally formed.)
Claim(s) 1, 2 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin, et al., US Publication No. 2021/0318583 A1.
In a third interpretation-
Shin anticipates:
1. A display device comprising (see fig. 6; also see figs. 2-3):
a substrate (110) comprising a display area (DA) in which display elements are arranged;
a first subpixel circuit unit (SP) in the display area and comprising a first subpixel circuit (SP1), a second subpixel circuit (SP2), and a third subpixel circuit (SP3);
a first scan line (e.g. top horizontal portion of HGLn+1) extending in a first direction (e.g. x dir) from a side of the first subpixel circuit unit;
a second scan line (e.g. top horizontal portion of HGLn) extending in the first direction from another side of the first subpixel circuit unit;
a first branch line (e.g. vertical portion of HGLn+1) extending from the first scan line (e.g. top horizontal portion of HGLn+1) in a second direction (e.g. y dir) crossing the first direction; and
a first compensation line (e.g. bottom horizontal portion HGLn+1) extending in the first direction from the first branch line (e.g. vertical portion of HGLn+1) toward the first subpixel circuit (SP1)adjacent to the second scan line. See Shin at para. [0001] – [0137], figs. 1-16.
2. The display device of claim 1, wherein the first subpixel circuit (SP1) comprises:
a first thin-film transistor (e.g. ST at top of SP1) in the display area and comprising a first semiconductor layer (e.g. ACT, para. [0115]) and a first gate electrode (GE) insulated from the first semiconductor layer; and
a second thin-film transistor (e.g. labeled in fig. 6 above; ST at bottom of SP1) in the display area and comprising a second semiconductor layer (e.g. ACT, para. [0115) and a second gate electrode (GE) insulated from the second semiconductor layer.
8. The display device of claim 2, wherein the first compensation line (e.g. bottom horizontal portion HGLn+1) is between the second scan line (HGLn) and the first thin-film transistor (e.g. ST at top of SP1) and extends in the first direction (x dir) from the first branch line (e.g. vertical portion of HGLn+1)
Claim(s) 12, 13 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin, et al., US Publication No. 2021/0318583 A1.
In a fourth interpretation-
12. A display device comprising (see fig. 6; also see figs. 2-3; Note that there are a plurality of pixels SP in fig. 2 so another, adjacent set of SP1-SP3 is a second subpixel circuit unit. The another, adjacent set of SP1-SP3 also has the layout shown in fig. 6.):
a substrate (110) comprising a display area (DA) in which display elements are arranged;
a second subpixel circuit unit (another, adjacent SP) in the display area and comprising a first subpixel circuit (SP1), a second subpixel circuit (SP2), and a third subpixel circuit (SP3);
a first scan line (e.g. bottom horizontal portion HGLn+1) extending in a first direction (x dir) from a side of the second subpixel circuit unit;
a second scan line (e.g. bottom horizontal portion HGLn) extending in the first direction from another side of the second subpixel circuit unit;
a second branch line (e.g. vertical portion HGLn) extending from the second scan line in a second direction (y dir) crossing the first direction; and
a third compensation line (e.g. top horizontal portion HGLn) extending in the first direction from the second branch line (e.g. vertical portion HGLn) toward the third subpixel circuit (SP3) adjacent to the first scan line. See Shin at para. [0001] – [0137], figs. 1-16.
13. The display device of claim 12, wherein the third subpixel circuit comprises:
a third thin-film transistor (e.g. bottom ST of SP3) in the display area and comprising a third semiconductor layer (ACT) and a third gate electrode (GE) insulated from the third semiconductor layer; and
a fourth thin-film transistor (e.g. top ST of SP3) in the display area and comprising a fourth semiconductor layer (ACT) and a fourth gate electrode (GE) insulated from the fourth semiconductor layer, fig. 6.
15. The display device of claim 13, wherein the second branch line (e.g. vertical portion HGLn) is integrally formed in the third gate electrode of the third thin-film transistor (e.g. bottom ST of SP3) (e.g. This feature is taught in fig. 9. For example, fig. 9 shows a cross-section along III-III in fig. 6. The gate electrode GE and HGLn is integrally formed.)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini, can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Michele Fan/
Primary Examiner, Art Unit 2818
26 May 2026
