Prosecution Insights
Last updated: October 02, 2026
Application No. 18/527,145

METHOD AND A PROTOTYPE ELECTRONIC CIRCUIT FOR DESIGNING AN ELECTRONIC CIRCUIT

Non-Final OA §102
Filed
Dec 01, 2023
Priority
Dec 02, 2022 — provisional 63/429,876 +2 more
Examiner
TAT, BINH C
Art Unit
Tech Center
Assignee
Skyworks Solutions Inc.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
1072 granted / 1228 resolved
+27.3% vs TC avg
Moderate +14% lift
Without
With
+14.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
25 currently pending
Career history
1245
Total Applications
across all art units

Statute-Specific Performance

§101
24.2%
-15.8% vs TC avg
§103
1.3%
-38.7% vs TC avg
§102
63.8%
+23.8% vs TC avg
§112
0.5%
-39.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1228 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. DETAILED ACTION This office action is in response to application 18/527145 filed on 12/01/23. Summary of claims Claims 1-20 are pending. Claims 1-20 are rejected. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-20 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tero Tapio Ranta (US Pat. 9024700). As to claim 1 the prior art teaches a method for designing an electronic circuit the method comprising: providing a prototype electronic circuit comprising one or more capacitors and one or more other components, at least one of the one or more capacitors being a variable capacitor (see fig 4-5 col. 9 lines 33 to col. 10 lines 38); testing the electronic circuit by adjusting the capacitance of the one or more variable capacitors to determine one or more first capacitance values of the one or more variable capacitors that cause the electronic circuit to have one or more operating parameters that meet one or more desired operating parameters of the electronic circuit (see fig 4-6 col. 13 lines 7 to col. 14 lines 36); determining, based on the testing of the electronic circuit, capacitance values for one or more fixed-value capacitors to replace the one or more variable capacitors in the electronic circuit, each of the fixed-value capacitors having a second capacitance value equivalent to the first value of the corresponding variable capacitor (see fig 4-8 col. 14 lines 4 to col. 15 lines 60). As to claim 2 the prior art teaches wherein the electronic circuit is an amplifier circuit (see fig 1-3 col. 6 lines 4-48). As to claim 3 the prior art teaches wherein at least one of the desired operating parameters are defined as one or more fixed values, each of the fixed values having an error margin (see fig 5-7 col. 15 lines 40 to col. 16 lines 50). As to claim 4 the prior art teaches wherein the capacitance of at least one of the variable capacitors is adjusted to change a shunt capacitance of at least one part of the electronic circuit to cause the electronic circuit to have one or more operating parameters that meet one or more desired operating parameters of the electronic circuit (see fig 5-7 col. 16 lines 5 to col. 17 lines 40). As to claim 5 the prior art teaches wherein the capacitance of at least one of the variable capacitors is adjusted to change a series capacitance of at least one part of the electronic circuit to cause the electronic circuit to have one or more operating parameters that meet one or more desired operating parameters of the electronic circuit (see fig 5-8 col. 14 lines 20 to col. 15 lines 40). As to claim 6 the prior art teaches wherein at least one of the operating parameters is dependent on an internal capacitance of at least one component of the electronic circuit (see fig 5-7 col. 17 lines 30-65). As to claim 7 the prior art teaches wherein at least one of the operating parameters is dependent on at least one parasitic capacitance that exists between two parts of the electronic circuit (see fig 4-8 col. 18 lines 5 to col. 19 lines 30). As to claim 8 the prior art teaches wherein at least one of the operating parameters is dependent on at least one parasitic capacitance that exists between at least one part of the electronic circuit and an external device or an external component electrically connected to the at least one part of the electronic circuit (see fig 5-7 col. 14 lines 20 to col. 15 lines 30). As to claim 9 the prior art teaches wherein at least one of the operating parameters is dependent on at least one parasitic capacitance that exists between at least one part of the electronic circuit and a device or a component located adjacent to the at least one part of the electronic circuit (see fig 3-6 col. 12 lines 15 to col. 13 lines 50). As to claim 10 the prior art teaches wherein the operating parameters include at least one frequency at which at least one part of the electronic circuit oscillates, and the desired operating parameters include at least one desired frequency at which the at least one part of the electronic circuit oscillates (see fig 5-9 col. 18 lines 5-60). As to claim 11 the prior art teaches wherein at least one of the variable capacitors is configured to function as a decoupling capacitor for decoupling a first part of the electronic circuit from a second part of the electronic circuit (see fig 5-9 col. 18 lines 45 to col. 19 lines 40). As to claim 12 the prior art teaches wherein the first and second parts of the electronic circuits are coupled through a common impedance to a common power source (see fig 5-9 col. 19 lines 1-65). As to claim 13 the prior art teaches wherein at least one of the variable capacitors is configured to function as a decoupling capacitor for decoupling at least one part of the electronic circuit and an external device or an external component electrically connected to the at least one part of the electronic circuit (see fig 5-9 col. 17 lines 50 to col. 19 lines 20). As to claim 14 the prior art teaches wherein at least one of the variable capacitors is configured to function as a bypass capacitor to decouple an AC signal from a first part of the electronic circuit from a second part of the electronic circuit (see fig 5-9 col. 19 lines 40 to col. 20 lines 60). As to claim 15 the prior art teaches wherein at least one of the variable capacitors is configured to function as a bypass capacitor to decouple a voltage spike and/or a voltage dip from a first part of the electronic circuit from a second part of the electronic circuit (see fig 5-9 col. 20 lines 15 to col. 21 lines 45). As to claim 16 the prior art teaches wherein at least one of the variable capacitors has a variable capacitance between a first node and a second node, the variable capacitor including: a switch having a first terminal and a second terminal, an impedance between the first terminal and the second terminal being controllable via a first control node, the switch including two or more transistors (see fig 7-10 col. 22 lines 15 to col. 23 lines 50); a first capacitor coupled between the first terminal and the first node; and a second capacitor coupled between the second terminal and the second node (see fig 7-10 col. 23 lines 10 to col. 24 lines 20). As to claim 17 the prior art teaches wherein the capacitance of the variable capacitor is adjusted using a controller (see fig 5-9 col. 20 lines 5-60). As to claim 18 the prior art teaches wherein the controller is configured to automatically adjust the capacitance of the variable capacitor and determine the one or more first capacitance values of the one or more variable capacitors that cause the electronic circuit to have the one or more operating parameters that meet the one or more desired operating parameters of the electronic circuit (see fig 5-9 col. 18 lines 5-60). As to claim 19 the prior art teaches a method for designing an electronic circuit the method comprising: providing a prototype electronic circuit comprising one or more passive components and one or more active components, at least one of the one or more passive components having a variable value (see fig 4-5 col. 9 lines 33 to col. 10 lines 38); testing the electronic circuit by adjusting value of the one or more passive components to determine one or more first values of the one or more passive components that cause the electronic circuit to have one or more operating parameters that meet one or more desired operating parameters of the electronic circuit (see fig 4-6 col. 13 lines 7 to col. 14 lines 36); and determining, based on the testing of the electronic circuit, values for one or more fixed-value passive components to replace the one or more variable passive components in the electronic circuit, each of the fixed-value passive components having a second value equivalent to the first value of the corresponding variable passive component (see fig 4-8 col. 14 lines 4 to col. 15 lines 60). As to claim 20 the prior art teaches wherein the one or more fixed-value passive components include one or more capacitors, resistors, or inductors (see fig 4-6 col. 16 lines 5-60). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on flex 7:00Am-8PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /BINH C TAT/Primary Examiner, Art Unit 2851
Read full office action

Prosecution Timeline

Dec 01, 2023
Application Filed
Aug 11, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
99%
With Interview (+14.2%)
2y 6m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1228 resolved cases by this examiner. Grant probability derived from career allowance rate.

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