DETAILED ACTION
This action is responsive to the amendments filed December 22, 2025. Prior to amendment, claims 1-17 were pending. Claims 9-14 have previously been withdrawn due to restriction. Claims 1-2, and 15 have been amended. After entry, claims 1-17 are currently pending. Claims 1, and 15 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The amendments to the drawings are acknowledged and accepted. The objection to the drawings has been withdrawn.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 8, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Dwiveldi et al. (US 20140015562; “Dwiveldi” – of Record), in view of Huang (US 20070226529 – of Record), as supported by Razavi ("The Decision-Feedback Equalizer [A Circuit for All Seasons]"), and further in view of Penney (US 20190189184).
Regarding independent claim 1, Dwiveldi discloses a data sampling circuit, comprising:
a first signal path, arranged to receive a first signal, process and transmit the first signal (Fig. 1:20 self-compensating delay chain and its output signal "B". See also para. 56; "such that transmission of the data value over the reference delay path"),
the first signal path having a first delay comprising a first physical delay and a compensation delay (Fig. 3 where it illustrates physical delay elements 50, 52, 54, and 56, and the compensation delay elements 60 & 65);
and a second signal path, arranged to receive a second signal (Fig. 2 inverter delay chain receiving signal "IN"),
receive processed first signal from the first signal path (Fig. 1:30 comparison circuit receiving the signal from the first path "B"),
and sample the second signal according to the processed first signal (Fig. 1:30 comparison circuit. See also para. 66; "the signal B, this is used to sample the data input")
Dwiveldi is silent with respect to specific memory input signals and their respective paths.
However, Huang teaches wherein the first signal is a data strobe signal DQS and the second signal is a data signal DQ (Fig. 1 where it illustrates DQ and DQS signals as path inputs to sampling circuit 110. See also para. 4; "The delayed data signal DQX and compensated data strobe signal DQSX are then input to a flip flop 110, and the delayed data signal DQX is sampled");
the second signal path includes:
a first amplifier, a second amplifier, a simulation summer, and a slicer (Fig. 3 where it illustrates the circuits for the DQ path 104 and the sampler 110 circuits. See also para. 22; "The DQ path 104", "are simplified diagrams of internal circuits of the memory controller 300, each comprising individual pads, metal and buffers inducing various signal latencies." and "The flip flop 110 coupled to the DQ path 104 and delay element 108, samples the delayed data signal DQX". It is noted that the first and second amplifiers are analogous to buffers in Huang's DQ path. The slicer is indicated in the instant application to be a sampler and is analogous to 110 of Huang. Regarding the simulation summer, the instant application does not define the structure the circuit would have but merely describes its function as "arranged to receive the amplified data signal DQ and perform decision feedback equalization processing" (Spec. para. 50). Circuits and methods for performing "decision feedback equalizing" (or DFE) processing" are well understood in the prior art as supported by the numerous examples cited in Razavi);
the first amplifier, the second amplifier, the simulation summer, and the slicer are sequentially coupled to each other (Fig. 3 where it illustrates the circuits for the DQ path 104. It is noted that for the DQ signal to pass through the DQ path, the circuits comprising it would necessarily be sequentially coupled).
Dwiveldi and Huang combined do not disclose a DQS path which utilizes an explicit phase divider.
However, Penney teaches the first signal path comprises: a main path, wherein the main path includes:
a buffer, a phase divider, and a clock tree (Fig. 2 where it illustrates the buffer 53, the phase divider circuitry (60, 62. 64, 66, 68, and 70) driving output to a clock tree. It is noted that the term "clock tree" is only defined in in the instant application as "arranged to drive the plurality of data strobe sub-signals to avoid signal strength attenuation and to transmit the plurality of data strobe sub-signals to the slicer 204" (Spec. para. 49). Therefore, the term "clock tree" will be understood using the broadest reasonable interpretation to mean the routing of a clock signal to its receiving destination. Penney discloses that the DQS signal is a clock (para. 33 - " the DQS signals are used as clock signals") and therefore the routing path of the signals from the phase divider is necessarily a clock tree):
the buffer, the phase divider, and the clock tree are sequentially coupled to each other (Fig. 3 where it illustrates the components of the DQS signal path being sequentially coupled together);
Dwiveldi, Huang, and Penney combined are from the same field of endeavor as applicant’s invention directed to signal delay compensation circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Dwiveldi’s signal path and compensation delay path with Huang's DQ path and Penney's DQS path to compensate for PVT variability in memory signals. Doing so would improve timing margin thereby improving device operating speed.
Regarding claim 8, Dwiveldi, Huang as supported by Razavi, and Penney combined discloses the limitations of claim 1.
As applied, Huang further discloses wherein the first signal is a data strobe signal and the second signal is a data signal (Fig. 1 where it illustrates DQ and DQS signals as path inputs to sampling circuit 110. See also para. 4; "The delayed data signal DQX and compensated data strobe signal DQSX are then input to a flip flop 110, and the delayed data signal DQX is sampled").
Regarding independent claim 15, Dwiveldi discloses a memory, comprising at least one of a data sampling circuit, or a delay detection circuit (Fig. 12 where it illustrates a memory device including the data sampling circuit 840. See also para 86; "The monitoring circuitry of the above described embodiments can be used in a variety of devices where it is desirable to monitor the process characteristic of components within that device." and "A particular example use case is within a memory device such us shown schematically in FIG. 12"),
wherein the data sampling circuit comprises:
a first signal path, arranged to receive a first signal, process and transmit the first signal (Fig. 1:20 self-compensating delay chain and its output signal "B". See also para. 56; "such that transmission of the data value over the reference delay path"),
the first signal path having a first delay comprising a first physical delay and a compensation delay (Fig. 3 where it illustrates physical delay elements 50, 52, 54, and 56, and the compensation delay elements 60 & 65);
and a second signal path, arranged to receive a second signal (Fig. 2 inverter delay chain receiving signal "IN"),
receive processed first signal from the first signal path (Fig. 1:30 comparison circuit receiving the signal from the first path "B"),
and sample the second signal according to the processed first signal (Fig. 1:30 comparison circuit. See also para. 66; "the signal B, this is used to sample the data input");
Dwiveldi is silent with respect to specific memory input signals and their respective paths.
However, Huang teaches wherein the first signal is a data strobe signal DQS and the second signal is a data signal DQ (Fig. 1 where it illustrates DQ and DQS signals as path inputs to sampling circuit 110. See also para. 4; "The delayed data signal DQX and compensated data strobe signal DQSX are then input to a flip flop 110, and the delayed data signal DQX is sampled");
the second signal path includes:
a first amplifier, a second amplifier, a simulation summer, and a slicer (Fig. 3 where it illustrates the circuits for the DQ path 104 and the sampler 110 circuits. See also para. 22; "The DQ path 104", "are simplified diagrams of internal circuits of the memory controller 300, each comprising individual pads, metal and buffers inducing various signal latencies." and "The flip flop 110 coupled to the DQ path 104 and delay element 108, samples the delayed data signal DQX". It is noted that the first and second amplifiers are analogous to buffers in Huang's DQ path. The slicer is indicated in the instant application to be a sampler and is analogous to 110 of Huang. Regarding the simulation summer, the instant application does not define the structure the circuit would have but merely describes its function as "arranged to receive the amplified data signal DQ and perform decision feedback equalization processing" (Spec. para. 50). Circuits and methods for performing "decision feedback equalizing" (or DFE) processing" are well understood in the prior art as supported by the numerous examples cited in Razavi);
the first amplifier, the second amplifier, the simulation summer, and the slicer are sequentially coupled to each other (Fig. 3 where it illustrates the circuits for the DQ path 104. It is noted that for the DQ signal to pass through the DQ path, the circuits comprising it would necessarily be sequentially coupled).
Dwiveldi and Huang combined do not disclose a DQS path which utilizes an explicit phase divider.
However, Penney teaches the first signal path comprises: a main path, wherein the main path includes:
a buffer, a phase divider, and a clock tree (Fig. 2 where it illustrates the buffer 53, the phase divider circuitry (60, 62. 64, 66, 68, and 70) driving output to a clock tree. It is noted that the term "clock tree" is only defined in in the instant application as "arranged to drive the plurality of data strobe sub-signals to avoid signal strength attenuation and to transmit the plurality of data strobe sub-signals to the slicer 204" (Spec. para. 49). Therefore, the term "clock tree" will be understood using the broadest reasonable interpretation to mean the routing of a clock signal to its receiving destination. Penney discloses that the DQS signal is a clock (para. 33 - " the DQS signals are used as clock signals") and therefore the routing path of the signals from the phase divider is necessarily a clock tree):
the buffer, the phase divider, and the clock tree are sequentially coupled to each other (Fig. 3 where it illustrates the components of the DQS signal path being sequentially coupled together);
Dwiveldi, Huang, and Penney combined are from the same field of endeavor as applicant’s invention directed to signal delay compensation circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Dwiveldi’s signal path and compensation delay path with Huang's DQ path and Penney's DQS path to compensate for PVT variability in memory signals. Doing so would improve timing margin thereby improving device operating speed.
and the delay detection circuit comprises: (The delay detection circuit and it’s features are drawn to a non-elected group and are therefore not considered for examination purposes. As the claim construction indicates this feature in the alternate in the preamble, it is simply language given no patentable weight, but not objected to. It is suggested that this claim be amended to remove these features.)
Regarding claim 16, Dwiveldi, Huang as supported by Razavi, and Penney combined discloses the limitations of claim 15.
As applied, Penney further discloses wherein the memory is a dynamic random access memory (DRAM) (Fig. 1:10 memory device. See also para. 22; "the memory device 10 may be a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device").
Regarding claim 17, Dwiveldi, Huang as supported by Razavi, and Penney disclose the limitations of claim 16.
As applied, Penney further discloses wherein the DRAM conforms to a 5th double data rate synchronous dynamic random access memory (DDR5) memory specification (Fig. 1:10 memory device. See also para. 22; "the memory device 10 may be a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device").
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Dwiveldi et al. (US 20140015562; “Dwiveldi” – of Record) in view of Huang (US 20070226529 – of Record), as supported by Razavi ("The Decision-Feedback Equalizer [A Circuit for All Seasons]"), and further in view of Penney (US 20190189184), and further in view of Mencziger (US 6765836 – of Record).
Regarding claim 2, Dwiveldi, Huang as supported by Razavi, and Penney disclose the limitations of claim 1.
As applied, Dwiveldi further discloses wherein the first signal path comprises:
the main path, arranged to process and transmit the first signal, the main path having the first physical delay (Fig. 3 where it illustrates physical delay elements 50, 52, 54, and 56);
Dwiveldi, Huang and Penney combined are silent with respect to an explicit nature of the compensation characteristics.
However, Mencziger teaches and a compensation unit, coupled to the main path and arranged to receive at least one compensation signal from a compensation controller (Fig. 1:100 memory device which contains a temperature controlled delay device)
and generate the compensation delay in response to the at least one compensation signal (col. 5, ln. 27-31; "memory device 100, a time-dependent input clock signal Cin(t) is fed to the inventive synchronization device 10, which inventively contains a temperature-controlled delay device 20"),
wherein the at least one compensation signal is obtained according to at least one of a process angle, a voltage condition, or a temperature condition (Fig. 2:21 temperature sensor feeding control signal Vcntl to the voltage-controlled delay line 22).
Dwiveldi, Huang, Penney and Menczigar combined are from the same field of endeavor as applicant’s invention directed to signal delay compensation circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Dwiveldi, Huang and Penney physical delay path with the teachings of Mencziger’s compensation delay path to mitigate one or more sources of variation of critical signal paths. Doing so would improve circuit reliability and decrease the added design margin required.
Regarding claim 3, Dwiveldi, Huang as supported by Razavi, Penney and Mencziger combined disclose the limitations of claim 2.
As applied, Mencziger further discloses wherein the compensation controller comprises,
a temperature sensor (Fig. 2:21 temperature sensor),
and the at least one compensation signal comprises at least one temperature compensation signal (Fig. 2:21b);
and the at least one temperature compensation signal is obtained by the temperature sensor according to the temperature condition (Fig. 2:21 temperature sensor. See also col. 6, ln 17-22; "a temperature sensor 21 by which a control voltage Vcntrl is generated, which serves as a temperature signal T representing the operating temperature .theta., and which is supplied across an output terminal 21b of the temperature sensor 21 to the control terminal 22c of a voltage-controlled delay circuit 22").
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Dwiveldi et al. (US 20140015562; “Dwiveldi” – of Record) in view of Huang (US 20070226529 – of Record), as supported by Razavi ("The Decision-Feedback Equalizer [A Circuit for All Seasons]"), and further in view of Penney (US 20190189184), and further in view of Mencziger (US 6765836 – of Record), and further in view of Hinrichs (US 11171654 – of Record).
Regarding claim 4, Dwiveldi, Huang as supported by Razavi, Penney and Mencziger combined disclose the limitations of claim 2.
Dwiveldi, Huang, Penny and Mencziger combined are silent with respect to a load capacitor controlled by the compensation signal.
However, Hinrichs teaches wherein the compensation unit comprises:
at least one first load capacitor (Fig. 12:1230);
wherein a load connecting end of the at least one first load capacitor is connected to any position of the main path (Fig. 12:120 fine delay element with the load capacitor connected to the delay buffer and where it illustrates a plurality of those fine delay elements in a path in Figure 11);
and the at least one first load capacitor is arranged to receive the at least one compensation signal respectively (Fig. 11:1150 Decoder. See also col. 18, ln 19-21; "the decoder 1150 adjusts the delay of each delay device 1110-1 to 1110-W by adjusting the respective capacitive load");
be activated by triggering of the at least one compensation signal (Fig. 11:916 control input to decoder. It is noted that the compensation signal is only defined in the instant application as "obtained according to the PVT condition". Hence, any electrical signal from Menczigar's temperature sensor could be the control input to the decoder.)
and change a capacitance of the at least one first load capacitor, to generate the compensation delay (Fig. 12:1230 variable capacitor. See also col. 18, ln 40-44; "This allows the decoder 1150 to adjust the capacitive load at the output 1224 of the delay buffer 1220 (and hence the delay of the delay device 1210) by adjusting the capacitance of the variable capacitor 1230").
Dwiveldi, Huang, Penny and Mencziger combined along with Hinrichs are from the same field of endeavor as applicant’s invention directed to signal delay compensation circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Dwiveldi, Huang, Penny and Mencziger’s signal path and compensation delay path with Hinrichs variable load capacitors to fine tune the phase delay of a signal path. Doing so would further improve circuit reliability and decrease the added design margin required by making the timing self-correcting.
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Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Dwiveldi et al. (US 20140015562; “Dwiveldi” – of Record) in view of Huang (US 20070226529 – of Record), as supported by Razavi ("The Decision-Feedback Equalizer [A Circuit for All Seasons]"), and further in view of Penney (US 20190189184), and further in view of Mencziger (US 6765836 – of Record), and further in view of Yoshizawa et al. (US 20090225208; “Yoshizawa” – of Record)
Regarding claim 5, Dwiveldi, Huang as supported by Razavi, Penney, Mencziger and Hinrichs combined disclose the limitations of claim 4.
Dwiveldi, Huang, Penny, Mencziger and Hinrichs combined are silent with respect to explicit details about a capacitor subunit.
However, Yoshizawa teaches wherein each first load capacitor of the at least one first load capacitor comprises:
an input subunit, arranged to receive one compensation signal of the at least one compensation signal (Fig. 28: Control Signal)
and generate two control signals based on the compensation signal (Fig. 28: Control signal and it's compliment);
and a capacitor subunit, connected to the input subunit and arranged to be activated by triggering of the two control signals (Fig. 28 where it illustrates two transistors P1 and N1),
and change the capacitance of the first load capacitor (Fig. 28 where it illustrates the gate of the two transistors P1 and N1 as MOS varactors with a capacitance that changes).
Dwiveldi, Huang, Penny, Menczigar and Hinrichs combined along with Yoshizawa are from the same field of endeavor as applicant’s invention directed to signal processing circuits using controllable loading. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Dwiveldi, Huang, Penny, Mencziger’s and Hinrichs delay compensation structure using Yoshizawa’s variable load capacitors of the MOS varactor type. Doing so would increase the range of controlled load capacitance for the tunable delay element while reducing the circuit are required for the implementation.
Regarding claim 6, Dwiveldi, Huang, Penny, Menczigar, Hinrichs and Yoshizawa combined disclose the limitations of claim 5.
As applied, Yoshizawa further discloses wherein the input subunit comprises:
a first inverter, arranged to receive the compensation signal (para. 234; "The control signals are supplied from a control signal generating unit (not shown) that selectively outputs a control signal having a first level or a control signal having a second level." Because the control signal is driving MOS transistors, it is well understood in the art that the first or second levels are the analogous high and low voltage as is driven by a common inverting output stage. Thus, the output stage of the control signal generating unit can be considered the first inverter of the input subunit)
and output a first control signal of the two control signals (Fig. 28: Control signal);
and a second inverter, having an input end connected to an output end of the first inverter (Fig. 28: 164 inverter),
arranged to output a second control signal of the two control signals (Fig. 28 where it illustrates the node on the output of inverter 164).
Regarding claim 7, Dwiveldi, Huang, Penny, Menczigar, Hinrichs and Yoshizawa combined disclose the limitations of claim 6.
As applied, Yoshizawa further discloses wherein the capacitor subunit comprises:
a first metal oxide semiconductor (MOS) transistor, having a source and a drain both connected to the output end of the first inverter (Fig. 28: P1);
and a second MOS transistor, having a source and a drain both connected to an output end of the second inverter (Fig. 28: N1),
a gate of the second MOS transistor and a gate of the first MOS transistor being connected and both serving as the load connecting end of the first load capacitor (Fig. 28: where it illustrates the gate of P1 and N1 connected as the output of the circuit),
and a type of the second MOS transistor being opposite to that of the first MOS transistor (Fig. 28: P1 is a PMOS transistor and N1 is an NMOS transistor).
Response to Arguments
Applicant's arguments filed December 22, 2025, with respect to independent claims 1, and 15, have been fully considered but are not persuasive because, while the applicant's argument that the amendments narrowing the claim scope is not disclosed by the previously applied reference, the new features which required further consideration and search resulting in new references, remains unpatentable under a new ground of rejection.
Accordingly, all dependent claims also remain rejected.
Applicant's request for rejoinder of claims 9-14 is premature due to the outstanding obviousness rejections against the previously elected claims. The restriction requirement remains in place until all elected claims are found allowable. Additionally, it is noted that even in the case of allowability of the currently elected claims, the request for rejoinder would be denied because the withdrawn claims are not commensurate in scope and would still represent a patently distinct invention because they lack the specific limitations of the currently elected claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825