DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-25 are presented for examination.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on December 3, 2023; June 27, 2025; March 5, 2026; and May 27, 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The drawings are objected to because (a) Figs. 2 and 7 contain text written on a shaded background, see 37 CFR § 1.84(p)(3); and (b) Figures 4A-B and 5A contain text that is too small to be read without significant zooming, see id. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The use of the term BLUETOOTH (paragraph 74), which is a trade name or a mark used in commerce, has been noted in this application. The term should be accompanied by the generic terminology; furthermore, the term should be capitalized wherever it appears or, where appropriate, include a proper symbol indicating use in commerce such as ™, SM , or ® following the term.
Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) is permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks.
Claim Objections
Claim 5 is objected to because of the following informalities: “wherein a routing … are based” should be “wherein a routing … is based”.
Claim 6 is objected to because of the following informalities: “based on switched state” should be “based on a switched state”. Claims 7-10 are objected to for dependency on claim 6.
Claim 9 is objected to because of the following informalities: “a routing … are based” should be “wherein a routing … is based”.
Claim 25 is objected to because of the following informalities: “coupling between an x-check qubit and L-data qubit” should be “a coupling between an X-check qubit and a data qubit”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4-7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Sameti et al., “Superconducting Quantum Simulator for Topological Order and the Toric Code,” in 95 Physical Rev. A 042330 (2017) (“Sameti”) in view of Delfosse et al. (WO 2022139882) (“Delfosse”) and further in view of Kovalev et al., “Quantum Kronecker Sum-Product Low-Density Parity Check Codes with Finite Rate,” in 88 Physical Rev. A 012311 (2013) (“Kovalev”).
Regarding claim 1, Sameti discloses “[a] structure comprising:
a plurality of qubits (Sameti Fig. 3 discloses a set of physical qubits arranged on a torus);
a plurality of couplings between each qubits, wherein the couplings are arranged based on a relationship between each qubit and its placement on a torus, and wherein a coupling for each qubit comprises coupling to four nearest neighbor qubits on the torus (Sameti Fig. 3 discloses a set of physical qubits on a torus, each of which is coupled to four nearest neighbors (e.g., qubit 4 has qubits 1, 2, 5, and 6 for nearest neighbors)) ….”
Sameti appears not to disclose explicitly the further limitations of the claim. However, Delfosse discloses “coupling to two cross-coupled qubits based on a definition and a set of parameters of a bivariate … code (Delfosse Fig. 7A discloses a graph in which a Z-check qubit is coupled to several noncontiguous [i.e., cross-coupled; compare instant application Fig. 3C, ref. chars. 310-40] data qubits; paragraph 66 discloses that the graph is created by multiplying two classical linear codes together, each code containing data bits represented by circles and check bits represented by squares [i.e., the two variables are data bits and check bits and the values of those bits are the parameters], wherein a data bit multiplied by a data bit yields a data qubit, a check bit multiplied by a check bit yields a data qubit, a data bit multiplied by a check bit yields an X-basis check qubit, and a check bit multiplied by a data bit yields a Z-basis check qubit [where these four rules collectively correspond to the claimed definition]).”
Delfosse and the instant application both relate to quantum computing and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sameti to cross-couple the qubits based on a bivariate code, as disclosed by Delfosse, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would reduce the depth of the syndrome extraction circuit, thereby increasing the efficiency of the algorithm. See Delfosse, paragraphs 2, 62.
Neither Sameti nor Delfosse appears to disclose explicitly the further limitations of the claim. However, Kovalev discloses a “bicycle code (Kovalev sec. II(C) discloses bicycle codes).”
Kovalev and the instant application both relate to quantum error correction and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sameti and Delfosse to employ bicycle codes, as disclosed by Kovalev, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would provide good error-correction capability with a relatively simple mathematical code formulation. See Kovalev, sec. II(C).
Regarding claim 2, the rejection of claim 1 is incorporated. Sameti further discloses “a unit cell located on … the torus”, as shown in the rejection of claim 6.
Neither Sameti nor Kovalev appears to disclose explicitly the further limitations of the claim. However, Delfosse discloses that “a unit cell located on a grid … comprises a first data qubit, an X-check qubit, a second data qubit, and a Z-check qubit, wherein the unit cells are arranged such that four nearest neighbor qubits of either the first data qubit or second data qubit are two X-check qubits and two Z-check qubits (Delfosse Fig. 7A discloses a grid in which, inter alia, the sixth row and third column is a data qubit whose four nearest neighbors are two X-checks and two Z-checks; note that the square comprising rows 5-6 and columns 3-4 contains two data qubits, an X-check, and a Z-check and therefore satisfies the requirements of the claimed unit cell, with the lower-left data qubit of this square satisfying the claimed nearest-neighbor properties).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sameti and Kovalev to arrange the qubits such that data qubits have X-check and Z-check qubits for nearest neighbors, as disclosed by Delfosse, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow the system to perform convenient parity checks, thereby ensuring that errors do not propagate while reducing processing time to perform the error correction. See Delfosse, paragraph 2.
Regarding claim 4, Sameti, as modified by Delfosse and Kovalev, discloses that “the parameters of the bivariate bicycle code are [[144, 12, 12]] (Kovalev p. 9, Example 5 gives an example of a code whose parameters are [[2n1n2, 2k1k2, d0]], which resolves to [[144, 12, 12]] when, for instance, n1 = 2, n2 = 36, k1 = 3, k2 = 2, and d0 = 12).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sameti and Delfosse to employ bicycle codes, as disclosed by Kovalev, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would provide good error-correction capability with a relatively simple mathematical code formulation. See Kovalev, sec. II(C).
Regarding claim 5, the rejection of claim 1 is incorporated. Delfosse further discloses that “a routing for the two cross-couplings [is] based on a coupling table for the parameters of the bivariate … code (edges of Code 1 and Code 2 are also multiplied across each row and column of the product graph; for example, a vertical edge [routing for cross-couplings] is added at a like-position in every column of a table [coupling table], while a horizontal edge is added at a like-position in every row of the table – Delfosse, paragraph 67; note that the code is parameterized and bivariate per the mapping of claim 1 to Delfosse).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sameti to route couplings of the qubits according to a table, as disclosed by Delfosse, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would reduce the depth of the syndrome extraction circuit, thereby increasing the efficiency of the algorithm. See Delfosse, paragraphs 2, 62.
Neither Sameti nor Delfosse appears to disclose explicitly the further limitations of the claim. However, Kovalev discloses a “bicycle code (Kovalev sec. II(C) discloses bicycle codes).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sameti and Delfosse to employ bicycle codes, as disclosed by Kovalev, for substantially the same reasons as given in the rejection of claim 1.
Regarding claim 6, Sameti discloses “[a] method of performing an error check on a quantum architecture, wherein the quantum architecture comprises:
a plurality of qubits (Sameti Fig. 3 discloses a set of physical qubits arranged on a torus); [and]
a plurality of couplings between each [of the] qubits, wherein the couplings are arranged based on a relationship between each qubit and its placement on a torus, and wherein a coupling for each qubit comprises coupling to four nearest neighbor qubits on the torus (Sameti Fig. 3 discloses a set of physical qubits on a torus, each of which is coupled to four nearest neighbors (e.g., qubit 4 has qubits 1, 2, 5, and 6 for nearest neighbors)) ….”
Sameti appears not to disclose explicitly the further limitations of the claim. However, Delfosse discloses “coupling to two cross-coupled qubits based on a definition and a set of parameters of a bivariate … code (Delfosse Fig. 7A discloses a graph in which a Z-check qubit is coupled to several noncontiguous [i.e., cross-coupled; compare instant application Fig. 3C, ref. chars. 310-40] data qubits; paragraph 66 discloses that the graph is created by multiplying two classical linear codes together, each code containing data bits represented by circles and check bits represented by squares [i.e., the two variables are data bits and check bits and the values of those bits are the parameters], wherein a data bit multiplied by a data bit yields a data qubit, a check bit multiplied by a check bit yields a data qubit, a data bit multiplied by a check bit yields an X-basis check qubit, and a check bit multiplied by a data bit yields a Z-basis check qubit [where these four rules collectively correspond to the claimed definition]); …
wherein the error check comprises:
initializing a plurality of X-check qubits and Z-check qubits coupled to a first data qubit and a second data qubit (Delfosse Fig. 7A discloses X-check and Z-check qubits coupled to data qubits [note that, though the figure only couples Z-check qubits to data qubits, paragraph 69 indicates that the graph omits edges that would normally exist, including edges connecting X-check qubits to data qubits]);
performing a CNOT gate using each coupling of a first data qubit, and each coupling of a second data qubit (Delfosse paragraph 28 discloses that an entangling operation such as a CNOT gate is possible between a pair of qubits iff they are connected [coupled] by an edge in the graph; Fig. 7A discloses coupling of data qubits);
measuring each coupled X-check qubit used in each CNOT gate (in contrast to data qubits, ancilla qubits make up a second set of physical qubits that are used to measure values of stabilizers; ancillas used to measure X-type errors are X-type check qubits and ancillas used to measure Z-type errors are Z-type check qubits – Delfosse, paragraph 30; see also paragraph 37 (disclosing the performance of a projective measurement of the resulting eigenstate after performing CNOT operations)); and
measuring each coupled Z-check qubit used in each CNOT gate (in contrast to data qubits, ancilla qubits make up a second set of physical qubits that are used to measure values of stabilizers; ancillas used to measure X-type errors are X-type check qubits and ancillas used to measure Z-type errors are Z-type check qubits – Delfosse, paragraph 30; see also paragraph 37 (disclosing the performance of a projective measurement of the resulting eigenstate after performing CNOT operations)); and
determining an error based on [a] switched state of any of the X-check qubits or Z-check qubits (ancilla qubits are positioned to interact with data qubits such that it is possible to detect errors by measuring the ancilla qubits – Delfosse, paragraph 21 [note that an error is by definition a switched state]; see also paragraph 30 (disclosing that X-type check qubits are used to measure X-type errors and Z-type check qubits are used to measure Z-type errors)).”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sameti to cross-couple the qubits based on a bivariate code, as disclosed by Delfosse, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would reduce the depth of the syndrome extraction circuit, thereby increasing the efficiency of the algorithm. See Delfosse, paragraphs 2, 62.
Neither Sameti nor Delfosse appears to disclose explicitly the further limitations of the claim. However, Kovalev discloses a “bicycle code (Kovalev sec. II(C) discloses bicycle codes).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sameti and Delfosse to employ bicycle codes, as disclosed by Kovalev, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would provide good error-correction capability with a relatively simple mathematical code formulation. See Kovalev, sec. II(C).
Regarding claim 7, the rejection of claim 6 is incorporated. Sameti further discloses “a unit cell located on … the torus”, as shown in the rejection of claim 6.
Neither Sameti nor Kovalev appears to disclose explicitly the further limitations of the claim. However, Delfosse discloses that “a unit cell located on a grid … comprises a first data qubit, an X-check qubit, a second data qubit, and a Z-check qubit, wherein the unit cells are arranged such that four nearest neighbor qubits of either the first data qubit or second data qubit are two X-check qubits and two Z-check qubits (Delfosse Fig. 7A discloses a grid in which, inter alia, the sixth row and third column is a data qubit whose four nearest neighbors are two X-checks and two Z-checks; note that the square comprising rows 5-6 and columns 3-4 contains two data qubits, an X-check, and a Z-check and therefore satisfies the requirements of the claimed unit cell, with the lower-left data qubit of this square satisfying the claimed nearest-neighbor properties).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sameti and Kovalev to arrange the qubits such that data qubits have X-check and Z-check qubits for nearest neighbors, as disclosed by Delfosse, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow the system to perform convenient parity checks, thereby ensuring that errors do not propagate while reducing processing time to perform the error correction. See Delfosse, paragraph 2.
Regarding claim 9, the rejection of claim 6 is incorporated. Delfosse further discloses that “a routing for the two cross-couplings [is] based on a coupling table for the parameters of the bivariate … code (edges of Code 1 and Code 2 are also multiplied across each row and column of the product graph; for example, a vertical edge [routing for cross-couplings] is added at a like-position in every column of a table [coupling table], while a horizontal edge is added at a like-position in every row of the table – Delfosse, paragraph 67; note that the code is parameterized and bivariate per the mapping of claim 1 to Delfosse).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sameti to route couplings of the qubits according to a table, as disclosed by Delfosse, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would reduce the depth of the syndrome extraction circuit, thereby increasing the efficiency of the algorithm. See Delfosse, paragraphs 2, 62.
Neither Sameti nor Delfosse appears to disclose explicitly the further limitations of the claim. However, Kovalev discloses a “bicycle code (Kovalev sec. II(C) discloses bicycle codes).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sameti and Delfosse to employ bicycle codes, as disclosed by Kovalev, for substantially the same reasons as given in the rejection of claim 1.
Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Sameti in view of Delfosse and Kovalev and further in view of Park et al. (US 20160063378) (“Park”).
Regarding claim 3, the rejection of claim 2 is incorporated. Delfosse further discloses a “distance of the coupling for the two cross-coupled qubits (Delfosse Fig. 7A discloses a grid of qubits connected/coupled to other qubits not immediately adjacent to them [i.e., there is a greater than unit distance between them]) ….” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sameti/Kovalev to cross-couple qubits at a distance, as disclosed by Delfosse, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would save time by allowing for simultaneous measurements. See Delfosse, paragraph 71.
Neither Sameti, Kovalev, nor Delfosse appears to disclose explicitly the further limitations of the claim. However, Park discloses that “a Manhattan distance … is 9 (intersecting point may be computed as Max – Min = (6, 3), which has Manhattan distance 9 – Park, paragraph 63).”
Park and the instant application both relate to computing Manhattan distances and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sameti/Kovalev/Delfosse to compute a Manhattan distance with a value of 9, as disclosed by Park, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would provide a simple way to calculate distances along a grid. See Park, paragraph 63.
Regarding claim 8, the rejection of claim 7 is incorporated. Delfosse further discloses a “distance of the coupling for the two additional qubits (Delfosse Fig. 7A discloses a grid of qubits connected/coupled to other qubits not immediately adjacent to them [i.e., there is a greater than unit distance between them]) ….” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sameti/Kovalev to cross-couple qubits at a distance, as disclosed by Delfosse, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would save time by allowing for simultaneous measurements. See Delfosse, paragraph 71.
Neither Sameti, Kovalev, nor Delfosse appears to disclose explicitly the further limitations of the claim. However, Park discloses that “a Manhattan distance … is 9 (intersecting point may be computed as Max – Min = (6, 3), which has Manhattan distance 9 – Park, paragraph 63).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sameti/Kovalev/Delfosse to compute a Manhattan distance with a value of 9, as disclosed by Park, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would provide a simple way to calculate distances along a grid. See Park, paragraph 63.
Claims 20 and 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Sameti in view of Reagor (WO 2024050152) (“Reagor”).
Regarding claim 20, Sameti discloses “[a] structure comprising:
a qubit connectivity graph comprising a plurality of repeating unit cells of qubits and couplings (Sameti Fig. 3 discloses a lattice of qubits [qubit connectivity graph] comprising repeating rows of qubits 2-1-2-1, 3-4-3, 6-5-6-5, 7-8-7, and back to 2-1-2-1 and diagonal couplings between them);
a first unit cell comprising coupled qubits located on a surface of a … substrate (Sameti Fig. 3 discloses a lattice with multiple qubits [located on a substrate] comprising, inter alia, diagonally repeating qubits 7, 2, 1, and 3 coupled as depicted using the yellow diamonds [set of all 7/2/1/3 diamonds = first unit cell]); and
a second unit cell comprising coupled qubits located on the surface of the … substrate, wherein qubits of the first unit cell are located between qubits of the second unit cell (Sameti Fig. 3 discloses a lattice with multiple qubits [located on a substrate] comprising, inter alia, diagonally repeating qubits 4, 5, 6, and 8 coupled as depicted using yellow diamonds separated from the 7/2/1/3 diamonds by a green diamond and situated between the 7/2/1/3 diamonds [set of all 4/5/6/8 diamonds = second unit cell]).”
Sameti appears not to disclose explicitly the further limitations of the claim. However, Reagor discloses a “planar substrate (positions of qubit devices within a quantum processing unit may define two-dimensional spatial arrays in a quantum plane and may be located on a substrate – Reagor, paragraph 63) ….”
Reagor and the instant application both relate to quantum error correction and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sameti to place the qubits on a planar substrate, as disclosed by Reagor, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would decrease the complexity of the calculation by reducing the dimensionality of the spatial arrangement of the qubits. See Reagor, paragraph 63.
Regarding claim 22, Sameti, as modified by Reagor, discloses that “couplings of the first unit cell and the second unit cell are based on a qubit connectivity map created [on] a non-planar surface (Sameti Fig. 3 and caption disclose a lattice [qubit connectivity map] for minimal realization on a torus [non-planar surface] in which the 7/2/1/3 cells [first unit cell] are coupled to the 4/5/6/8 cells [second unit cell]).”
Regarding claim 23, Sameti, as modified by Reagor, discloses that “the non-planar surface is a torus (Sameti Fig. 3 and caption disclose a lattice [qubit connectivity map] for minimal realization on a torus [non-planar surface] in which the 7/2/1/3 cells [first unit cell] are coupled to the 4/5/6/8 cells [second unit cell]).”
Regarding claim 24, Sameti, as modified by Reagor, discloses that “the unit cells are overlapping (see mapping of claim 20 to Sameti and Fig. 3 thereof and note that, going diagonally from top left to bottom right, a 7/2/1/3 cell abuts a 4/5/6/8 cell, which abuts a 7/2/1/3 cell, etc. [i.e., the 7/2/1/3 cells alternate with the 4/5/6/8 cells, so the set of all 7/2/1/3 cells overlaps with the set of all 4/5/6/8 cells on the diagonal line going from top left to bottom right Sameti Fig. 3 and caption disclose a lattice [qubit connectivity map] for minimal realization on a torus [non-planar surface] in which the 7/2/1/3 cells [first unit cell] are coupled to the 4/5/6/8 cells [second unit cell]]).”
Claims 21 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Sameti in view of Reagor and further in view of Delfosse.
Regarding claim 21, the rejection of claim 20 is incorporated. Sameti further discloses “repeating unit cells”, as shown above in the rejection of claim 20.
Neither Sameti nor Reagor appears to disclose explicitly the further limitations of the claim. However, Delfosse discloses that “the …unit cell[] comprise[s] a first data qubit, an X-check qubit, a second data qubit, and a Z-check qubit, wherein the unit cell[ is] arranged such that four nearest neighbor qubits of either the first data qubit or second data qubit are two X-check qubits and two Z-check qubits (Delfosse Fig. 7A discloses a grid in which, inter alia, the sixth row and third column is a data qubit whose four nearest neighbors are two X-checks and two Z-checks; note that the square comprising rows 5-6 and columns 3-4 contains two data qubits, an X-check, and a Z-check and therefore satisfies the requirements of the claimed unit cell, with the lower-left data qubit of this square satisfying the claimed nearest-neighbor properties).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sameti and Reagor to arrange the qubits such that data qubits have X-check and Z-check qubits for nearest neighbors, as disclosed by Delfosse, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow the system to perform convenient parity checks, thereby ensuring that errors do not propagate while reducing processing time to perform the error correction. See Delfosse, paragraph 2.
Regarding claim 25, Sameti, as modified by Reagor and Delfosse, discloses that “[a] coupling between an [X]-check qubit and [a] data qubit is routed past a qubit of the second unit cell (Delfosse Fig. 7A shows, for instance, a coupling between a Z-check qubit at row 2, column 4 coupled to a data qubit at row 5, column 4 that skips over [i.e., is routed past] the data qubits at rows 3 and 4, column 4; paragraph 69 indicates that not all edges are depicted for clarity [i.e., there is, in general, an equivalent connection between an X-check qubit and a non-adjacent data qubit]).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sameti/Reagor to route a coupling between a check qubit and a data qubit past another qubit, as disclosed by Delfosse, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow the system to perform convenient parity checks, thereby ensuring that errors do not propagate while reducing processing time to perform the error correction. See Delfosse, paragraph 2.
Allowable Subject Matter
Claims 11-19 are allowed. Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: None of the prior art of record appears to disclose explicitly at least the following limitations of independent claim 11, when considered in combination with the remainder of the claim:
swapping positions of qubits on the planar surface while maintaining the couplings from the qubit connectivity map;
determining a device layout by placing qubits according to locations on the planar surface and couplers between the qubits corresponding to the coupling map; [and]
changing a wiring level of a coupler in the device layout based on a physical overlap with another coupler.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN C VAUGHN whose telephone number is (571)272-4849. The examiner can normally be reached M-R 7:00a-5:00p ET.
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/RYAN C VAUGHN/ Primary Examiner, Art Unit 2125
