Prosecution Insights
Last updated: October 02, 2026
Application No. 18/527,383

INSPECTION METHOD AND RELATED INSPECTION DEVICE FOR OUT-OF-ORDER EXECUTION CENTRAL PROCESSING UNIT CIRCUIT

Non-Final OA §101§112
Filed
Dec 04, 2023
Priority
May 11, 2023 — TW 112117495
Examiner
KIK, PHALLAKA
Art Unit
Tech Center
Assignee
Realtek Semiconductor Corporation
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
875 granted / 964 resolved
+30.8% vs TC avg
Minimal +2% lift
Without
With
+1.6%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
14 currently pending
Career history
972
Total Applications
across all art units

Statute-Specific Performance

§101
32.2%
-7.8% vs TC avg
§103
16.7%
-23.3% vs TC avg
§102
26.3%
-13.7% vs TC avg
§112
9.2%
-30.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 964 resolved cases

Office Action

§101 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action responds to the Application and IDS filed on 12/04/2023. Claims 1-14 are pending. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention, wherein it is not clear what is being inspected. Based on claim 8 and Applicant specification (see paragraphs [0070], [0029]), it seems that the inspection method is part of the method for validation property of the to-be inspected circuit (i.e., circuit design which are expressed in the forms of finite sate graph and at least a logic expression). Applicant may want to insert –to validate property of a to-be inspected circuit expressed in terms of a finite state graph and at least a logic expression, the method—should be inserted after “circuit,” (line 2) to clearly define what this method is inspecting. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-7 are rejected under 35 U.S.C. 101 because the claimed invention lacks patentable utility, wherein it is not understood what the inspecting method is inspecting (see 112 rejections of claims 1-7 above). Applicant may want to insert –to validate property of a to-be inspected circuit expressed in terms of a finite state graph and at least a logic expression, the method—should be inserted after “circuit, ” (line 2) to clearly define what this method is inspecting and provide for the proper utility as part of circuit design validation/verification process. Allowable Subject Matter Claims 8-14 are allowed. Claims 1-7 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, and 101 rejections set forth in this Office action. The following is a statement of reasons for the indication of allowable subject matter: As per claims 1-14, the independent claims 1 and 8, from which the respective claims depend, recite the inspection method/device for an out-of-order execution processing circuit comprising a combination of inventive steps/operations comprising: determining that a refill request is not sent by a data cache unit of the out-of-order execution processing circuit before an exception commitment triggered by a permission check failure of the out-of-order execution processing circuit; and determining a key data is not read by a load-store unit of the out-of-order execution processing circuit and the key data is not utilized by a calculation unit of the out-of-order execution processing circuit before the exception commitment triggered by the permission check failure of the out-of-order execution processing circuit, as claimed, which the prior arts made of record failed to teach or suggest as claimed. Furthermore, under the 2019 Patent Eligibility Guideline, the claims are directed to patent eligible subject matter because (1) under Step 1, the claims are directed to a process and a machine, respectively; (2) under Step 2A, Prong One, the claims are not directed to mathematical concepts comprising mathematical relationships, mathematical formulas or equations, and mathematical calculations since no expressed equation or formula is recited in the claims; nor are the claims directed to a mental process since one of ordinary skilled in the art at the time of the filing of the invention, would NOT reasonably be able to perform the method mentally since the calculations would involve large amount of data associated with the electronic design, as normally found in the art of computer-aided design and analysis of circuits; nor are the claims directed to certain methods of organizing human activity, wherein per claims 1-7, presuming claim 1 is amended as suggested above to provide for the necessary patentable utility as part of the circuit design verification process. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHALLAKA KIK whose telephone number is (571)272-1895. The examiner can normally be reached Maxiflex Mon-Fri 8:30AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 5712727483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Any response to this action should be mailed to: Commissioner for Patents P. O. Box 1450 Alexandria, VA 22313-1450 or faxed to: 571-273-8300 /PHALLAKA KIK/Primary Examiner, Art Unit 2851 September 4, 2026
Read full office action

Prosecution Timeline

Dec 04, 2023
Application Filed
Sep 10, 2026
Non-Final Rejection mailed — §101, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
92%
With Interview (+1.6%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 964 resolved cases by this examiner. Grant probability derived from career allowance rate.

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